JPH0562994A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable an n<-> layer to be formed only on the drain of an LDD transistor without using a photolithography process by a method wherein a contact is formed so as to overlap a side wall formed on the side wall of a gate section. CONSTITUTION:An n<-> layer 105 is formed using a gate electrode 104 as a mask, and then a side wall 106 is formed. Next, a first n<+> layer 107 is formed using the side wall 107 and the gate electrode 104 as a mask, and an insulating film 108 is formed on the whole surface after a heat treatment is carried out. Then, contacts 109 and 109a are formed on a drain 115 and a source 116 respectively. At this point, the contact 109a provided to the source 116 is bored at a point so as to overlap a gate section. Then, impurities are injected into the first n<+> 107 through the contacts 109 and 1O9a for the formation of a second n<+> layer 110. An n<-> layer of high resistance is completely eliminated by the formation of the second n<+> layer 110, and the contact 109a is connected with the second n<+> layer 110 of low resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which an n ^- layer is formed only on the drain side of a transistor having an LDD (Lightly Doped Drain) structure without using a photolithography process. is there.

[0002]

2. Description of the Related Art Conventionally, in order to prevent a hot carrier effect, a transistor having an LDD structure (hereinafter referred to as an LDD transistor) has been widely used.

However, in this LDD transistor, the concentration of the n ⁻ layer is lowered to relax the electric field, so that the resistance of the n ⁻ layer deteriorates the performance of the LDD transistor and lowers the circuit performance. There is.

As a device for eliminating this performance deterioration, "the 17th Conference on Solid State Devices and M
aterials Tokyo, 1985, PP25-28 ”. In this method, considering the resistance R _S following the source side and the resistance R _D following the drain side, it is the resistance R _S that greatly contributes to the circuit performance.

In order to reduce the resistance R _S , the conventional LDD transistor forming method using sidewalls is not used,
The n ⁻ layer is formed only on the drain side by photolithography technology (hereinafter referred to as photolithography).

By using this method, the source side becomes a high-concentration diffusion layer, the resistance R _S is reduced, and the n ⁻ layer is formed on the drain side, so that the effect of relaxing a high electric field is the same as before. , I can expect it.

[0007]

However, in the above method, an increase in cost and a decrease in yield due to an increase in the photolithography process are unavoidable.

Further, in the future, if the gate length becomes further smaller, the photolithography technique will become difficult, so that the miniaturization cannot be expected.

Further, the size of the n ⁻ layer changes due to the misalignment at the time of alignment, so that there is a problem that the electric field relaxation effect with respect to the hot carrier effect is not constant, and a technically satisfactory product is obtained. I couldn't do it.

Among the problems of the above-mentioned prior art, the present invention causes an increase in cost due to an increase in the photolithography process, and a change in the length of the n ^- layer due to a decrease in yield and variations in the photolithography process. The present invention provides a method for manufacturing a semiconductor device that solves the problem that the performance of an LDD transistor and the resistance to the hot carrier effect change.

[0011]

In order to solve the above-mentioned problems, the present invention provides a method of manufacturing a semiconductor device, wherein a sidewall is formed on a sidewall of a gate electrode and a gate oxide film, and the sidewall is used as a mask. A step of forming an insulating film after forming a diffusion layer on a semiconductor substrate by ion implantation, and opening a hole in the insulating film to form a contact on the source side so as to overlap the drain side and the gate electrode or at least the sidewall. Introducing a step of injecting impurities into the diffusion layer through the contact and a step of forming an oxidized portion in the gate electrode exposed at the surface of the diffusion layer and the contact on the source side.

[0012]

According to the present invention, since the steps described above are introduced in the method of manufacturing a semiconductor device, sidewalls are formed on the sidewalls of the gate electrode and the gate oxide film, and the sidewalls are used as a mask. A diffusion layer is formed by implanting ions into the semiconductor substrate, an insulating film is formed on the entire surface, and holes are formed on the drain and source sides of this insulating film.
Form contacts respectively.

The contact on the drain side is left at the normal contact position, but the contact on the source side is formed at a position overlapping the gate electrode or at least the side wall, and impurities are injected into the diffusion layer through this contact, By forming an oxide film on the portion of the source-side gate electrode exposed to the contact, the source-side diffusion layer can be removed, and therefore the above-mentioned problem can be eliminated.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. Prior to description of specific examples of the manufacturing method, first, the structure of a semiconductor device obtained by the manufacturing method of the present invention will be described.

FIG. 3 is a sectional view of a semiconductor device (LDD transistor) obtained by the manufacturing method of the present invention.
FIG. 4 is a plan view thereof. 3 and 4, a film oxide film 102 is formed on a semiconductor substrate 101 to form an element region and an isolation region, and a gate electrode 103 is formed on the semiconductor substrate 101 in this element region via a gate oxide film 103. 104 is formed.

Ion implantation of phosphorus or the like is performed on the semiconductor substrate 101 using the gate electrode 104 as a mask to form an n ⁻ layer 105, and then an oxide film is formed and patterned to form the gate oxide film 103. , Gate electrode 1
A sidewall 106 is formed on the sidewall of 04.

Using the side wall 106 as a mask, ion implantation of impurities such as arsenic is performed, and the first n ⁺
The layer 107 is formed, and thereafter, heat treatment for activation is performed to form an insulating film 108 on the surface. As shown in FIGS. 3 and 4, the contact 109 is formed on the drain side 115.
Has a hole.

The contact 109 on the drain side 116
Is formed at the same position as the conventional contact, whereas the contact 109a on the source side 116 is formed so as to overlap with the sidewall 106. Impurities are injected through the contacts 109 and 109a to form the second contact.
Although the n ⁺ layer 110 is formed, the contact 109a is opened by overlapping the sidewalls 106 by implanting the impurity through the contact 109a on the source side 116. Therefore, the n ⁻ layer on the source side is implanted with this impurity. Is gone by. Therefore, the parasitic resistance is correspondingly reduced, and a structure in which the performance of the LDD transistor is not deteriorated can be obtained.

Further, on the drain side 115, the n ⁻ layer 105 utilizing the side wall 106 remains as it is, so that sufficient resistance to the hot carrier effect is secured.

The n ⁻ layer 105 is completely removed, and the resistance R
_In order to reduce _S , it is possible to bring the gate electrode 104 and the contact 109a close to each other,
At this time, the sidewall oxide film 111 is left on the gate portion exposed at the contact 109a, so that a short circuit between the power supply 104 and the contact 109b can be prevented.

FIG. 5 is a plan view of another semiconductor device obtained by the manufacturing method of the present invention. In FIG. 5, the same parts as those in FIGS. 3 and 4 are allotted with the same reference numerals.
The description will focus on parts different from those in FIGS.

As is apparent from a comparison of FIG. 5 with FIGS. 3 and 4, in FIG.
9a completely covers the gate part, and the gate part has n
^- the layer does not exist at all, only the 2n ⁺ layer 110, a small state of least resistance R _S.

Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. Also in FIGS. 1A to 1C, the same parts as those in FIGS. 3 to 5 are denoted by the same reference numerals. The embodiment shown in FIGS. 1A to 1C shows a manufacturing method when the gate portion and the contact 109a on the source side 116 overlap each other.

First, as shown in FIG. 1A, a field oxide film 1 is formed on a semiconductor substrate 101 by a selective oxidation method.
02 is formed to form an element region and an isolation region.

Next, a gate oxide film 103 is formed on the semiconductor substrate 101 in the element region by a thermal oxidation method, and further,
After depositing polysilicon by a CVD method, impurities (for example, phosphorus) are diffused in order to have conductivity,
The gate electrode 104 is formed by patterning by the photolithographic etching technique.

Then, using the gate electrode 104 as a mask, phosphorus is implanted by an implantation technique to form an n ⁻ layer 105.

Next, an oxide film is deposited, and the sidewall 106 having a desired pattern is formed by the whole surface reactive ion etching technique.

Next, using the sidewall 106 and the gate electrode 104 as a mask, for example, arsenic is implanted into the semiconductor substrate 101 by an implantation technique,
The first n ⁺ layer 107 is formed.

Then, after heat treatment for activation, the insulating film 108 is subjected to CVD (Chemical Vapor Depositio).
n) Formed on the entire surface by technology. The above-mentioned steps until the LDD transistor is obtained are conventional known techniques.

Next, by the photolithographic etching technique,
As shown in FIG. 1B, contacts 109 and 109a are formed on the drain side 115 and the source side 116, respectively. At this time, the contact 109 on the drain side 115 is opened at a normal position outside the sidewall 106, and the contact 109a on the source side 116 is opened at a position overlapping the gate portion.

[0031] Thereafter, a contact 109 of the drain side 115, through the contact 109a of the source 116, to the 1n ⁺ layer 107, the second 1n ⁺ layer 107 and impurities of the same conductivity type first 1n ⁺ layer 107 approximately equal or Implantation is performed by an implantation technique with a higher concentration to form the second n ⁺ layer 110.

Next, a heat treatment for activation is performed, and the atmosphere at this time is set to an oxygen atmosphere, so that the source side 1
The gate electrode 104 on the source side exposed at the contact 109a of 16 is oxidized and the second n ⁺ layer 11 is formed.
The 0 surface is also oxidized. Thus, the oxide film 111 is formed.

Due to the formation of the second n ⁺ layer 110, the high resistance n ⁻ layer on the source side 116 is completely eliminated, and the low resistance second n ⁺ layer 110 is connected to the contact 109a. In this case, the contact 10 on the drain side 115
9 is perforated in the normal position and the n ⁻ layer 105 is the second
Since it is not affected by the n ⁺ layer 110, it is expected that the resistance to the hot carrier effect is about the same as that of a normal LDD transistor.

After that, as shown in FIG. 1C, the oxide film 1 on the surface of the second n ⁺ layer 110 is etched back by the entire surface.
After removing 11 and sputtering an Al alloy, a desired metal wiring 112 is formed by a photolithographic etching technique.

Next, a second embodiment of the manufacturing method of the present invention will be described with reference to FIG. This FIG. 2 (a), FIG.
1B is a process sectional view of the second embodiment, and FIG.
The same parts as those in FIG. 1C are designated by the same reference numerals, and the description of the same steps will be omitted.

In FIG. 2 (a), FIG. 1 (a) -FIG.
Instead of obtaining the oxide film 111 described in (c) by the thermal oxidation method, the oxide film 111 on the sidewall is formed by the CVD method, and thereafter, as shown in FIG. The sidewall oxide film 113 is formed by etching.

The sidewall oxide film 113 is formed by forming the contacts 109 and 109a, depositing an oxide film, and then anisotropically etching the entire surface of the contact 10.
The oxide film may be left only on the side walls of 9,109a.

Further, although all of the above-mentioned respective embodiments are examples of the N-Ch type LDD transistor, the P-Ch type LD is used.
The same effect can be expected with the D transistor.

[0039]

As described above in detail, according to the present invention, only the contact on the source side overlaps the gate portion, but the contact is formed so as to overlap at least the sidewall formed on the side wall of the gate portion. By implanting impurities through the contact to form a diffusion layer, the high resistance diffusion layer on the source side is completely removed without using a photolithography process, and the high resistance diffusion layer on the drain side is resistant to the hot carrier effect. Resistance is stable,
An LDD transistor with excellent reliability can be formed.

Further, since the high resistance diffusion layer on the source side is completely removed, it is possible to obtain an LDD transistor without performance deterioration due to source side odd resistance.

[Brief description of drawings]

FIG. 1 is a process sectional view of an embodiment of a method of manufacturing a semiconductor device of the present invention.

FIG. 2 is a process sectional view of another embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor element obtained by the method of manufacturing a semiconductor element of the present invention.

FIG. 4 is a plan view of the same semiconductor device.

FIG. 5 is a plan view of another semiconductor element obtained by the method for manufacturing a semiconductor element of the present invention.

[Explanation of symbols]

101 semiconductor substrate 102 field oxide film 103 gate oxide film 104 gate electrode 105 n ⁻ layer 106 sidewall 107 first n ⁺ layer 108 insulating film 109 contact 109a contact 110 second n ⁺ layer 111 oxide film 112 metal wiring 113 sidewall oxide film

Claims (1)

[Claims] 1. A step of forming a field oxide film on a semiconductor substrate to form an element region and an isolation region, and after forming a gate electrode on the semiconductor substrate of the element region via a gate oxide film. Forming a first diffusion layer on the semiconductor substrate by ion implantation using the gate electrode as a mask; forming sidewalls on sidewalls of the gate electrode and the gate oxide film; and using the sidewall as a mask Forming an insulating film on the semiconductor substrate by ion implantation after forming the second diffusion layer; forming a contact on the drain side by forming a hole in the insulating film, and overlapping the gate on the source side or at least a sidewall. Forming the contacts so as to overlap each other, and impurities of the same conductivity type as the second diffusion layer through the respective contacts, And a step of forming an oxide portion on the gate electrode exposed on the surface of the third diffusion layer and on the contact on the source side, Of manufacturing a semiconductor device having the same.