JP3117872B2 - Manufacturing method of thin film semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor integrated circuit having a thin film transistor formed on an insulating surface. In the present invention, the insulating surface refers to an insulating substrate, an insulating film formed thereon, or an insulating film formed on a semiconductor or a metal material. The present invention particularly relates to an active matrix circuit used for a liquid crystal display or the like in an integrated circuit using a metal material containing aluminum as a main component as a gate electrode / wiring material.

[0002]

2. Description of the Related Art Conventionally, thin film transistors (TFTs)
It has been manufactured using a self-alignment method (self-alignment method) with the aid of a single crystal semiconductor integrated circuit technology. In this method, a gate electrode is formed on a semiconductor film via a gate insulating film, and impurities are introduced into the semiconductor film using the gate electrode as a mask. As a means for introducing impurities, a thermal diffusion method, an ion implantation method, a plasma doping method, or a laser doping method is used.

Conventionally, a TFT uses silicon as a gate electrode material, the conductivity of which is increased by doping using a single crystal semiconductor integrated circuit technology. This material has high heat resistance and is an ideal material when performing high-temperature treatment. However, in recent years it has been found that it is not appropriate to use silicon gates. First
Means that the conductivity is low. Until now, this was not noticeable in devices with a relatively small area, but as the size of the liquid crystal display increased, the size of the active matrix circuit also increased, and the design rules (the width of the gate wiring) were deferred. Became noticeable.

The second problem is related to the substrate material. With the increase in the size of the device, the substrate material used is not an expensive material having high heat resistance such as quartz or a silicon wafer, but a Corning 7059 glass. It is necessary to use an inexpensive material that is inexpensive but inferior in heat resistance, such as borosilicate glass such as NA-35 and NA-45 of NH Techno Glass Co., Ltd. Since formation of silicon gate requires a heat treatment of at least 650 ° C. or more, it was not appropriate to use such a material as a substrate.

[0005] From such a problem, it has been necessary to use an aluminum gate instead of a silicon gate.
In this case, pure aluminum may be used, but since heat resistance is extremely poor, a small amount of a material such as silicon, copper, and scandium (Sc) is usually added. Nevertheless, since aluminum has a problem in terms of heat resistance, thermal annealing cannot be used to activate impurities after a doping step using accelerated ions such as ion implantation, for example. Light annealing was used.
At that time, the intensity of the light to be irradiated so as not to be damaged by the light irradiation of the aluminum gate was greatly restricted.

Aluminum itself having a mirror surface reflects light over a wide wavelength range from ultraviolet to infrared. For example, in flash lamp annealing,
Since the duration of light irradiation is long, the temperature of the silicon film rises due to the light absorbed by the silicon film or the like, which is transmitted to the aluminum by heat conduction, and the aluminum is melted and deformed. The same problem occurs in both the laser annealing and the method of irradiating continuous oscillation laser light. In the case of irradiating a laser with an extremely short pulse oscillation, the light absorbed by the silicon film was used only for annealing the silicon film, and aluminum could be used without raising the temperature.

FIG. 4 shows a process for manufacturing a thin film transistor based on the above concept. First, a base insulating film 402 is deposited over a substrate 401, and island-shaped crystalline semiconductor regions 403 and 404 are formed. Then, an insulating film 405 functioning as a gate insulating film is formed to cover this. (FIG. 4 (A))

Then, gate electrodes / wirings 406 and 407 are formed using a material containing aluminum as a main component.
(FIG. 4B) Next, using the gate electrodes / wirings 406 and 407 as masks, impurities (for example, phosphorus (P) or boron (B)) are self-aligned by means of ion implantation, ion doping, or the like. ) Is implanted to form impurity regions 408 and 409. Here, since phosphorus is implanted into the impurity region 408 and boron is implanted into the impurity region 408, it is assumed that the former becomes N-type and the latter becomes P-type. (FIG. 4 (C))

Thereafter, the region into which the impurities are introduced is activated by irradiating a pulsed laser beam from the upper surface. (FIG. 4D) Finally, an interlayer insulator 411 is deposited, a contact hole is formed in each impurity region, and electrodes / wirings 412 to 416 connected thereto are formed, whereby a thin film transistor is completed. (FIG. 4E)

[0010]

However, in the method described above, the boundary between the impurity region and the channel formation region (the portion sandwiched between the impurity regions in the semiconductor region immediately below the gate electrode) (see FIG. 4D, for example). In), 410) has not been subjected to a sufficient treatment in the process, so it is electrically unstable, and if used for a long time, a problem such as an increase in leak current occurs, and the reliability is reduced. Was revealed. That is, as is apparent from the process, after the gate electrode is formed, no impurity is introduced and no laser is irradiated, so that the crystallinity of the channel formation region does not substantially change.

On the other hand, the impurity region adjacent to the channel forming region initially has the same crystallinity as the channel forming region, but the crystallinity is destroyed in the process of introducing the impurity. The impurity region is recovered by a subsequent laser irradiation step,
It is difficult to reproduce the same state as the initial crystallinity. Particularly, a portion of the impurity region which is in contact with the active region is likely to be shadowed by laser irradiation, and sufficient activation cannot be performed. That is, the crystallinity of the impurity region and the active region is discontinuous, and thus a trap level or the like is likely to occur. In particular, when a method of irradiating high-speed ions is employed as a method of introducing impurities, the impurity ions are scattered below the gate electrode portion by scattering to destroy the crystallinity of the portion. The region under such a gate electrode portion cannot be activated by a laser or the like due to the shadow of the gate electrode portion.

The same applies to the gate insulating film. That is, while the gate insulating film on the channel formation region keeps the initial state, the gate insulating film on the impurity region is greatly changed by the process of impurity introduction, laser irradiation, and the like. A trap level has occurred.

One method of solving this problem is to perform irradiation by irradiating light such as a laser from the back surface to activate. In this method, since the gate wiring does not become a shadow, the boundary between the active region and the impurity region is sufficiently activated. However, in this case, it is necessary for the substrate material to transmit light, and it is difficult for many glass substrates to transmit ultraviolet light of 300 nm or less. For example, a KrF excimer laser (wavelength: 248 nm) excellent in mass productivity is used. ) Is not available.

The present invention has been made in view of such a problem, and proposes a method for manufacturing a highly reliable thin film transistor by achieving continuity of crystallinity between an active region and an impurity region. It is another object of the present invention to obtain a high performance thin film semiconductor integrated circuit in which such thin film transistors are integrated.

[0015]

SUMMARY OF THE INVENTION The present invention is directed to a method of annealing a semiconductor device in addition to an impurity region and a gate insulating film by a thermal annealing process or an optical annealing process of irradiating light energy emitted from a strong light source such as a laser or a flash lamp. The above problem is solved by activating even the channel formation region.

The basic configuration of the present invention is as follows. First, a material that functions as a mask for forming an impurity region over a crystalline island-like semiconductor region is formed, and then a doping impurity is introduced into the semiconductor film by ion doping or the like using the material as a mask. . As a material to be used as the mask, an insulating material containing an organic material such as polyimide or a silicon oxide or silicon nitride such as silicon nitride, and a conductive material such as a metal such as aluminum, tantalum, titanium, or nitride may be used. Conductive metal nitrides such as tantalum and titanium nitride are preferred. In order to avoid direct contact between the semiconductor region and the mask, a film of silicon oxide or silicon nitride may be formed therebetween.

Next, the mask is removed to form an insulating film functioning as a gate insulating film. After that, by thermal annealing or optical annealing, not only the activation of the doped impurity is activated, but also the interface characteristics between the gate insulating film and the channel formation region and the characteristics of the boundary between the channel formation region and the impurity region are improved. Thereafter, a gate electrode and wiring mainly composed of aluminum are formed. In the thermal annealing process, the annealing temperature is set to 650 ° C. or lower. When a laser is used in the optical annealing process, a KrF laser (wavelength: 248 nm), XeC
1 laser (308 nm), ArF laser (193n)
m), various excimer lasers such as XeF laser (353 nm), and Nd: YAG laser (1064 nm)
And its second, third, and fourth harmonics, a carbon dioxide gas laser, an argon ion laser, a copper vapor laser, or the like.

Further, non-coherent light sources are inexpensive and easy to use. For example, a xenon lamp, a krypton arc lamp, a halogen lamp, or the like is used. In these light treatments, not only irradiation from above the semiconductor region,
Irradiation from the back side can be performed from both the upper side and the back side. In the thermal annealing or the light annealing, an atmosphere containing a halogen element (an atmosphere containing hydrogen chloride, chlorine, ethylene trichloride, hydrogen fluoride, fluorine, nitrogen trifluoride, etc.) or an oxidizing atmosphere (Atmosphere containing oxygen, various nitrogen oxides, ozone, etc.)
It is effective to do it in

When a gate electrode is formed, the relationship between the gate electrode and the impurity region may be an offset gate or an overlap gate. If an offset gate is used, the leakage current of the TFT can be reduced. However, in the case of the offset gate, since the current when the TFT is turned on is small, it is disadvantageous in terms of the operation speed. Therefore, the offset gate is usually used for switching the pixel of the active matrix circuit.
It may be used only for the FT or the sampling TFT, and the other logic circuits may be slightly overlapped. The overlap gate is disadvantageous in high-speed operation because of the presence of parasitic capacitance, but has no problem in driving an active matrix circuit.

The upper and side surfaces of all or a part of the gate electrode / wiring thus formed are anodized to form an aluminum oxide film having a high withstand voltage. Can be.
Especially in an active matrix circuit where there are many intersections of wiring, if an anodic oxide film is formed on the upper surface in this way,
An interlayer short circuit can be prevented. Since aluminum oxide has a high dielectric constant, a capacitance (capacitor) can be formed between the aluminum oxide and the upper wiring. The anodization is usually performed electrochemically in an electrolytic solution, but it goes without saying that the anodization may be performed in a reduced-pressure plasma atmosphere as in a known plasma anodization method.

[0021]

According to the present invention, when thermal annealing or optical annealing for activating doped impurities is performed, no gate electrode or wiring is formed, so that a conventional self-aligned structure as shown in FIG. The allowable range of the thermal annealing and the optical annealing is wider than that of the simple doping. For example, thermal annealing or flash lamp annealing, which cannot be used in the conventional technology, can be used. In the thermal annealing process, the impurity region, the channel formation region, and the gate insulating film are uniformly heated, so that no discontinuity occurs at the boundary between them. Similarly, even in the case of the optical annealing process, since there is no gate electrode, discontinuity does not occur due to shadow.

When the light annealing or the thermal annealing is performed in an atmosphere containing halogen or an oxidizing atmosphere, an effect of replacing hydrogen atoms remaining in the gate insulating film and the semiconductor region is recognized. A high electric field is generated in the gate insulating film or the channel formation region, and when hydrogen atoms are present in the form of silicon-hydrogen or oxygen-hydrogen, hydrogen is released by the electric field, resulting in a temporal change in characteristics. . If halogen, especially fluorine or chlorine, is present instead of hydrogen, the bond between silicon-halogen and oxygen-halogen is very strong, so that the bond is not easily separated and the characteristics are stable.

[0023]

【Example】

Embodiment 1 FIG. 1 shows this embodiment. This embodiment shows a process of forming an active matrix circuit and a driver circuit for driving the active matrix circuit on an insulating substrate.
The substrate 101 is a glass substrate, for example, Corning 70
A non-alkali borosilicate glass substrate such as 59. A silicon oxide film 102 was deposited thereon as an underlying oxide film. As a method for depositing the silicon oxide film, for example, a sputtering method or a chemical vapor deposition method (CVD method) can be used. Here, TEOS
A film was formed by a plasma CVD method using (tetraethoxysilane) and oxygen as material gases.
The substrate temperature was 200 to 400 ° C. The thickness of the base silicon oxide film was 500 to 2000 °.

Next, an amorphous silicon film was deposited. As a method of depositing the amorphous silicon film, a plasma CVD method or a low pressure CVD method is used. Here, monosilane (SiH ₄ ) is used as a material gas and plasma CV is used.
An amorphous silicon film was deposited by the D method. The thickness of the amorphous silicon film was 1000-15000 °. Then, the film was crystallized by annealing at 600 ° C. for 72 hours. The crystalline silicon film thus obtained was etched to form the island-shaped silicon regions 103 and others.

Thereafter, a silicon nitride film is formed on the entire surface by a plasma CVD method so as to have a thickness of 1000 to 6000.degree.
000 mm formed. The thickness is selected to be sufficient to function as a mask during doping. Then, the silicon nitride film is etched to form a doping mask 1.
04, 105 and 106 were formed. Then, the region 103 where the N-channel TFT was to be formed was covered with a photoresist mask 107.

In this state, boron ion doping was performed by an ion doping method. In this method, ions obtained by discharging a gas obtained by diluting diborane (B ₂ H ₆ ) with hydrogen are extracted at a high voltage, and the substrate is irradiated with the ions. The ion accelerating voltage is changed depending on the thickness of the silicon region. Typically, when the silicon region is 1000 °, 10 to 30 kV is appropriate. In this embodiment, 2
0 kV. The dose is 1 × 10 ^{14 to} 6 × 10
¹⁵ atoms / cm ² , for example, 5 × 10 ¹⁴ atoms / cm ² . Thus, P-type impurity regions 108 and 109 were formed. It should be noted that the range of the impurity region shown in the drawing is a nominal one, and it goes without saying that there is actually a wraparound due to ion scattering or the like. (Fig. 1 (A))

Similarly, after removing the photoresist mask 107, the region for forming the P-channel TFT was covered with a photoresist mask 110, and phosphorus ions were doped by an ion doping method. As the ion source, a gas obtained by diluting phosphine (PH ₃ ) with hydrogen was used. The acceleration voltage of the ion is 10 to 30 kV, for example, 2
0 kV. The dose is 1 × 10 ^{14 to} 6 × 10
¹⁵ atoms / cm ² , for example, 5 × 10 ¹⁴ atoms / cm ² . Thus, the N-type impurity region 111 was formed. (FIG. 1 (B))

Next, the photoresist mask 110 and the masks 104 to 106 were removed, and a silicon oxide film 112 functioning as a gate insulating film was formed to a thickness of 800 to 1500 Å, for example, 1200 Å. Here, the same manufacturing method as that of the base silicon oxide film 102 was employed. And 6
Annealing at 00 ° C. for 12 to 48 hours, for example, 24 hours, activated the doped impurities and improved the interface characteristics between the gate insulating film and the silicon region. (Fig. 1 (C))

Thereafter, the thickness of 3000 was obtained by sputtering.
An aluminum film (containing 1 to 5% by weight of silicon) of, for example, 5000 to 8000.degree.
3, 114, 115 and 116 were formed. At this time, the gate electrodes / wirings 113 and 114 are
8 so as to overlap. On the other hand, the gate electrode / wiring 115 is offset.
Further, since the gate wiring 116 was formed on the impurity region, it did not function as the gate electrode of the TFT, but functioned as one electrode of the capacitor. (Fig. 1 (D))

Further, a silicon oxide film 117 having a thickness of 2000 to 1000 Å, for example, 5000 と し て was formed as an interlayer insulator by a plasma CVD method using TEOS as a material gas, and a contact hole was formed therein. Then, a material such as a metal, for example, titanium nitride having a thickness of 1000
A multilayer film of aluminum having a thickness of 000 ° was formed, and this was etched to form electrodes / wirings 118 to 123 in impurity regions and gate wirings. Although the figure shows a state in which a contact is formed on a gate electrode on a silicon region, the contact is actually formed on a gate wiring other than the silicon region. (FIG. 1 (E))

Finally, a passivation film having a thickness of 2
A silicon nitride film 124 of 000 to 6000〜, for example, 3000Å was formed by a plasma CVD method, and the silicon oxide film 117 was etched to form a contact hole for the impurity region 109. Then, a transparent conductive film (for example, an indium tin oxide film) was formed, and this was etched to form a pixel electrode 125. (Figure 1
(F))

Through the above steps, an N-channel TFT
126, and P-channel TFTs 127 and 128 could be formed. Further, the capacitor 12 is located adjacent to the TFT 127.
9 (which uses the gate insulating film 112 as a dielectric) was also formed. In the present embodiment, the TFT 128 represents a TFT used as a switching element or a sampling TFT of a pixel of the active matrix circuit.
Reference numerals 26 and 127 represent TFTs used in other logic circuits.

FIG. 5 is a block diagram showing a case where an active matrix circuit using the TFT shown in this embodiment, its driver circuit, and other circuits are formed on a substrate 504. TFTs 126 and 127 shown in this embodiment
Is the original X / Y decoder driver and CPU,
Used for various memory logic circuits. On the other hand, TFT1
28 is a switching TFT 501 of a pixel of an active matrix circuit, a sampling TFT of a driver circuit,
Used as a matrix element for various memories. The capacitor 129 is used as an auxiliary capacitor 503 of the pixel cell 502 of the active matrix circuit and a storage element of various memory circuits.

Embodiment 2 FIG. 2 shows this embodiment. This example is the same as Example 1 up to the doping step except that a catalyst element for accelerating crystallization is added at the time of crystallization of amorphous silicon. Therefore, FIGS. 1A and 1B are referred to. First, an amorphous silicon film having a thickness of 300 to 1000 Å, for example, 500 Å was formed on a substrate on which a base oxide film was formed in the same manner as in Example 1. Then, after forming a thin nickel acetate film or nickel film on the surface, in a nitrogen or argon atmosphere,
By annealing at 00 to 580 ° C. for 2 to 8 hours,
Amorphous silicon was crystallized. At this time, nickel functions as a catalyst for promoting crystallization. The crystalline silicon film thus obtained was etched to form an island-shaped silicon region.

Thereafter, a silicon oxide film having a thickness of 1000 to 6000 °, for example, 3
000 mm formed. Then, the silicon oxide film was etched to form a doping mask. Then, the region for forming the N-channel TFT was covered with a photoresist mask. In this state, boron ion doping was performed by an ion doping method. Diborane diluted with hydrogen (B ₂ H ₆ ) was used as a doping gas. The ion acceleration voltage was 5 to 30 kV, for example, 10 kV. The dose is 1 × 10 ^{14 to} 6 × 10 ¹⁵ atoms / c.
m ² , for example, 2 × 10 ¹⁴ atoms / cm ² . Thus, P-type impurity regions 202 and 203 were formed.

Similarly, doping of phosphorus ions was performed by an ion doping method. Phosphine (PH ₃ ) diluted with hydrogen was used as a doping gas. The ion acceleration voltage was 5 to 30 kV, for example, 10 kV. The dose is 1 × 10 ^{14 to} 6 × 10 ¹⁵ atoms / cm ² ,
For example, it was set to 5 × 10 ¹⁴ atoms / cm ² . Thus, N
A mold impurity region 201 was formed.

Next, the masks 201 to 203 are removed, and the silicon oxide film 204 functioning as a gate insulating film is
0 to 1500 °, for example, 1200 °. By irradiating a KrF excimer laser (wavelength: 248 nm), the doped impurity was activated and the interface characteristics between the gate insulating film and the silicon region were improved. The energy of the laser is 250-45
0 mJ / cm ² , and the number of shots was suitably 2 to 50 shots. During laser irradiation, the substrate is
Heating to 550 ° C. activated more effectively.

Since the energy density and the number of shots depend on the silicon film, the optimum one may be selected according to the density, crystallinity, doping amount and other characteristics of the silicon film to be used. Typically, it is doped with phosphorus and has a dose of 2 × 10 ¹⁴ atoms / cm ² , a substrate temperature of 250 ° C.,
500 to ¹⁰ at a laser energy of 300 mJ / cm ²
A sheet resistance of 00Ω / □ was obtained. As is apparent from the figure, in this embodiment, the boundary between the impurity region and the active region is also irradiated by the laser, so that the reliability due to the deterioration of the boundary, which has been a problem in the conventional manufacturing process (see FIG. 4), is reduced. The decline was significantly reduced.

When crystallization is performed using a catalyst element such as nickel as in this embodiment, it is observed that a region which remains in an amorphous silicon state is left behind. The remaining amorphous silicon region could be completely crystallized. (Fig. 2 (A))

Thereafter, the thickness of 3000 was obtained by sputtering.
An aluminum film (containing 0.1 to 0.5% by weight of scandium) of 成膜 8000 °, for example, 5000 ° was formed. In a subsequent step (porous anodic oxide forming step), an anodic oxide film having a thickness of about 100 to 300 ° may be formed on the aluminum surface in order to enhance the adhesion between the aluminum film and the photoresist mask. In that case, the substrate may be immersed in a 1-5% citric acid ethylene glycol solution adjusted to about pH = 7 with ammonia, and a voltage of 5 to 20 V may be applied to the entire aluminum film.

Next, this was etched to form aluminum gate electrodes / wirings 205, 206, 207, and 208. At this time, the gate electrodes / wirings 205, 206,
Reference numeral 207 denotes impurity regions 201, 202, 203
In this case, the overlap was about 1 μm. Further, since the gate wiring 208 was formed on the impurity region, it did not function as the gate electrode of the TFT, but functioned as one electrode of the capacitor. In this state, the gate electrodes 205 and 206 are
And completely electrically insulated. The photoresist masks 209, 210, 211, and 212 used in the above-described patterning and etching steps were left as they were. (FIG. 2 (B))

Then, the gate electrodes / wirings 207 and 208
By applying a current in an electrolytic solution, porous anodic oxides 213 and 214 were formed on the side surfaces of the gate electrode. This anodic oxidation step was performed using a 3 to 20% aqueous solution of an acid such as citric acid, oxalic acid, phosphoric acid, chromic acid, sulfuric acid or the like. In this case, a thick anodic oxide of 0.5 μm or more, for example, 2 μm was formed at a low voltage of about 10 to 30 V. The width of the anodic oxide was dependent on the anodic oxidation time. At this time, since no current was applied to the gate electrodes / wirings 205 and 206, anodic oxidation did not occur.
(Fig. 2 (C))

As a result, initially, the gate electrodes 205 to 20
7 was in a state of being overlapped by about 1 μm with respect to the impurity region. However, since only the gate electrode 207 had its surface receded by 2 μm due to anodic oxidation, it turned around and was offset by 1 μm. It has become a state. Thus, the offset width can be stably controlled by using anodic oxidation.

Thereafter, the photoresist masks 209 to 209 are formed.
212 was peeled off, and the area other than the active matrix circuit was covered with the photoresist 215 again. Then, anodic oxidation is performed by passing a current through the gate electrodes / wirings 212 and 213, and a dense anodic oxide (aluminum oxide) film 216 is formed on the inside of the porous anodic oxides 213 and 214 and the upper surfaces of the gate electrodes / wirings 207 and 208. 217 to thickness 1
2,000 to 2500 °. Anodization is performed by immersing the substrate in an ethylene glycol solution of 1 to 5% citric acid adjusted to about pH = 7 with ammonia, setting all the gate wirings of the active matrix circuit as positive electrodes, and applying a voltage of 1 to 5 V /. This was done by boosting in minutes.

The anodic oxide film thus formed is recognized as a barrier type anodic oxide, and has excellent withstand voltage. Since the anodic oxide on the gate electrode is for preventing a short circuit with the upper wiring, an appropriate thickness may be selected for the purpose. Note that, except for the active matrix circuit region, the region was masked with the photoresist 215, and since it was electrically insulated from the active matrix circuit, anodic oxidation was not performed. (Figure 2
(D))

Thereafter, the photoresist 215 is removed,
A silicon oxide film 218 having a thickness of 2000 to 10 is formed as an interlayer insulator by a plasma CVD method using TEOS as a material gas.
A contact hole was formed in the contact hole, for example, at a thickness of 00 °, eg, 5000 °. Then, an aluminum film having a thickness of 5000 ° is formed and etched to form an electrode / wiring 21.
9 to 224 were formed in the impurity region and the gate wiring. (FIG. 2 (E))

Finally, a passivation film having a thickness of 2
A silicon nitride film 225 of 2,000 to 6000〜, for example, 3000Å was formed by a plasma CVD method, and the silicon oxide film 218 was etched to form a contact hole for the impurity region 203. Then, a transparent conductive film (for example, an indium tin oxide film) was formed, and this was etched to form a pixel electrode 226. (Figure 2
(F))

Through the above steps, an N-channel TFT
227 and P-channel TFTs 228 and 229 were formed. Further, the capacitor 23 is located adjacent to the TFT 229.
0 (which uses the gate insulating film 204 as a dielectric) was also formed. In this embodiment, the TFT 229 represents a TFT used as a switching element of a pixel of an active matrix circuit or a sampling TFT.
27 and 228 represent TFTs used in other logic circuits.

Embodiment 3 FIG. 3 shows this embodiment. First, a base silicon oxide film was formed on a substrate (Corning 7059), and an island-shaped amorphous silicon film was formed to a thickness of 300 to 1000 Å, for example, 500 Å. Then, the amorphous silicon film was crystallized by laser irradiation.

The laser used was a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec), and the energy density of the laser was 250 to 450 mJ / cm ² . During laser irradiation, the substrate was heated to 350-450 ° C. The number of laser shots was 2 to 10 shots. Since the energy density, the number of shots, and the temperature of the laser depend on the film quality of the amorphous silicon film, an optimum value may be selected according to the film quality. Although a pulse laser is used in this embodiment, a continuous wave laser such as an argon ion laser may be used. The crystalline silicon film thus obtained was etched to form an island-shaped silicon region.

Thereafter, a silicon nitride film 301 was deposited over the entire surface by plasma CVD to a thickness of 500.degree. continue,
Similarly, a silicon oxide film having a thickness of 3000 .ANG. Was formed on the entire surface by the plasma CVD method. Then, this silicon oxide film is etched, and doping masks 302, 303, and 3 are formed.
04 was formed. Further, a region for forming an N-channel TFT was covered with a photoresist mask 305.

In this state, boron ion doping was performed by an ion doping method. Diborane diluted with hydrogen (B ₂ H ₆ ) was used as a doping gas. The ion acceleration voltage was 10 to 50 kV, for example, 20 kV. The acceleration voltage needs to be increased by the amount of the silicon nitride film 301. The dose is 1 × 10 ^{14 to} 6
× 10 ¹⁵ atoms / cm ² , for example, 3 × 10 ¹⁵ atoms / cm
^{And 2} . Thus, P-type impurity regions 306 and 307 were formed. (FIG. 3 (A))

After removing the photoresist mask 305, phosphorus ions were again doped by the ion doping method. Phosphine (PH ₃ ) diluted with hydrogen was used as a doping gas. The ion acceleration voltage is
10 to 50 kV, for example, 20 kV. The dose is 1 × 10 ^{14 to} 6 × 10 ¹⁵ atoms / cm ² , for example,
1 × 10 ¹⁵ atoms / cm ² . At this time, phosphorus was implanted into the entire surface, but since the dose of phosphorus is smaller than the dose of boron in the previous doping, the conductivity type of the previously formed P-type impurity regions 306 and 307 is still P-type. It was a mold. Thus, an N-type impurity region 309 was formed. (FIG. 3 (B))

Next, the photoresist mask 308, the masks 302 to 304, and the silicon nitride film 301 are removed, and a silicon oxide film 310 functioning as a gate insulating film is formed to a thickness of 80.
0 to 1500 °, for example, 1200 °. By irradiating a halogen lamp light instantaneously, the doped impurity was activated and the interface characteristics between the gate insulating film and the silicon region were improved.

The intensity of the light radiated from the lamp depends on the temperature on the single crystal silicon wafer of the monitor being 800 to 130.
The temperature was adjusted to be 0 ° C., typically between 900 and 1200 ° C. Specifically, the temperature of the thermocouple embedded in the silicon wafer was monitored and fed back to the infrared light source. The temperature rise is constant and the speed is 50-20
0 ° C./sec, the temperature was lowered to 20 to 100 ° C. by natural cooling.

In particular, intrinsic or substantially intrinsic amorphous silicon is well absorbed by visible light, especially light having a wavelength of less than 0.5 μm, and can convert light to heat. 4
Irradiate light with a wavelength of μm. This wavelength is the crystallized intrinsic or substantially intrinsic (10 ¹⁷ cm ^{-3 of} phosphorus or boron).
Light can be effectively absorbed by the silicon film of the following) and converted into heat. Further, far-infrared light having a wavelength of 10 μm or more is absorbed by the glass substrate and heated, but when the wavelength of 4 μm or less is the majority, the glass is heated very little. That is, to further crystallize the crystallized silicon film, 0.5 to 4
A wavelength of μm is effective.

As is apparent from the figure, in this embodiment, since the light was irradiated from above and below the substrate, the reliability attributable to the deterioration of the boundary portion which was a problem in the conventional manufacturing process (see FIG. 4) was reduced. Decreased significantly. (FIG. 3 (C)) Thereafter, the thickness is 3000 to 8000 by a sputtering method.
Å, for example, a 5000Å aluminum film (containing scandium of 1 to 5% by weight) is formed and etched to form aluminum gate electrodes / wirings 311 and 31
2, 313 and 314 were formed.

At this time, as in the second embodiment, an area other than the active matrix circuit is covered with a photoresist 315, anodization is performed by passing current through the gate electrodes / wirings 313 and 314, and an aluminum oxide film having a thickness of 10 mm is formed.
A barrier-type anodic oxide film was formed on the upper and side surfaces of the gate electrodes / wirings 313, 314 at a temperature of 00 to 2500 °.

At this time, the gate electrode / wiring 311,
312 overlaps with the impurity regions 309 and 306. On the other hand, the gate electrode / wiring 303
Is offset, but unlike the second embodiment, one of the impurity regions 307 (the one forming the pixel electrode)
Is an offset, and the other is an overlap. Further, since the gate wiring 314 was formed on the impurity region, it did not function as the gate electrode of the TFT, but functioned as one electrode of the capacitor. (FIG. 3 (D))

After that, the photoresist 315 is removed,
A silicon oxide film 316 was formed to a thickness of 5000 .ANG. As an interlayer insulator by a plasma CVD method using TEOS as a material gas, and a contact hole was formed therein. Then, an aluminum film having a thickness of 5000 ° was formed, and this was etched to form electrodes and wirings 317 to 322 in impurity regions and gate wirings. (FIG. 3 (E))

Finally, a passivation film having a thickness of 3
A silicon nitride film 323 of 2,000 ° is formed by a plasma CVD method, and the silicon oxide film 316 is etched by
A contact hole was formed for impurity region 307. Then, a transparent conductive film (for example, an indium tin oxide film) is formed, and this is etched to form a pixel electrode 32.
4 was formed. (FIG. 3 (F))

Through the above steps, an N-channel TFT
325 and P-channel TFTs 326 and 327 could be formed. Further, the capacitor 32 is adjacent to the TFT 327.
8 (which uses the gate insulating film 310 as a dielectric) was also formed. In this embodiment, the TFT 327 represents a TFT used as a switching element or a sampling TFT of a pixel of the active matrix circuit.
Reference numerals 25 and 326 denote TFTs used in other logic circuits.

[0063]

According to the present invention, a thin film semiconductor integrated circuit constituting a gate electrode and a wiring can be formed by using a material containing aluminum as a main component. Although the TFT according to the present example was formed by a low-temperature process of 650 ° C. or lower, it had excellent reliability and was less likely to deteriorate. Specifically, the source is grounded, and +20 V or more or -2 is applied to one or both of the drain and the gate.
Even when left for 10 hours or more in a state where a potential of 0 V or less was applied, the characteristics of the transistor were not significantly affected.
As described above, the present invention is an industrially useful invention.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention. (See Example 1)

FIG. 2 shows an embodiment of the present invention. (See Example 2)

FIG. 3 shows an embodiment of the present invention. (See Example 3)

FIG. 4 shows an example of a conventional technique.

FIG. 5 shows a block diagram of an integrated circuit using the present invention.

[Explanation of symbols]

101: Substrate 102: Base oxide film 103: Island-shaped semiconductor region 104, 105, 106 .. Doping mask 107 ... Photoresist mask 108, 108 ... P-type impurity region 110 ... Photoresist mask 111 N-type impurity region 112 Gate insulating film 113, 114, 115 Gate electrode 116 ··· Gate wiring 117 ··· Interlayer insulator 118 to 123 ····· Upper wiring and electrode 124 ··· Passivation film 125 ·・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Pixel electrode 126 ・ ・ ・N-channel TFTs 127 and 128 P-channel TFT 129 Capacitance

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yasuhiko Takemura 398 Hase, Atsugi-shi, Kanagawa Examiner, Kazuya Tanada, Semiconductor Energy Laboratory Co., Ltd. (56) References JP-A-3-201538 (JP, A) Hei 6-77252 (JP, A) JP-A Hei 5-21463 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 G02F 1/1368 H01L 21/205 H01L 21 / 336 H01L 29/40

Claims (9)

(57) [Claims] A first step of forming an island-shaped semiconductor region on an insulating surface; a second step of selectively introducing an impurity into the semiconductor region to form an impurity region; A third step of forming an insulating film covering the semiconductor film, a fourth step of annealing the semiconductor region and the insulating film, and a fifth step of forming a gate electrode and a wiring on the insulating film. A method for manufacturing a thin film semiconductor integrated circuit, comprising: 2. A first step of forming first and second island-shaped semiconductor regions on an insulating surface, and selectively introducing impurities into the first and second semiconductor regions. A second step of forming an insulating film covering the first and second semiconductor regions; and a third step of annealing the first and second semiconductor regions and the insulating film. 4) and a fifth step of forming a gate electrode / wiring on the insulating film, wherein the gate electrode formed in the first semiconductor region substantially overlaps the impurity region, and Wherein the gate electrode formed in the semiconductor region has a portion which does not overlap with the impurity region. 3. A first step of forming first and second island-shaped semiconductor regions on an insulating surface, and an N-type or P-type conductive impurity region in the first semiconductor region. A third step of forming an impurity region of a conductivity type opposite to the conductivity type of the impurity region formed in the first step in the second semiconductor region; Fourth annealing of the second semiconductor region
And a fifth step of forming a gate electrode and a wiring on the insulating film, wherein the gate electrodes formed in the first and second semiconductor regions substantially overlap with the impurity regions. A method for manufacturing a thin film semiconductor integrated circuit, comprising: 4. The method for manufacturing a thin film semiconductor integrated circuit according to claim 1, wherein the annealing in the fourth step is a thermal annealing at 650 ° C. or lower. 5. The method for manufacturing a thin film semiconductor integrated circuit according to claim 1, wherein the annealing treatment in the fourth step is a light annealing treatment for irradiating laser light or strong light equivalent thereto. 6. The method for manufacturing a thin film semiconductor integrated circuit according to claim 1, wherein the annealing in the fourth step is performed in an atmosphere containing halogen. 7. The method according to claim 1, further comprising, between the first step and the second step, a step of forming a film containing silicon nitride as a main component so as to cover the semiconductor region. A method for manufacturing a thin film semiconductor integrated circuit. 8. The method for manufacturing a thin film semiconductor integrated circuit according to claim 1, wherein the semiconductor region is formed on a film containing silicon nitride as a main component. 9. The method according to claim 2, wherein after the fifth step, an oxide film is formed on the surface by anodizing the side and top surfaces of the gate electrode / wiring formed in the second semiconductor region. A method for manufacturing a thin film semiconductor integrated circuit, comprising the steps of: