JPH0290683A - Thin film transistor and its manufacturing method - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-voltage gIB transistor (hereinafter referred to as TPT) and a method for manufacturing the same.

[Conventional technology] High voltage TFTs are S, 5EKI etc.

IEEE ELECTRON DEVICELET
TERS, VOL, EDL-8, NO19゜pp, 42
5-427. 1987. As shown in et al., unlike normal TPT, it has an offset area.

In the conventional high voltage TPT, as shown in the above-mentioned literature, the impurity concentrations of the offset region and the channel region are different.

[Problems to be Solved by the Invention] However, the conventional high voltage TPT requires at least two impurity mixing steps in its manufacturing process.

These are a step of forming an offset region and a step of forming a source and drain region. Complementary type (
When forming a semiconductor device with a 0MO3 type circuit (hereinafter referred to as 0MO3 type), the impurity mixing step is performed at least four times, which poses the problem that the semiconductor device using high voltage TPT becomes expensive. Ta. In addition, in conventional high-voltage TPTs in which the impurity concentration is different from that of the offset region and the channel region, it is necessary to make the offset region large, which increases the area occupied by one high-voltage TPT, which increases the cost of semiconductor devices using this. It was spurring high.

Therefore, an object of the present invention is to reduce the cost of a semiconductor device using a high-voltage TPT by reducing the number of steps for adding impurities to the high-voltage TPT and reducing the offset region of the high-voltage TPT. It is.

[Means for Solving the Problems] In order to solve the above problems, the thin film transistor of the present invention is characterized in that the channel region and the offset region are formed with the same impurity having the same conductivity type and at the same impurity concentration. . Further, the method of manufacturing a thin film transistor of the present invention is characterized in that the concentration of impurities having p-type or n-type conductivity in the channel region and the offset region is set to 1015 cm" or less. It is characterized in that it includes a step of occasionally mixing an impurity having p-type or n-type conductivity into the semiconductor thin film.

[Example] FIG. 1 shows a cross-sectional view of the manufacturing process order of a high voltage TFT in an example of the present invention. FIG. 5A is a cross-sectional view at the end of the gate electrode forming process. 101 is a substrate whose surface is insulated at least, 102 is a semiconductor FNM, 103 is a gate insulating film, and 104 is a gate electrode. A semiconductor fiJg[102 is formed on the substrate 101, and a gate insulator H103 is formed.
, forming the gate electrode 104. FIG. 5B is a cross-sectional view during the step of forming the source and drain regions, and 105 is a mask material for preventing the incorporation of impurities. A p region (a region with a p-type conductivity type and a high impurity concentration) or an n9 region (a region with an n-type conductivity type and a high impurity concentration) is formed by an ion implantation method (I/I method), etc., and a source, Use as drain region. When using the I/I method, mask material 10
5, a photoresist or the like is used. The offset region is between the end of the gate electrode and the end of the source and drain regions.

When the semiconductor thin film 102 is made of Si, the impurity mixed in is B(
p type), P (n type), etc., and the impurity concentration is 1029c.
It is about m-3. Figure (c) is a cross-sectional view at the end of the source and drain region forming process, 106 and 107 are the source and drain regions formed by the process shown in Figure (b), and 108 is the channel region and offset region. . Impurities having p-type or n-type conductivity are not mixed into the channel region and offset region 108 after the step of forming the gate electrode 104. Therefore, the impurity mixing step in this example only needs to be carried out at least once, and
A high breakdown voltage TPT can be formed in a process similar to that for forming a T. After FIG. 2C, an insulating film is formed, wiring, etc. are performed, and the semiconductor device is completed.

In the same embodiment, the channel region and offset region 1
If the impurity concentration having p-type or n-type conductivity in 08 is 1015 crrr3 or less, the semiconductor thin film 1
When polycrystalline Si is used for 02, the drain breakdown voltage is significantly improved and the offset region is greatly reduced. When a pn junction is formed in polycrystalline Si, there is a large amount of leakage current due to defects in grain boundaries, and the reverse resistance and pressure are also small.

The same is true when forming a high breakdown voltage TPT; to improve this, either grow the crystals to make them larger, or
It was necessary to add atoms such as hydrogen to the defects by H2 plasma treatment or the like. However, if the impurity concentration in the offset region is set to 1015 cm-" or less as described above,
In particular, the drain breakdown voltage can be improved and the offset region can be reduced without requiring processes such as crystal growth or H2 plasma. For example, conventionally, to obtain a drain breakdown voltage of 100V, an offset length (distance Wl between the end of the gate electrode and the end of the source and drain regions in FIG. 1(C)) was required to be 20 μm, but this was reduced to half, 10 μm. We were able to.

Figure 2 shows a CMO8 type high voltage T in an embodiment of the present invention.
1A and 1B are cross-sectional views showing the order of manufacturing steps of a semiconductor device using PT.

FIG. 1(a) is a cross-sectional view during the process of selectively mixing impurities with p-type conductivity to form the source and drain regions of a Pch TFT, and the same symbols as in FIG. Represents the same thing as Figure 1. In the same figure (b), Nch
FIG. 3 is a cross-sectional view during a step of selectively incorporating impurities having an n-type conductivity type in order to form source and drain regions of a TFT. Reference numerals 201 and 202 are the source and drain regions of the Pch TFT formed in the process shown in FIG. 3A, and 203 is the channel region and offset region of the Pch TFT. FIG. 5(C) is a cross-sectional view at the end of the process of forming the source and drain regions of the CMO8 type high breakdown voltage TPT. 204 and 205 are the source and drain regions of the Nch TFT formed in the process shown in FIG.
6 is a channel region and an offset region of the Nch TFT. As can be seen from the above embodiments, when forming a CMO8 type high breakdown voltage TPT, the impurity mixing process may be performed at least twice, which significantly shortens the manufacturing process compared to the conventional process of at least four times.

Although the embodiments described above are examples in which a TPT having offset regions on both sides of the gate electrode is used, the present invention may also be applied to a case in which a TPT having an offset region on only one side of the gate electrode is used. Of course, the channel region and the offset region may be made of an intrinsic (i-type) semiconductor. When polycrystalline Si is used for the semiconductor N film, better results are currently obtained by making the channel region and offset region i-type. Furthermore, by using the method of manufacturing a semiconductor device of the present invention, at the same time, T
Since PT can also be formed, a CMO8 type semiconductor device in which normal TPT and high voltage TPT are mixed can be formed in a small number of steps. The high voltage TPT can be used to form driving circuits for electroluminescence and piezoelectric elements, and the present invention has a wide range of applications.

[Effects of the Invention] As described above, according to the present invention, in a high voltage TPT, the channel region and the offset region are formed with the same impurity having the same conductivity type and the same impurity concentration, and the manufacturing method thereof can be improved. In this method, the number of manufacturing steps can be reduced by mixing impurities having p-type or n-type conductivity into the semiconductor thin film only when forming the source and drain regions. In addition, by setting the impurity concentration of p-type or n-type conductivity in the channel region and offset region to 1 o"cm-' or less, the offset region can be reduced. Due to the above effects, manufacturing can be performed at low cost. A high-performance, high-voltage TPT can be realized, and a high-voltage semiconductor device using it can be realized at low cost.The present invention can also be applied to a semiconductor device including a general circuit using a high voltage.

[Brief explanation of drawings]

FIGS. 1(a) to 1(C) are cross-sectional views showing the steps of manufacturing a high voltage TPT according to an embodiment of the present invention. 5A is a cross-sectional view at the end of the gate electrode formation process, FIG. 2B is a cross-sectional view at the source and drain region formation step, and FIG. 2C is a cross-sectional view at the end of the source and drain region formation step. FIGS. 2(a) to (C) are CMs in the embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the order of manufacturing steps of a semiconductor device using an O8 type high breakdown voltage TPT. Figure (a) shows that during the step of selectively mixing impurities with p-type conductivity to form the source and drain regions of a Pch TFT, the
In order to form the source and drain regions of the TFT, during the process of selectively mixing an inert substance with n-type conductivity type, the same figure (C) shows the completion of the process of forming the source and drain regions of the CMO3 type high voltage TPT. A cross-sectional view of time. 101...Substrate 102 whose surface is insulated at least
...Semiconductor thin film 103...Gate insulating film 104...Gate electrode 105...Mask material 106, 107...Source, drain region 108...
...Applicant for channel area and offset area and above Seiko Epson Co., Ltd. agent Patent attorney Masayoshi Kamiyanagi (1 other person) ↓I/T

Claims (3)

[Claims] (1) A thin film transistor in which a semiconductor thin film, a gate insulating film, and a gate electrode are provided on a substrate whose surface is insulated at least, and a channel region, an offset region, a source region, and a drain region are provided in the semiconductor thin film. A thin film transistor characterized in that the offset region and the offset region are formed using the same impurity having the same conductivity type and the same impurity concentration. (2) p in the channel region and offset region
The concentration of impurities with conductivity type or n-type is 10^1
The thin film transistor according to claim 1, characterized in that the thickness is ^5 cm^-^3 or less. (3) A method for manufacturing a thin film transistor, comprising providing a semiconductor thin film, a gate insulating film, and a gate electrode on a substrate whose surface is insulated at least, and providing a channel region, an offset region, a source, and a drain region in the semiconductor thin film. A method for manufacturing a thin film transistor, comprising the step of mixing an impurity having p-type or n-type conductivity into the semiconductor thin film only when forming source and drain regions.