Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)
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Updated
Aug 23, 2024 - Python
Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)
VLSI Conference Dates
This repository contains fundamental digital logic gate designs coded in Verilog. These designs are intended to provide a clear and straightforward example of how to create and simulate various digital logic gates.
Path-Oriented Decision Making (PODEM) algorithm for Automatic Test Pattern Generation (ATPG).
Summer School on Full Stack Open-Source Ecosystem for Processor Based Chip Design
The repository contains an analysis and tapeout design process of a CMOS inverter under sky130 PDK. open source tools like Ngspice, Magic VLSI, Xschem has been used for design and simulations.
A collection of Schematics, PCBs and VLSI work on various platforms
Gatery, a library for circuit design.
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
This repository contains a collection of basic VHDL programs, including implementations of fundamental electronic components such as logic gates, flip-flops, adders, counters, subtractors, and more.
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
VLSI Project for CMPE 480______ Authors: John San Juan, Cody Hum, Vincent Verdan, Jose Zaragosa
This is the Repository which contains the detail of my work done at SCL Mohali (formerly Department of Space, ISRO). This was the internship basically focused on the "Experimental Analysis of MOS Capacitor for Oxide Furnaces" and further study of VLSI.
This repository contains code files for VLSI Laboratory - EC39004, conducted in Spring 2024 at IIT Kharagpur
This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
Small designs made using Catapult-based HLS (C++ / SystemC)
VLSI System with memory that displays arithmetic operations on a Video Graphics Array. (October 2023)
Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator
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