rtl-design

JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.

asic rtl verilog finite-state-machine uart alu hdl verilog-hdl open-source-hardware serial-communication rtl-design digital-designs 8bit-cpu chip-design tinytapeout control-logic prototype-core embedded-core minimal-cpu-core

Updated Oct 19, 2025
SystemVerilog

4xmen / rvnm

Star

Responsive vertical navigation menu

javascript wordpress navbar rtl menu right-to-left responsive-menu multi-theme wordpress-menu wordpress-navigation rtl-design responsive-navbar xstack 4xmen

Updated Dec 3, 2022
CSS

Akashtailor-exe / 30-days-of-verilog

Star

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

verilog vlsi 30daysofcode 30-days-of-code digital-logic-design verilog-programs digitalcircuit verilog-project rtl-design rtl-coding

Updated Sep 30, 2023

snbk001 / 100DaysofRTL

Star

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

makefile verilog synthesis systemverilog hdl testbench systemverilog-hdl systemverilog-simulation rtl-design systemverilog-test-bench edge-detector-with-mealy

Updated Nov 6, 2022
SystemVerilog

AUCOHL / RTL-Repo

Star

RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24

verilog rtl-design llm llm-benchmarking

Updated Jun 5, 2024
Python

synogate / gatery

Star

Gatery, a library for circuit design.

library asic fpga cpp rtl vlsi vlsi-design rtl-design gatery

Updated Dec 9, 2024
C++

dannydyl / SONY-Cell-SPU-Processor

Star

This repository contains the complete Verilog implementation and supporting tools for a cycle-accurate, dual-issue pipelined multimedia processor inspired by the Synergistic Processing Unit (SPU) of the Cell Broadband Engine architecture.

processor simd verilog computer-architecture vlsi cpu-architecture rtl-design dual-issue

Updated May 6, 2025
Verilog

MohamedHussein27 / AMPA_APB4_Protocol

Star

This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory, and comprehensive testbenches. Includes scripts for fast simulation and synthesis using QuestaSim, Vivado and Quartus Prime

communication-protocol digital-design verilog-project amba-apb rtl-design

Updated Sep 5, 2024
Verilog

maazm007 / 100Daysof_RTL

Star

The Repository contains the code of various Digital Circuits

verilog hdl verilog-hdl xilinx-ise vlsi-design rtl-design

Updated Aug 7, 2023
Verilog

esynr3z / pip-hdl

Star

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

python vhdl verification vip pip verilog systemverilog ip-core rtl-design

Updated Jan 26, 2024
Python

williaml33moore / bathtub

Star

BDD Gherkin implementation in native SystemVerilog, based on UVM.

asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification

Updated Nov 16, 2024
SystemVerilog

Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM

Star

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

rtl verilog finite-state-machine synthesis vivado systemverilog questasim testbench rtl-design

Updated Aug 4, 2024
Verilog

cp024s / 100-days-of-RTL

Star

probable journey of RTL coding ft. Chandra Prakash

fpga verilog systemverilog testbench fpga-programming rtl-design

Updated Mar 14, 2024
Verilog

Choaib-ELMADI / getting-started-with-systemverilog

Sponsor

Code

Issues

Pull requests

Getting started with SystemVerilog: Hardware Description Language for design and verification.

testing design asic fpga hardware verification rtl systemverilog hardware-designs hdl modelsim questasim uvm testbench systemverilog-hdl rtl-design uvm-verification

Updated Nov 5, 2025

SystemVerilog

alirezajaberirad / Object-Oriented-Modeling-of-Electronic-Circuits

Star 6

Code

Issues

Pull requests

This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022

image-processing object-oriented systemc object-oriented-programming gate-level system-modeling systemc-ams gate-level-simulation rtl-design

Updated Jul 29, 2022

C++

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rtl-design

Here are 99 public repositories matching this topic...

4xmen / Web-Package-RTL

pulp-platform / cheshire

4xmen / x-mega-menu

pulp-platform / croc

4xmen / x-tree-select

mirseo / JSilicon

4xmen / rvnm

Akashtailor-exe / 30-days-of-verilog

snbk001 / 100DaysofRTL

AUCOHL / RTL-Repo

synogate / gatery

dannydyl / SONY-Cell-SPU-Processor

MohamedHussein27 / AMPA_APB4_Protocol

maazm007 / 100Daysof_RTL

esynr3z / pip-hdl

williaml33moore / bathtub

Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM

cp024s / 100-days-of-RTL

Choaib-ELMADI / getting-started-with-systemverilog

alirezajaberirad / Object-Oriented-Modeling-of-Electronic-Circuits

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