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ORCIDA-SSCC 2019: Macau, SAR, China
- IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macau, SAR, China, November 4-6, 2019. IEEE 2019, ISBN 978-1-7281-5106-9
- Yiming Zhu:
What are the driving forces of DRAM? 1-4 - Kyo Won Jin:
Memory Centric Computing, The Foundation of the Next Smart Society. 5-8 - Debapriya Sahu, Rittu Sachdev-Singh, Harikrishna Parthasarathy, Rohit Chatterjee, Brian P. Ginsburg
, Daniel Breen, Karan Bhatia, Sudhir Polarouthu, Vimal Edayath, Bhupendra Sharma, Meghna Agarwal, Karthik Subburaj, Anjan Prasad, Shankar Ram, Cathy Chi, Ross Kulak, Vijay Rentala, Neeraj P. Nayak:
A 45nm 76-81GHz CMOS Radar Receiver for Automotive Applications. 9-12 - Y. Zha, Loïc Zahnd, Jiang Deng, David Ruffieux, Komail M. H. Badami, T. Mavrogordatos, Y. Matsuo, Stéphane Emery:
An Untrimmed PVT-Robust 12-bit 1-MS/s SAR ADC IP in 55nm Deeply Depleted Channel CMOS Process. 13-16 - Yoshisato Yokoyama, Kenji Goto, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Yoshiki Tsujihashi, Yuichiro Ishii:
A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU. 17-20 - Harry Muljono, Kathy Peng, Linda Sun, Isaac Abraham, Charlie Lin, Yanjie Zhu, Chunrong Song:
A 2.666GT/s 128GB/s 14nm Memory I/O with Jitter and Crosstalk Cancellation. 21-24 - Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. 25-28 - Xiaoyong Xue, Jianguo Yang, Yuejun Zhang, Mingyu Wang, Hangbing Lv, Xiaoyang Zeng, Ming Liu:
A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key. 29-32 - Tzu-Hsiang Hsu, Yen-Kai Chen, Tai-Hsing Wen, Wei-Chen Wei, Yi-Ren Chen, Fu-Chun Chang, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh:
A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction. 33-34 - Hyunjoon Kim, Qian Chen, Bongjin Kim:
A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC. 35-36 - Jonathan Fuh, Fu-Bin Yang, Po-Hung Chen:
A 69.3% Efficiency, 6.78-MHz Wireless Power Delivery System with 0X/1X Regulating Rectifier and Reconfigurable Power Amplifier. 37-38 - Bohui Xiao, Praveen Kumar Venkatachala, Yang Xu, Ahmed ElShater, Calvin Yoji Lee, Spencer Leuenberger, Qadeer Ahmad Khan, Un-Ku Moon:
An 80mA Capacitor-Less LDO with 6.5µA Quiescent Current and No Frequency Compensation Using Adaptive-Deadzone Ring Amplifier. 39-42 - Xinyuan Ge, Lin Cheng, Wing-Hung Ki:
A DCM ZVS Class-D Power Amplifier for Wireless Power Transfer Applications. 43-44 - Jin-Gyu Kang, Min-Gyu Jeong, Jeongpyo Park, Changsik Yoo:
Time-Based Digital LDO Regualtor with Fractionally Controlled Power Transistor Strength and Fast Transient Response. 45-48 - T. Nagateja, Shao-Qi Chen, Li-Cheng Chu, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
A Single-Inductor Triple-Output Converter with an Automatic Detection of DC or AC Energy Harvesting Source for Supplying 93% Efficiency and 0.05mV/mA Cross Regulation to Wearable Electronics. 49-52 - Tsu-Ming Liu, Chang-Hung Tsai, Shawn Shih, Chih-Kai Chang, Jia-Ying Lin, Wayne Hsieh, Yung-Chang Chang, Chi-Cheng Ju:
A 0.7mm2 8.54mW FocusNet Display LSI for Power Reduction on OLED Smart-phones. 53-56 - Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, Yeongjae Choi, Hyeonuk Kim, Lee-Sup Kim:
A 47.4µJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices. 57-60 - Zhe Yuan, Jingyu Wang, Yixiong Yang, Jinshan Yue, Zhibo Wang, Xiaoyu Feng, Yanzhi Wang, Xueqing Li, Huazhong Yang, Yongpan Liu:
A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler. 61-64 - Cheng-Hsun Lu, Yi-Chung Wu, Chia-Hsiang Yang:
A 2.25 TOPS/W Fully-Integrated Deep CNN Learning Processor with On-Chip Training. 65-68 - Chenyu Xu, Dixian Zhao:
A Ka-Band CMOS Phase-Inverting Amplifier with 0.6 dB Gain Error and 2.5° Phase Error. 69-72 - Nahla T. Abou-El-Kheir, Ralph D. Mason, Mingze Li, Mustapha C. E. Yagoub:
A High-Performance Low Complexity All-Digital Fractional Clock Multiplier. 73-76 - Peng Gu, Dixian Zhao:
A DC-43.5 GHz CMOS Switched-Type Attenuator with Capacitive Compensation Technique. 77-78 - Xiangyu Meng, Zhenpeng Zheng, Jiaqi Zhang, C. Patrick Yue:
A 28-GHz Compact SPDT Switch Using LC-Based Spiral Transmission Lines in 65-nm CMOS. 79-80 - Jiajun Zhang, Dixian Zhao:
A 20-GHz Ultra-Low-Power LNA Using gm-Boosted and Current-Reuse Techniques in 65-nm CMOS for Satellite Communication Terminals. 81-82 - Xuefan Jin, Dong-Seok Kang, Youngjun Ko, Kee-Won Kwon, Jung-Hoon Chun:
A 4-GHz Sub-harmonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injection Timing and Pulsewidth. 83-86 - Sangdon Jung, Jaehong Jung, Byungki Han, Seunghyun Oh, Jongwoo Lee:
A 9.4MHz-to-2.4GHz Jitter-Power Reconfigurable Fractional-N Ring PLL for Multi-Standard Applications in 7nm FinFET CMOS Technology. 87-90 - Chun-Yu Lin, Yu-Ting Hung, Tsung-Hsien Lin:
A 2.4-GHz 500-µW 370-fsrms Integrated Jitter Sub-Sampling Sub-Harmonically Injection-Locked PLL in 90-nm CMOS. 91-94 - Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu:
A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time. 95-98 - Yasunori Mochizuki:
AI and IoT for Social Value Creation. 99-102 - Mau-Chung Frank Chang:
Millimeter-Wave System-on-Chip Applications from Space Explorations to Contactless Connectivity. 103-106 - Rushil K. Kumar, Hui Jiang, Kofi A. A. Makinwa:
An Energy-Efficient BJT-Based Temperature-to-Digital Converter with ±0.13°C (3σ) Inaccuracy from -40 to 125°C. 107-108 - Elisa Sacco, Johan Vergauwen, Georges G. E. Gielen:
A 16.1-b ENOB 0.064mm2 Compact Highly-Digital Closed-Loop Single-VCO-based 1-1 SMASH Resistance-to-Digital Converter in 180nm CMOS. 109-112 - Matthias Eberlein, Harald Pretl:
A Low-Noise Sub-Bandgap Reference with a ±0.64% Untrimmed Precision in 16nm FinFET. 113-116 - Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS. 117-120 - Pengfei Zhai, Xiong Zhou, Yan Cai, Zheng Zhu, Fan Zhang, Zixiao Lin, Qiang Li:
A Multi-Slice VCO-based Quantizer for On-Chip Power Supply Noise Analysis Achieving 0.11 (mV)2/sqrt(MHz) Noise Floor. 121-122 - Sujith Billa, Suhas Dixit, Shanthi Pavan:
A 265μW Continuous-Time 1-2 MASH ADC Achieving 100.6 dB SNDR in a 24 kHz Bandwidth. 123-124 - Saurabh Jain, Longyang Lin, Massimo Alioto:
Drop-In Energy-Performance Range Extension in Microcontrollers Beyond VDD Scaling. 125-128 - Toshifumi Uemura, Yuko Kitaji, Kazuki Fukuoka:
A 28nm fully digital voltage monitor with 16.5uV/°C accuracy and 0.8mV quantized error from -40 to 160°C for ISO26262 ASIL-D capable MCU. 129-132 - Bo Wang, Manupa Karunarathne, Aditi Kulkarni Mohite, Tulika Mitra, Li-Shiuan Peh:
HyCUBE: A 0.9V 26.4 MOPS/mW, 290 pJ/op, Power Efficient Accelerator for IoT Applications. 133-136 - Amit Agarwal, Steven Hsu, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De:
A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS. 137-140 - Fei Li, Ming Ming Wong, Aarthy Mani, Vishnu Paramasivam, Anh-Tuan Do:
0.54 pJ/bit, 15Mb/s True Random Number Generator Using Probabilistic Delay Cell for Edge Computing Applications. 141-144 - Sai Kiran Cherupally, Shihui Yin, Deepak Kadetotad, Chisung Bae, Sang Joon Kim, Jae-Sun Seo:
A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV and SRAM PUF for Authentication and Secret Key Generation. 145-148 - Alexander Standaert, Patrick Reynaert:
A Packaged Fully Digital 390GHz Harmonic Outphasing Transmitter in 28nm CMOS. 149-152 - An'an Li, Yingtao Ding, Zipeng Chen, Wei Wang, Sijia Jiang, Shiyan Sun, Zhiming Chen, Baoyong Chi:
A Fully Integrated 27.5-30.5 GHz 8-Element Phased-Array Transmit Front-end Module in 65 nm CMOS. 153-156 - Heng Huang, Milin Zhang, Guolin Li, Zhihua Wang:
A 2Mbps sub-100µW Crystal-less RF Transmitter with Energy Harvesting for Multi-Channel Neural Signal Acquisition. 157-160 - Paul Stärke, Andres Seidel, Corrado Carta, Frank Ellinger:
Direct-Conversion Receiver Front-End for 180 GHz with 80 GHz Bandwidth in 130nm SiGe. 161-164 - Barosaim Sung, Chilun Lo, Jaehoon Lee, Sangdon Jung, Seungjin Kim, Jaehong Jung, Seungyong Bae, Youngsea Cho, Yong Lim, Dooseok Choi, Myeongcheol Shin, Soonwoo Choi, Byungki Han, Seunghyun Oh, Jongwoo Lee:
A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS. 165-168 - Ehsan Kargaran, Carl Bryant, Danilo Manstretta, Jon Strange, Rinaldo Castello:
A Sub-0.6V, 330 µW, 0.15 mm2 Receiver Front-End for Bluetooth Low Energy (BLE) in 22 nm FD-SOI with Zero External Components. 169-172 - Jian Zhao, Jingna Mao, Wenyu Sun, Yuxuan Huang, Yixiong Yang, Huazhong Yang, Yongpan Liu:
A 4-Mbps 41-pJ/bit On-off Keying Transceiver for Body-channel Communication with Enhanced Auto Loss Compensation Technique. 173-176 - Jihee Lee, Jaeeun Jang, Jaehyuk Lee, Hoi-Jun Yoo:
A battery-less 31 µW HBC receiver with RF energy harvester for implantable devices. 177-180 - Muhammad Bilawal Khan, Hassan Saif, Yoonmyung Lee:
A Piezoelectric Energy Harvesting Interface for Irregular High Voltage Input with Partial Electric Charge Extraction with 3.9× Extraction Improvement. 181-184 - Peng-Chang Huang, Tai-Haur Kuo:
A 100-pA Adaptive-FOCV MPPT Circuit with >99.6% Tracking Efficiency for Indoor Light Energy Harvesting. 185-188 - Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, Dong-Jin Chang, Won-Mook Lim, Jae-Hyun Chung, Chang-Un Park, Eun-Ji An, Seung-Tak Ryu:
A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. 189-192 - Harald Garvik, Carsten Wulff, Trond Ytterdal:
A 68 dB SNDR Compiled Noise-Shaping SAR ADC With On-Chip CDAC Calibration. 193-194 - Jae Sik Yoon, Jiyoon Hong, Jintae Kim:
A Digitally-Calibrated 70.98dB-SNDR 625kHz-Bandwidth Temperature-Tolerant 2nd-order Noise-Shaping SAR ADC in 65nm CMOS. 195-196 - Akshay Jayaraj, Abhijit Das, Srinivas Arcot, Arindam Sanyal:
8.6fJ/step VCO-Based CT 2nd-Order $\Delta\Sigma$ ADC. 197-200 - Wooseok Byun, Dokyun Kim, Sung Yeon Kim, Ji-Hoon Kim:
A 110.3-bits/min 8-Ch SSVEP-based Brain-Computer Interface SoC with 87.9% Accuracy. 201-204 - Seungsik Moon, Hyunhoon Lee, Younghoon Byun, Jongmin Park, Junseo Joe, Seokha Hwang, Sunggu Lee, Youngjoo Lee:
FPGA-Based Sparsity-Aware CNN Accelerator for Noise-Resilient Edge-Level Image Recognition. 205-208 - Miaorong Wang, Anantha P. Chandrakasan:
Flexible Low Power CNN Accelerator for Edge Computing with Weight Tuning. 209-212 - Jilin Zhang, Hui Wu, Jinsong Wei, Shaojun Wei, Hong Chen:
An Asynchronous Reconfigurable SNN Accelerator With Event-Driven Time Step Update. 213-216 - Zhixiao Zhang, Jia-Jing Chen, Xin Si, Yung-Ning Tu, Jian-Wei Su, Wei-Hsing Huang, Jing-Hong Wang, Wei-Chen Wei, Yen-Cheng Chiu, Je-Min Hong, Shyh-Shyuan Sheu, Sih-Han Li, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors. 217-218 - Jonathan Narinx, Robert Giterman, Andrea Bonetti, Nicolas Frigerio, Cosimo Aprile, Andreas Burg, Yusuf Leblebici:
A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications. 219-222 - Jongeun Koo, Eunhwan Kim, Seunghyun Yoo, Taesu Kim, Sungju Ryu, Jae-Joon Kim:
Configurable BCAM/TCAM Based on 6T SRAM Bit Cell and Enhanced Match Line Clamping. 223-226 - C. Y. He, K. H. Tang, T. S. Chen, K. Y. Chang, C. H. Lin, K. Sato, Shyh-Jye Jou, P. H. Chen, H. M. Chen, B. D. Rong, K. Itoh:
Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_ Line. 227-230 - Shun Suzuki, Kyoji Mizoguchi, Hikaru Watanabe, Toshiki Nakamura, Yoshiaki Deguchi, Keita Mizushina, Ken Takeuchi:
Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing. 231-234 - Yizhak Shifman, Yoel Krupnik, Udi Virobnik, Ahmad Khairi, Yosi Sanhedrai, Ariel Cohen:
A 1.64mW Differential Super Source-Follower Buffer with 9.7GHz BW and 43dB PSRR for Time-Interleaved ADC Applications in 10nm. 235-238 - Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Hyeon-Min Bae, Andreas Burg, Thomas Toifl, Yusuf Leblebici:
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. 239-240 - Zhao Zhang, Guang Zhu, Can Wang, Li Wang, C. Patrick Yue:
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator. 241-242 - Hye-Yoon Joo, Deog-Kyoon Jeong:
A Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Optimal Timing Adaptation. 243-244 - Xiaofei Li, Fangyu Mao, Pyungwoo Yeon, Yan Lu, Maysam Ghovanloo, Rui Paulo Martins:
A 200-MHz Wide Input Range CMOS Passive Rectifier with Active Bias Tunning. 245-246 - Elly De Pelecijn, Michiel Steyaert:
A 7.5 - 42V Input High-VCR Monolithic DC-DC Converter Using Stacked Isolated SC Cores. 247-250 - Chen-Yi Kuo, Chun-An Lu, Yu-Te Liao:
A 918MHz Wide-Range CMOS Rectifier with Diode-Feeding and Switch-Capacitor-Based Load Modulation Technique. 251-254 - Neha Kumari, Shang-Hsien Yang, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
A CMOS Switched-Capacitor Boost Mode Envelope Tracking Regulator with 4% Efficiency Improvement at 7.7dB PAPR for 20MHz LTE Envelope Tracking RF Power Amplifiers. 255-258 - Junyoung Park, Hyungmin Gi, Seungchul Jung, Sang Joon Kim, Yoonmyung Lee:
A Conversion-Ratio-Insensitive High Efficiency Soft-Charging-Based SC DC-DC Boost Converter for Energy Harvesting in Miniature Sensor Systems. 259-262 - Makoto Ikeda, Tadayuki Ichihashi, Hiromitsu Awano:
33us, 94uJ Optimal Ate Pairing Engine on BN Curve over 254b Prime Field in 65nm CMOS FDSOI. 263-266 - Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Tetsuya Hirose, Masaya Miyahara, Teruki Someya, Kenichi Okada, Ippei Akita, Yoshihiko Kurui, Hideyuki Tomizawa, Masahiko Yoshimoto:
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. 267-270 - Qichen Zhang, Yun Chen, Xiaoyang Zeng, Keshab K. Parhi, Borivoje Nikolic:
A 3.01 mm2 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm. 271-274 - Kang-Lun Chiu, Hsun-Wei Chan, Wei-Che Lee, Chang-Ting Wu, Henry Lopez Davila, Hung-Chih Liu, Meng-Yuan Huang, Chun-Yi Liu, Tsai-Hua Lee, Hsin-Ting Chang, Chih-Wei Jen, Nien-Hsiang Chang, Pei-Yun Tsai, Yen-Cheng Kuan, Shyh-Jye Jou:
A Millimeter Wave Digital CMOS Baseband Transceiver for Wireless LAN Applications. 275-278 - Bingwei Jiang, Howard C. Luong:
A 23-mW 60-GHz Differential Sub-Sampling PLL with an NMOS-Only Differential-Inductively-Tuned VCO. 279-282 - Zunsong Yang, Yong Chen, Pui-In Mak, Rui Paulo Martins:
A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS. 283-284 - Peilin Yang, Yanshu Guo, Hanjun Jiang, Zhihua Wang:
A 360-456 MHz PLL frequency synthesizer with digitally controlled charge pump leakage calibration. 285-286 - Zhengkun Shen, Heyi Li, Haoyun Jiang, Zherui Zhang, Junhua Liu, Huailin Liao:
A 12-GHz All-Digital Calibration-Free FMCW Signal Generator Based on a Retiming Fractional Frequency Divider. 287-290 - Cong Ding, Haixin Song, Woogeun Rhee, Zhihua Wang:
A 100Mb/s 3.5GHz Fully-Balanced BFOOK Modulator Based on Integer-N Hyrbrid PLL. 291-294 - Jeong Hoan Park, Tao Tang, Lian Zhang, Kian Ann Ng, Jerald Yoo:
A 15-Ch. 0.019 mm2/Ch. 0.43% Gain Mismatch Orthogonal Code Chopping Instrumentation Amplifier SoC for Bio-Signal Acquisition. 295-296 - Yu-Pin Hsu, Zemin Liu, Mona Mostafa Hella:
A 10 $\mu \mathrm{W}-74.6\mathrm{dB}$ THD Arterial Pulse Waveform Sensing System with Automatic Bridge-Offset Calibration and Super Class-AB Output Stage. 297-300 - Lian Zhang, Tao Tang, Jeong Hoan Park, Jerald Yoo:
A 0.012 mm2, $1.5 \mathrm{G}\Omega$ ZIN Intrinsic Feedback Capacitor Instrumentation Amplifier for Bio-Potential Recording and Respiratory Monitoring. 301-304 - Shinya Kajiyama, Yutaka Igarashi, Toru Yazaki, Yusaku Katsube, Takuma Nishimoto, Tatsuo Nakagawa, Yohei Nakamura, Yoshihiro Hayashi, Taizo Yamawaki:
T/R-Switch Composed of 3 High-Voltage MOSFETs with 12.1 µW Consumption that can Perform Per-channel TX to RX Self-Loopback AC Tests for 3D Ultrasound Imaging with 3072-channel Transceiver. 305-308 - Junhao Liang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins, Hanjun Jiang:
A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator. 309-312
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last updated on 2024-11-15 19:20 CET by the dblp team
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