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2020 – today
- 2024
[j36]Zhikang Chen, Yuejun Zhang
, Ziyu Zhou, Lixun Wang, Huihong Zhang, Pengjun Wang, Jinyan Xu:
An efficient ANN SoC for detecting Alzheimer's disease based on recurrent computing. Comput. Biol. Medicine 181: 108993 (2024)- [j35]Qikang Li, Yuejun Zhang, Lixun Wang, Huihong Zhang, Penjun Wang, Minghong Gu, Suling Xu:
Lightweight skin cancer detection IP hardware implementation using cycle expansion and optimal computation arrays methods. Comput. Biol. Medicine 183: 109258 (2024) - [j34]Donghao Xia, Yuejun Zhang, Yuanxin Tian, Mengfan Xu, Liang Wen:
High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme. Integr. 98: 102227 (2024) - [j33]Huihong Zhang, Zhiwei Zhao, Hongshuai Wei, Yuejun Zhang, Pengjun Wang:
Novel crosstalk circuit design for high density logic applications. Microelectron. J. 149: 106217 (2024) - [j32]Xuanxu Chen, Yuejun Zhang, Guangpeng Ai, Lixun Wang, Huihong Zhang, Xiangyu Li, Pengjun Wang:
Distance optimization KNN and EMD based lightweight hardware IP core design for EEG epilepsy detection. Microelectron. J. 151: 106335 (2024) - [j31]Li Ni, Pengjun Wang, Yuejun Zhang, Xiangyu Li, Gang Li, Lin Ding, Jiliang Zhang:
SI PUF: An SRAM and Inverter-Based PUF With a Bit Error Rate of 0.0053% and 0.073/0.042 pJ/bit. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2339-2343 (2024) - [c35]Chengjie Wang, Yuejun Zhang, Shengjie Fu, Lixun Wang:
A Physical Unclonable Function Feature Extraction Technique for Oil Paintings Copyright Protection. ITC-Asia 2024: 1-6 - 2023
- [j30]Minghong Gu, Yuejun Zhang, Yongzhong Wen, Guangpeng Ai, Huihong Zhang, Pengjun Wang, Guoqing Wang:
A lightweight convolutional neural network hardware implementation for wearable heart rate anomaly detection. Comput. Biol. Medicine 155: 106623 (2023) - [j29]Li Ni, Pengjun Wang, Yuejun Zhang, Gang Li, Lin Ding, Jiliang Zhang:
PI PUF: A Processor-Intrinsic PUF for IoT. Comput. Electr. Eng. 105: 108540 (2023) - [j28]Guangpeng Ai, Yuejun Zhang, Yongzhong Wen, Minghong Gu, Huihong Zhang, Pengjun Wang:
Convolutional neural network-based lightweight hardware IP core design for EEG epilepsy prediction. Microelectron. J. 137: 105810 (2023) - [j27]Lei Ni, Pengjun Wang, Yuejun Zhang, Huihong Zhang, Xiangyu Li, Li Ni, Jie Lv, Weifang Zheng:
Profiling side-channel attacks based on CNN model fusion. Microelectron. J. 139: 105901 (2023) - [j26]Xiangyu Li, Pengjun Wang, Gang Li, Yuejun Zhang:
Design of a Novel Self-Test-on-Chip Interface ASIC for Capacitive Accelerometers. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2834-2843 (2023) - [c34]Haonan He, Pengjun Wang, Xiangyu Li, Li Ni, Yuejun Zhang:
Highly Reliable Physical Unclonable Function Based on ZnO-SnO2 Gas Sensor. ASICON 2023: 1-4 - [c33]Hanyu Shi, Yuejun Zhang, Huihong Zhang, Qikang Li, Pengjun Wang:
Ternary Multiply-Accumulate Circuit Based on Domino Structure. ASICON 2023: 1-4 - [c32]Yuanxin Tian, Yuejun Zhang, Huihong Zhang, Liang Wen, Pengjun Wang, Zhiyi Li:
An Architecture of a Single-Event Tolerant D Flip-flop Using Full-Custom Design in 28nm Process. ASICON 2023: 1-4 - [c31]Yang Wang, Huihong Zhang, Yuejun Zhang, Hongshuai Wei, Pengjun Wang, Tengfei Yuan, Chengjie Wang:
High-Performance Rejection Sampling Hardware Circuit Design for Kyber. ASICON 2023: 1-4 - [c30]Hongshuai Wei, Yuejun Zhang, Huihong Zhang, Yang Wang, Tengfei Yuan, Chengjie Wang, Pengjun Wang:
An Efficient Hash Computing Unit for Kyber Algorithm. ASICON 2023: 1-4 - [c29]Mengfan Xu, Yuejun Zhang, Huihong Zhang, Liang Wen, Tengfei Yuan, Pengjun Wang, Zhiyi Li:
Full-custom Design of Improved Carry Adder Circuit for CLBs. ASICON 2023: 1-4 - [c28]Wanlong Zhao, Yuejun Zhang, Mingze Ren, Liang Wen, Pengjun Wang:
A 7nm-Based Decodable Self-Resetting Regfile Circuit. ASICON 2023: 1-4 - 2022
- [j25]Yongzhong Wen, Yuejun Zhang, Liang Wen, Haojie Cao, Guangpeng Ai, Minghong Gu, Pengjun Wang, Huiling Chen:
A 65nm/0.448 mW EEG processor with parallel architecture SVM and lifting wavelet transform for high-performance and low-power epilepsy detection. Comput. Biol. Medicine 144: 105366 (2022) - [j24]Yuejun Zhang, Qiufeng Wu, Pengjun Wang, Liang Wen, Zhicun Luan, Chongyan Gu:
TVD-PB logic circuit based on camouflaging circuit for IoT security. IET Circuits Devices Syst. 16(1): 40-52 (2022) - [j23]Li Ni, Pengjun Wang, Yuejun Zhang, Jia Chen, Huihong Zhang, Youyi Zhuang:
An ACF. Microelectron. J. 121: 105362 (2022) - [j22]Ye Lin, Yuejun Zhang, Shengjie Fu, Huihong Zhang, Pengjun Wang:
A configurable detection chip with ±0.6% Inaccuracy for liquid conductivity using dual-frequency sinusoidal signal technique in 65 nm CMOS. Microelectron. J. 124: 105434 (2022) - [j21]Shimin Du, Yang Runping, Yuejun Zhang, Yu Shenglu:
A stable voltage island-driven floorplanning with fixed-outline constraint for low power SoC. Microelectron. J. 128: 105536 (2022) - [j20]Jianguo Yang, Ruijun Lin, Keji Zhou, Yuejun Zhang, Xiaoyong Xue, Hangbing Lv:
A 28 nm 512 Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for high density and low BER cryptographic key in IoT devices. Microelectron. J. 128: 105550 (2022) - 2021
- [j19]Yuejun Zhang, Jiawei Wang, Pengjun Wang, Xiaoyong Xue, Xiaoyang Zeng:
Orthogonal obfuscation based key management for multiple IP protection. Integr. 77: 139-150 (2021) - [j18]Yuejun Zhang, Haiming Zhang, Pengjun Wang, Qiufeng Wu, Gang Li:
A 0.004% resolution & SAT. Integr. 78: 135-143 (2021) - [j17]Jia Chen, Pengjun Wang, Yuejun Zhang, Huihong Zhang:
SPUF design based on Camellia encryption algorithm. Microelectron. J. 112: 105051 (2021) - [j16]Gang Li, Pengjun Wang, Xuejiao Ma, Yijian Shi, Bo Chen, Yuejun Zhang:
A Multimode Configurable Physically Unclonable Function With Bit-Instability-Screening and Power-Gating Strategies. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 100-111 (2021) - [c27]Sheng Dai, Yuejun Zhang, Huihong Zhang, Jing Li, Ye Lin:
A ReRAM-based 10T2R SRAM Using Power-off Recovery Function for Reducing Power. ASICON 2021: 1-4 - [c26]Zhecheng Guo, Yuejun Zhang, Suling Xu, Zhixin Wu, Wanlong Zhao:
A Multi-conductance States Memristor-based CNN Circuit Using Quantization Method for Digital Recognition. ASICON 2021: 1-4 - [c25]Jinliang Han, Yongzhong Wen, Yuejun Zhang, Pengjun Wang, Huihong Zhang:
A 65nm Reliable Near-Subthreshold Standard Cells Design Using Schmitt Trigger. ASICON 2021: 1-4 - [c24]Jing Li, Yulin Zhao, Bo Peng, Xuanzhi Liu, Qiao Hu, Sheng Dai, Jianguo Yang, Yuejun Zhang:
A HfO2 Ferroelectric Capacitor based 10T2C High Reliability Non-Volatile SRAM for Low Power IoT Applications. ASICON 2021: 1-4 - [c23]Yang Li, Yuejun Zhang, Steve Yang, Shimin Du, Ye Lin:
A String-in-string-out 256 Bits eFuse Using Full-custom Design in 55nm Process. ASICON 2021: 1-4 - [c22]Li Ni, Pengjun Wang, Yuejun Zhang, Jia Chen, Liwei Li, Huihong Zhang:
A Reliable Multi-information Entropy Glitch PUF Using Schmitt Trigger Sampling Method for IoT Security. ASICON 2021: 1-4 - [c21]Zhixin Wu, Yuejun Zhang, Shimin Du, Zhecheng Guo, Wanlong Zhao:
A Three-valued Adder Circuit Implemented in ZnO Memristor with Multi-resistance States. ASICON 2021: 1-3 - 2020
- [j15]Liang Wen, Longmei Nan, Jing Zhang, Chunning Meng, Yan Lu, Shiqian Qi, Jianping Lv, Yuejun Zhang:
65 nm sub-threshold logic standard cell library using quasi-Schmitt-trigger design scheme and inverse narrow width effect aware sizing. IET Circuits Devices Syst. 14(3): 303-310 (2020) - [j14]Yuejun Zhang, Zhao Pan, Pengjun Wang, Xiaowei Zhang:
A Low Cost MST-FSM Obfuscation Method for Hardware IP Protection. J. Circuits Syst. Comput. 29(13): 2050208:1-2050208:21 (2020) - [j13]Liang Wen, Yuejun Zhang, Pengjun Wang:
Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1935-1939 (2020) - [j12]Gang Li, Pengjun Wang, Xuejiao Ma, Jiana Lian, Junpeng Shu, Yuejun Zhang:
A 215-F² Bistable Physically Unclonable Function With an ACF of <0.005 and a Native Bit Instability of 2.05% in 65-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2290-2299 (2020)
2010 – 2019
- 2019
- [j11]Liwei Li, Pengjun Wang, Yuejun Zhang:
Design of anti-key leakage camouflage gate circuit for reverse engineering based on dummy vias. Microelectron. J. 90: 163-168 (2019) - [j10]Yuejun Zhang, Zhao Pan, Pengjun Wang, Dailu Ding, Qiaoyan Yu:
A 0.1-pJ/b and ACF <0.04 Multiple-Valued PUF for Chip Identification Using Bit-Line Sharing Strategy in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1043-1052 (2019) - [j9]Liang Wen, Yuejun Zhang, Xiaoyang Zeng:
Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1470-1474 (2019) - [c20]Jiawei Wang, Yuejun Zhang, Pengjun Wang, Zhicun Luan, Xiaoyong Xue, Xiaoyang Zeng, Qiaoyan Yu:
An Orthogonal Algorithm for Key Management in Hardware Obfuscation. AsianHOST 2019: 1-4 - [c19]Liang Wen, Yu Liu, Wei Mo, Jing Zhang, Shiqian Qi, Jianping Lv, Yuejun Zhang:
A 96kb, 0.36V, Energy-Efficient 8T-SRAM with Column-Selection and Shared Buffer-Foot Techniques for EEG Processor. ASICON 2019: 1-4 - [c18]Xiaotian Zhang, Pengjun Wang, Yunfei Yu, Yuejun Zhang, Shunxin Ye:
A High-speed Dynamic Domino Full Adder Based on DICG Positive Feedback. ASICON 2019: 1-4 - [c17]Haiming Zhang, Pengjun Wang, Yuejun Zhang, Yunfei Yu:
Design of Aging Detection Sensor Based on Voltage Comparison. ASICON 2019: 1-3 - [c16]Zhiwei Zhao, Yuejun Zhang, Pengjun Wang, Huihong Zhang, Zhang Weishan:
Design of Crosstalk NAND Gate Circuit Based on Interconnect Coupling Capacitance. ASICON 2019: 1-4 - [c15]Xiaoyong Xue, Jianguo Yang, Yuejun Zhang, Mingyu Wang, Hangbing Lv, Xiaoyang Zeng, Ming Liu:
A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key. A-SSCC 2019: 29-32 - 2018
- [j8]Yuejun Zhang, Dailu Ding, Zhao Pan, Pengjun Wang, Qiaoyan Yu:
An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process. Microelectron. J. 78: 26-34 (2018) - [c14]Zhengyang He, Kai Ren, Jiayan Chen, Xinyi Dai, Zhao Pan, Yuejun Zhang:
Design of Delayed Ternary PUF Circuit Based on CNFET. APCC 2018: 503-507 - 2017
- [j7]Gang Li, Pengjun Wang, Yuejun Zhang, Huihong Zhang:
A multi-port low-power current mode PUF using MOSFET current-division deviation in 65 nm technology. Microelectron. J. 67: 169-175 (2017) - [c13]Gang Li, Pengjun Wang, Yuejun Zhang:
A highly reliable lightweight PUF circuit with temperature and voltage compensated for secure chip identification. ASICON 2017: 60-63 - [c12]Yaopeng Kang, Pengjun Wang, Yuejun Zhang, Gang Li:
Design of ternary pulsed reversible counter based on CNFET. ASICON 2017: 375-378 - 2016
- [c11]Jaya Dofe, Yuejun Zhang, Qiaoyan Yu:
DSD: A Dynamic State-Deflection Method for Gate-Level Netlist Obfuscation. ISVLSI 2016: 565-570 - 2015
- [j6]Tangbin Xia, Xiaoning Jin, Lifeng Xi, Yuejun Zhang, Jun Ni:
Operating load based real-time rolling grey forecasting for machine health prognosis in dynamic maintenance schedule. J. Intell. Manuf. 26(2): 269-280 (2015) - [j5]Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han, Xingxing Zhang, Zhang Zhang, Xu Cheng, Zhiyi Yu:
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1365-1369 (2015) - [c10]Yuejun Zhang, Pengjun Wang, Gang Li, Haoyu Qian, Xiaomin Zheng:
Design of power-up and arbiter hybrid physical unclonable functions in 65nm CMOS. ASICON 2015: 1-4 - 2014
- [j4]Yi Li, Liang Wen, Yuejun Zhang, Xu Cheng, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. IEICE Electron. Express 11(3): 20130992 (2014) - [c9]Yuejun Zhang, Pengjun Wang, Jianrui Li, Gang Li:
Design of threshold dominant delay Physical Unclonable Functions in 65nm CMOS. ISIC 2014: 324-327 - 2013
- [j3]Pengjun Wang, Yuejun Zhang, Jun Han, Zhiyi Yu, Yibo Fan, Zhang Zhang:
Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(5): 963-970 (2013) - [c8]Xuelong Zhang, Pengjun Wang, Yuejun Zhang:
Highly stable data SRAM-PUF in 65nm CMOS process. ASICON 2013: 1-4 - 2012
- [j2]Yuejun Zhang, Pengjun Wang, Baoyu Xiong, Zhiyi Yu:
Design of a high information-density multiple valued 2-read 1-write register file. IEICE Electron. Express 9(11): 958-964 (2012) - [j1]Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng:
A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. IEICE Electron. Express 9(16): 1355-1361 (2012) - 2011
- [c7]Yuejun Zhang, Pengjun Wang, Lipeng Hao:
Design of resistant DPA three-valued counter based on SABL. ASICON 2011: 9-12
2000 – 2009
- 2008
- [c6]Yuejun Zhang, Kinshuk, Ilkka Jormanainen, Erkki Sutinen:
An Implementation of the Agency Architecture in Educational Robotics. ICALT 2008: 194-198 - 2007
- [c5]Ilkka Jormanainen, Yuejun Zhang, Kinshuk, Erkki Sutinen:
Pedagogical Agents for Teacher Intervention in Educational Robotics Classes: Implementation Issues. DIGITEL 2007: 49-56 - 2006
- [c4]Ilkka Jormanainen, Yuejun Zhang, Erkki Sutinen, Kinshuk:
Agency Architecture for Teacher Intervention in Robotics Classes. ICALT 2006: 142-143 - [c3]Yuejun Zhang, Kinshuk, Øyvind Smestad, Jingyu Yang, Lynn Jeffrey:
Using Agents for Enhancing Learning Effects in an Advanced Discussion Forum. ICCE 2006: 157-164 - [c2]Ilkka Jormanainen, Chiara Moroni, Yuejun Zhang, Kinshuk, Erkki Sutinen:
Implementation of Intelligent Agents with Mobility in Educational Robotics Settings. WMTE 2006: 90-92 - 2005
- [c1]Yuejun Zhang, Kinshuk, Taiyu Lin:
An Open-ended Framework for Learning Object Metadata Interchange. ICCE 2005: 950-953
Coauthor Index
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