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2020 – today
- 2024
[j30]Jooyoung Bae
, Wonsik Oh, Jahyun Koo, Chengshuo Yu, Bongjin Kim:
CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully Parallel Spin Updates and Equalization of Spin States. IEEE J. Solid State Circuits 59(1): 173-183 (2024)- [j29]Woohyun Kwon, Hyosup Won, Taeho Kim, Sejun Jeon, Soon-Won Kwon, Ha-Il Song, Hanho Choi, Bongjin Kim, Huxian Jin, Jun-Gi Jo, Woosang Han, Tai-Young Kim, Gain Kim, Jake Eu, Jinho Park, Hyeon-Min Bae:
A 26-Gb/s Framed-Pulsewidth Modulation Transceiver for Extended Reach Optical Links. IEEE J. Solid State Circuits 59(8): 2506-2517 (2024) - [j28]Yuqi Su, Tony Tae-Hyoung Kim, Bongjin Kim:
FlexSpin: A CMOS Ising Machine With 256 Flexible Spin Processing Elements With 8-b Coefficients for Solving Combinatorial Optimization Problems. IEEE J. Solid State Circuits 59(8): 2659-2670 (2024) - [j27]Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim:
A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations. IEEE J. Solid State Circuits 59(8): 2706-2716 (2024) - [j26]Chengshuo Yu, Haoge Jiang, Junjie Mu, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim:
A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3672-3682 (2024) - [c45]Jooyoung Bae, Jahyun Koo, Chaeyun Shim, Bongjin Kim:
15.5 LISA: A 576×4 All-in-One Replica-Spins Continuous-Time Latch-Based Ising Computer Using Massively-Parallel Random-Number Generations and Replica Equalizations. ISSCC 2024: 284-286 - [c44]Jooyoung Bae, Chaeyun Shim, Bongjin Kim:
15.6 e-Chimera: A Scalable SRAM-Based Ising Macro with Enhanced-Chimera Topology for Solving Combinatorial Optimization Problems Within Memory. ISSCC 2024: 286-288 - [c43]Chaeyun Shim, Jooyoung Bae, Bongjin Kim:
30.3 VIP-Sat: A Boolean Satisfiability Solver Featuring 5×12 Variable In-Memory Processing Elements with 98% Solvability for 50-Variables 218-Clauses 3-SAT Problems. ISSCC 2024: 486-488 - [c42]Sai Sukruth Bezugam, Yihao Wu, JaeBum Yoo, Dmitri Strukov, Bongjin Kim:
Quantized Context Based LIF Neurons for Recurrent Spiking Neural Networks in 45nm. NICE 2024: 1-7 - [i1]Sai Sukruth Bezugam, Yihao Wu, JaeBum Yoo, Dmitri Strukov, Bongjin Kim:
Quantized Context Based LIF Neurons for Recurrent Spiking Neural Networks in 45nm. CoRR abs/2404.18066 (2024) - 2023
- [j25]Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin:
ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. IEEE J. Solid State Circuits 58(1): 243-255 (2023) - [j24]Junjie Mu, Bongjin Kim:
A Dynamic-Precision Bit-Serial Computing Hardware Accelerator for Solving Partial Differential Equations Using Finite Difference Method. IEEE J. Solid State Circuits 58(2): 543-553 (2023) - [j23]Chengshuo Yu, Junjie Mu, Yuqi Su, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim:
A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array. IEEE J. Solid State Circuits 58(8): 2372-2382 (2023) - [j22]Hyunjoon Kim, Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim:
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 70(4): 1580-1590 (2023) - [c41]Yuqi Su, Tony Tae-Hyoung Kim, Bongjin Kim:
A Reconfigurable lsing Machine for Boolean Satisfiability Problems Featuring Many-Body Spin Interactions. CICC 2023: 1-2 - [c40]Chengshuo Yu, Junjie Mu, Kevin Tshun-Chuan Chai, Tony T. Kim, Bongjin Kim:
A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates. CICC 2023: 1-2 - [c39]Zhengzhe Wei, Junjie Mu, Zhongzhiguang Lu, Yuanjin Zheng, Tony Tae-Hyoung Kim, Bongjin Kim:
A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing. ISCAS 2023: 1-5 - [c38]Qibang Zang, Wang Ling Goh, Lu Lu, Chengshuo Yu, Junjie Mu, Tony Tae-Hyoung Kim, Bongjin Kim, Dongrui Li, Anh Tuan Do:
282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing. ISCAS 2023: 1-5 - [c37]Jooyoung Bae, Wonsik Oh, Jahyun Koo, Bongjin Kim:
CTLE-Ising:A 1440-Spin Continuous-Time Latch-Based isling Machine with One-Shot Fully-Parallel Spin Updates Featuring Equalization of Spin States. ISSCC 2023: 142-143 - [c36]Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim:
A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j21]Tony Tae-Hyoung Kim, Bongjin Kim, Joo-Young Kim, Jaydeep P. Kulkarni:
Guest Editorial Revolution of AI and Machine Learning With Processing-in-Memory (PIM): From Systems, Architectures, to Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 333-337 (2022) - [j20]Donghyuk Kim, Chengshuo Yu, Shanshan Xie, Yuzong Chen, Joo-Young Kim, Bongjin Kim, Jaydeep P. Kulkarni, Tony Tae-Hyoung Kim:
An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 338-353 (2022) - [j19]Yuqi Su, Junjie Mu, Hyunjoon Kim, Bongjin Kim:
A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems. IEEE J. Solid State Circuits 57(3): 858-868 (2022) - [j18]Yuqi Su, Hyunjoon Kim, Bongjin Kim:
CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems. IEEE J. Solid State Circuits 57(7): 2263-2273 (2022) - [j17]Chengshuo Yu, Taegeun Yoo, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim:
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks. IEEE J. Solid State Circuits 57(11): 3466-3476 (2022) - [j16]Junjie Mu, Hyunjoon Kim, Bongjin Kim:
SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 69(6): 2412-2422 (2022) - [c35]Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim:
A Scalable Bit-Serial Computing Hardware Accelerator for Solving 2D/3D Partial Differential Equations Using Finite Difference Method. ESSCIRC 2022: 353-356 - [c34]Yuqi Su, Tony Tae-Hyoung Kim, Bongjin Kim:
FlexSpin: A Scalable CMOS Ising Machine with 256 Flexible Spin Processing Elements for Solving Complex Combinatorial Optimization Problems. ISSCC 2022: 1-3 - [c33]Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin:
A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. ISSCC 2022: 1-3 - 2021
- [j15]Hyunjoon Kim, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim:
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks. IEEE J. Solid State Circuits 56(7): 2221-2233 (2021) - [j14]Yuzong Chen, Lu Lu, Bongjin Kim, Tony Tae-Hyoung Kim:
A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications. IEEE Open J. Circuits Syst. 2: 210-222 (2021) - [j13]Chengshuo Yu, Taegeun Yoo, Hyunjoon Kim, Tony Tae-Hyoung Kim, Kevin Chai Tshun Chuan, Bongjin Kim:
A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 667-679 (2021) - [c32]Yuqi Su, Junjie Mu, Hyunjoon Kim, Bongjin Kim:
A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems. CICC 2021: 1-2 - [c31]Chengshuo Yu, Yuqi Su, Jaeho Lee, Kevin T. C. Chai, Bongjin Kim:
A 32x32 Time-Domain Wavefront Computing Accelerator for Path Planning and Scientific Simulations. CICC 2021: 1-2 - [c30]Chengshuo Yu, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim:
A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC. ESSCIRC 2021: 131-134 - [c29]Chengshuo Yu, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim:
A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC. ESSDERC 2021: 131-134 - [c28]Junjie Mu, Bongjin Kim:
A 21×21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method. ISSCC 2021: 406-408 - [c27]Junjie Mu, Yuqi Su, Bongjin Kim:
A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems. VLSI Circuits 2021: 1-2 - 2020
- [j12]Yuzong Chen, Lu Lu, Bongjin Kim, Tony Tae-Hyoung Kim:
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2636-2649 (2020) - [c26]Chengshuo Yu, Taegeun Yoo, Tony Tae-Hyoung Kim, Kevin Tshun Chuan Chai, Bongjin Kim:
A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC. CICC 2020: 1-4 - [c25]Qian Chen, Yuqi Su, Hyunjoon Kim, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim:
A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length. DATE 2020: 678-681 - [c24]Qian Chen, Yuan Liang, Bongjin Kim, Chirn Chye Boon:
A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter. ISCAS 2020: 1-5 - [c23]Yuzong Chen, Lu Lu, Bongjin Kim, Tony Tae-Hyoung Kim:
Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing. ISCAS 2020: 1-5 - [c22]Junjie Mu, Bongjin Kim:
A 65nm Logic-Compatible Embedded and Flash Memory for In-Memory Computation of Artificial Neural Networks. ISCAS 2020: 1-4 - [c21]Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim, Chengshuo Yu, Kevin Chai Tshun Chuan:
Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks. ISOCC 2020: 175-176 - [c20]Yuqi Su, Hyunjoon Kim, Bongjin Kim:
31.2 CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems. ISSCC 2020: 480-482
2010 – 2019
- 2019
- [c19]Hyunjoon Kim, Qian Chen, Bongjin Kim:
A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC. A-SSCC 2019: 35-36 - [c18]Hyunjoon Kim, Qian Chen, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim:
A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation. ESSCIRC 2019: 345-348 - [c17]Taegeun Yoo, Hyunjoon Kim, Qian Chen, Tony Tae-Hyoung Kim, Bongjin Kim:
A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks. ISLPED 2019: 1-6 - [c16]Hyunjoon Kim, Qian Chen, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim:
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks. ISOCC 2019: 166-167 - [c15]Bongjin Kim:
Mixed-Signal Circuits and Architectures for Energy-Efficient In-Memory and In-Sensor Computation of Artificial Neural Networks. SoCC 2019: 475-478 - 2018
- [c14]Gyusung Park, Minsu Kim, Chris H. Kim, Bongjin Kim, Vijay Reddy:
All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits. IRPS 2018: 5 - [c13]Kyeongha Kwon, Jong-Hyeok Yoon, Hanho Choi, Younho Jeon, Jaehyeok Yang, Bongjin Kim, Soon-Won Kwon, Minsik Kim, Sejun Jeon, Hyosup Won, Hyeon-Min Bae:
A 28Gb/s transceiver with chirp-managed EDC for DML systems. ISSCC 2018: 264-266 - 2017
- [j11]Somnath Kundu, Bongjin Kim, Chris H. Kim:
A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection. IEEE J. Solid State Circuits 52(3): 799-811 (2017) - 2016
- [c12]Somnath Kundu, Bongjin Kim, Chris H. Kim:
19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection. ISSCC 2016: 326-327 - 2015
- [j10]Youngjoo Lee, Bongjin Kim, Jaehwan Jung, In-Cheol Park:
Low-Complexity Tree Architecture for Finding the First Two Minima. IEEE Trans. Circuits Syst. II Express Briefs 62-II(1): 61-64 (2015) - [j9]Injae Yoo, Bongjin Kim, In-Cheol Park:
Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(12): 2920-2928 (2015) - [c11]Bongjin Kim, Hoon Ki Kim, Chris H. Kim:
An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier. CICC 2015: 1-4 - [c10]Somnath Kundu, Bongjin Kim, Chris H. Kim:
Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals. CICC 2015: 1-4 - [c9]Bongjin Kim, Somnath Kundu, Chris H. Kim:
A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit. VLSIC 2015: 140- - 2014
- [j8]Bongjin Kim, Weichao Xu, Chris H. Kim:
A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter. IEEE J. Solid State Circuits 49(4): 1017-1026 (2014) - [j7]Injae Yoo, Bongjin Kim, In-Cheol Park:
Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2711-2720 (2014) - [j6]Byeong Yong Kong, Jihyuck Jo, Hyewon Jeong, Mina Hwang, Soyoung Cha, Bongjin Kim, In-Cheol Park:
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1648-1652 (2014) - [c8]Bongjin Kim, Somnath Kundu, Seokkyun Ko, Chris H. Kim:
A VCO-based ADC employing a multi-phase noise-shaping beat frequency quantizer for direct sampling of Sub-1mV input signals. CICC 2014: 1-4 - [c7]Qianying Tang, Bongjin Kim, Yingjie Lao, Keshab K. Parhi, Chris H. Kim:
True Random Number Generator circuits based on single- and multi-phase beat frequency detection. CICC 2014: 1-4 - 2013
- [j5]Bongjin Kim, In-Cheol Park:
Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division. IEICE Trans. Commun. 96-B(7): 1772-1779 (2013) - [j4]Bongjin Kim, Injae Yoo, In-Cheol Park:
Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns. IEEE Trans. Circuits Syst. II Express Briefs 60-II(3): 162-166 (2013) - [c6]Bongjin Kim, Weichao Xu, Chris H. Kim:
A fully-digital beat-frequency based ADC achieving 39dB SNDR for a 1.6mVpp input signal. CICC 2013: 1-4 - [c5]Injae Yoo, Bongjin Kim, In-Cheol Park:
Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes. VTC Spring 2013: 1-5 - 2012
- [j3]Injae Yoo, Bongjin Kim, In-Cheol Park:
Immediate Exchange of Extrinsic Information for High-Throughput Turbo Decoding. IEEE Commun. Lett. 16(12): 2048-2051 (2012) - [j2]Dong Jiao, Bongjin Kim, Chris H. Kim:
Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation. IEEE J. Solid State Circuits 47(10): 2505-2516 (2012) - [c4]Pingqiang Zhou, Won Ho Choi, Bongjin Kim, Chris H. Kim, Sachin S. Sapatnekar:
Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications. ICCAD 2012: 263-270 - 2011
- [c3]Bongjin Kim, In-Cheol Park:
QC-LDPC Decoding Architecture based on Stride Scheduling. ISCAS 2011: 1319-1322 - 2010
- [c2]Bongjin Kim, Hasan Ahmed, In-Cheol Park:
Dual-rail decoding of low-density parity-check codes. ISCAS 2010: 477-480
2000 – 2009
- 2008
- [c1]Jongshin Shin, Jaehyun Park, Bongjin Kim, Jongjae Ryu, Chiwon Kim, Jiyoung Kim, Seung-Hee Yang, Hyungoo Kim, Jaewhui Kim:
A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer. CICC 2008: 237-240 - 2004
- [j1]Bongjin Kim, Byoung Soo Kim, David L. Skoug:
Integral transforms, convolution products, and first variations. Int. J. Math. Math. Sci. 2004(11): 579-598 (2004)
Coauthor Index
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