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    Sudhakar Reddy

    University of Iowa, Electrical and Computer Engineering, Faculty Member
    Papers
    Perspectives for high performance computing in workstation networksmore
    by Sudhakar Reddy
    Publication Date: 1996
    Publication Name: Lecture Notes in Computer Science
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    Application Processing and Decision Systems and Processesmore
    by Sudhakar Reddy
    Publication Date: Jul 5, 2006
    On compacting test response data containing unknown valuesmore
    by Sudhakar Reddy
    The design of a test response compactor called a Block Compactoris given. Block Compactors belong to a new class of compactorscalled Finite Memory Compactors. Different from spacecompactors, finite memory compactors contain memory... more
    The design of a test response compactor called a Block Compactoris given. Block Compactors belong to a new class of compactorscalled Finite Memory Compactors. Different from spacecompactors, finite memory compactors contain memory elements.Also unlike time compactors, finite memory compactors havefinite impulse response. These properties give finite memorycompactors the ability to achieve higher compaction ratios thanspace compactors and still be able to tolerate unknown values intest responses. The proposed Block Compactors, as an instance offinite memory compactors generate a signature of response data inseveral scan cycles. Results presented on several industrial designsshow that Block Compactors provide better test quality and higherdata compaction than earlier works on test response compactors.
    Publication Date: 2003
    Publication Name: ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)
    Research Interests:
    Heuristics for the placement of flip-flops in partial scan designs and the placement of signal boosters in lossy circuitsmore
    by Sudhakar Reddy
    ABSTRACT
    Publication Date: 1993
    Publication Name: The Sixth International Conference on VLSI Design
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    Delay Fault Models Based on Robust Propagation of Signal-Transitions +more
    by Sudhakar Reddy
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    Synthesis of testable sequential circuits: An overview of university activitiesmore
    by Sudhakar Reddy
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    Design of Easily Testable Microprocessors : A Case Studymore
    by Sudhakar Reddy
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    Itc
    On the Design of Random Pattern Testable PLAsmore
    by Sudhakar Reddy
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    Itc
    EXOP (Extended Operation): A new logical fault model for digital circuitsmore
    by Sudhakar Reddy
    ABSTRACT
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    On Timing Faults in Digital Logic Circuitsmore
    by Sudhakar Reddy
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    Testing-what's missing? An incomplete list of challengesmore
    by Sudhakar Reddy
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    Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approachmore
    by Sudhakar Reddy
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    Delay Fault Testing: How Robust are Our Models?more
    by Sudhakar Reddy
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    VTS
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    EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coveragemore
    by Sudhakar Reddy
    ABSTRACT
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    On Generating Test Sets that Remain Valid in the Presence of Undetected Faultsmore
    by Sudhakar Reddy
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    Design-for-Testability for Synchronous Sequential Circuits using Locally Available Linesmore
    by Sudhakar Reddy
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    On full reset as a design-for-testability techniquemore
    by Sudhakar Reddy
    ABSTRACT
    Publication Name: Proceedings of the IEEE International Conference on VLSI Design
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    TEMPLATES: A test generation procedure for synchronous sequential circuitsmore
    by Sudhakar Reddy
    ABSTRACT
    Publication Name: Proceedings of the Asian Test Symposium
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    Application of Tools Developed at the University of Iowa to ITC Benchmarksmore
    by Sudhakar Reddy
    ABSTRACT
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    Itc
    On synchronizing sequences and test sequence partitioningmore
    by Sudhakar Reddy
    ABSTRACT
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    A synthesis procedure for flexible logic functionsmore
    by Sudhakar Reddy
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    Delay fault models for VLSI circuits 1 Work supported in part by NSF Grant Nos. MIP9357581, and MIP9725053 1more
    by Sudhakar Reddy
    ABSTRACT
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    On avoiding undetectable faults during test generationmore
    by Sudhakar Reddy
    ABSTRACT
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    Application of Tools Developed at the University of Iowa to ITC-99 Benchmarksmore
    by Sudhakar Reddy
    ABSTRACT
    Publication Name: IEEE International Test Conference (TC)
    Research Interests:
    Itc
    VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuitsmore
    by Sudhakar Reddy
    ABSTRACT
    Publication Name: Proceedings of the IEEE International Conference on VLSI Design
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    On synchronizing sequences and unspecified values in output responses of synchronous sequential circuitsmore
    by Sudhakar Reddy
    ABSTRACT
    Publication Name: Proceedings of the IEEE International Conference on VLSI Design
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    Vector-based functional fault models for delay faultsmore
    by Sudhakar Reddy
    ABSTRACT
    Publication Name: Proceedings of the Asian Test Symposium
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    Test-point insertion to enhance test compaction for scan designsmore
    by Sudhakar Reddy
    ABSTRACT
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    Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generationmore
    by Sudhakar Reddy
    ABSTRACT
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    On the feasibility of fault simulation using partial circuit descriptionsmore
    by Sudhakar Reddy
    Publication Name: Proceedings of the Asian Test Symposium
    Research Interests:
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    PASTA: Partial scan to enhance test compactionmore
    by Sudhakar Reddy
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    High Performance/Delay Testingmore
    by Sudhakar Reddy
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    Ats
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    Fault diagnosis based on parameters of output responsesmore
    by Sudhakar Reddy
    ABSTRACT
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    A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuitsmore
    by Sudhakar Reddy
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    A partitioning and storage based built-in test pattern generation method for delay faults in scan circuitsmore
    by Sudhakar Reddy
    Publication Name: Proceedings of the Asian Test Symposium
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    Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codesmore
    by Sudhakar Reddy
    Publication Name: IEEE Transactions on Computers
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    Design of sequential machines for reliable fault diagnosismore
    by Sudhakar Reddy
    Improving the efficiency of static compaction based on chronological order enumeration of test sequencesmore
    by Sudhakar Reddy
    ABSTRACT
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    Nonpositive Hopfield Networks in Error Correcting Coding Applicationsmore
    by Sudhakar Reddy
    We consider a class of symmetric Hopfield Networks, with nonpositive synapses and zero thresholds and address a variety of design and analysis issues conected with Unidirectional Error Correcting Coding applications of this class. We show... more
    We consider a class of symmetric Hopfield Networks, with nonpositive synapses and zero thresholds and address a variety of design and analysis issues conected with Unidirectional Error Correcting Coding applications of this class. We show that this class is naturally suited to work in a unidirectional error environment We give a necessary and sufficient condition for a set of vectors to be storable in a Nonpositive Network. We propose a simple word storage algorithm, which is amenable to on line implementation, and guarantees storage of all storage compatible words. We show that the storage algorithm creates a maximally fault tolerant network which is free from spurious stationary points, whenever that freedom is possible. We also give a word forgetting algorithm; a tight, deterministic bound on the storage capacity, and give conditions under which the network created by our storage scheme tolerates a given number of arbitrary physical faults.
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    A DFT approach for path delay faults in interconnected circuitsmore
    by Sudhakar Reddy
    ABSTRACT
    Publication Name: Proceedings of the Asian Test Symposium
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    On interconnecting circuits with multiple scan chains for improved test data compressionmore
    by Sudhakar Reddy
    ABSTRACT
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    The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuitsmore
    by Sudhakar Reddy
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    The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faultsmore
    by Sudhakar Reddy
    ABSTRACT
    Publication Name: Proceedings of the IEEE International Conference on VLSI Design
    Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequencesmore
    by Sudhakar Reddy
    When multiple copies of the same functional unit are available in a design, fault detection can be achieved by comparing the output responses of two copies (or two identical circuits). This obviates the need for storing test responses or... more
    When multiple copies of the same functional unit are available in a design, fault detection can be achieved by comparing the output responses of two copies (or two identical circuits). This obviates the need for storing test responses or for computing signatures of test responses. The paper proposes the testing of identical circuits using a deterministic test sequence by running
    Research Interests:
    Fault Collapsing for Transition Faults Using Extended Transition Faultsmore
    by Sudhakar Reddy
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    Techniques for Reducing Power Dissipation During Test Application in Full Scan Circuitsmore
    by Sudhakar Reddy
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    Functional Broadside Tests with Different Levels of Reachabilitymore
    by Sudhakar Reddy
    ABSTRACT
    Publication Name: Proceedings of the IEEE International Conference on VLSI Design
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    On static test compaction and test pattern ordering for scan designsmore
    by Sudhakar Reddy
    ABSTRACT
    Publication Date: 2001
    Publication Name: Proceedings International Test Conference 2001 (Cat. No.01CH37260)
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    Diagnostic Test Generation Targeting Equivalence Classesmore
    by Sudhakar Reddy
    ABSTRACT
    Publication Name: Proceedings of the Asian Test Symposium
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    On the saturation of n-detection test sets with increased nmore
    by Sudhakar Reddy
    Publication Name: IEEE International Test Conference (TC)
    Research Interests:
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