Design for Testability

In the nanometer regime, especially the RF and analog circuits exhibit wide parameter variability, and consequently every chip produced needs to be tested. On-chip design for testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, artificial neural networks (ANN) are employed as multivariate regression technique to architect a general RF calibration scheme using DC- instead of RF stimuli. This relaxes the routing requirements on a chip for GHz test signals along with the reduction in test time and cost. The RF detector, a key element of a radio front-end DfT circuitry, designed in 65 nm CMOS is used to demonstrate the calibration scheme.

Design-for-testability (DFT) is widely used in current integrated circuit design to enhance the controllability and observability of signals. The technologies insert extra logics into an original design, running in test mode without any functional influence. How to make all the test logics work harmoniously and obtain high fault coverage with low area and performance overhead are the two main issues of DFT. Based on the design of a general-purposed CPU chip, this paper introduces some advanced topics to conquer the problems, including technologies of memory built-in-self-test (BIST), internal scan design, logic BIST, IEEE Std. 1149.1 (JTAG)-compatible boundary scan design and the correlations among them. These technologies offer a convenient and reliable DFT scheme for digital circuit designs, especially for large-scale ones, like a general-purpose CPU chip.

The cost of the test activity constitutes an important part of the total development cost. To make test easier (cost, time, and efforts), the consideration of test problems before the implementation phase is now necessary. This early consideration is known as Design for testability (DFT). The design of testable software does not consist solely in applying methods that improve the testability but also to verify if the degree of testability of the new obtained product is acceptable. This activity can be carried out using testability evaluation and a set of appropriate transformations. We propose a method based on the modeling of software by relations. The testability of a given specification is defined as a set of factors that influence the tests. These factors are evaluated separately and their values are gathered in a vector called the testability vector. The evaluation is based on the properties of a relation such as determinism, definissability, and informability. The method is us...

This paper presents a technique of re-using DFT logic for system functional and silicon debugging. By re-configuring the existing DFT logic implemented on an ASIC, we are able to 1) test each part of an ASIC in a system environment separately and thus locate manufacturing defects, 2) control and observe any state elements of an ASIC to facilitate system function

The embedded core testing methodology at Advanced Micro Devices Inc. Involves adopting a disciplined system for developing new products with a focus on time to market and engineering productivity. A key factor is to achieve high and verifiable fault coverage for designs by closely adhering to guidelines and by increased test automation. This paper addresses the design for test (DFT) aspects of the methodology, production testing of embedded CPU cores, and provides some data on completed designs

The latest innovation technology in computing devices has given a rise of compact, speedy and economical products which also embeds cryptography hardware on-chip. This device generally holds secret key and confidential information, more attention has been given to attacks on hardware which guards such secure information. The attacker may leak secret information from symmetric crypto-hardware (AES, DES etc.) using side-channel analysis, fault injection or exploiting existing test infrastructure. This paper examines various DFT based attack implementation method applied to cryptographic hardware. The paper contains an extensive analysis of attacks based on various parameters. The countermeasures are classified and analyzed in details.

In this paper, we present a comprehensive methodology for a formal, but intuitive, cause-effect dependency modeling using multi-signal directed graphs that correspond closely to hierarchical system schematics and develop diagnostic strategies to isolate faults in the shortest possible time without making the unrealistic single fault assumption. A key feature of our methodology is that our models lend naturally to real-world necessities, such as system integration and hierarchical troubleshooting

- This paper describes a real-time simulator of wind turbine generator system suitable for controller design and tests. The simulated generator is a grid-connected doubly fed induction machine with back-to-back PWM voltage source vector control at the rotor. The simulator ...

A technique for testing analog and mixed-signal linear cir-cuit components based on their impulse response (IR) sig-natures is presented in this paper. A simple DFT structure is proposed to enable the on-chip generation of the impulse response signatures from the ...

A Built-in self-test technique constitute a class of algorithms that provide the capability of performing at speed testing with high fault coverage, whereas at the same time they relax the reliance on expensive external testing equipment. Hence, they constitute a striking solution to the problem of testing VLSI devices. BIST techniques are typically classified into offline and online Concurrent BIST performs two modes of operations, test mode and normal mode during test mode the test generator (TG) result is compared with higher order bits and the output is given to comparator circuit. During normal operation mode the inputs to the CUT are driven from the normal inputs. The modified Decoder and SRAM is used to reduce the switching activity thus the dynamic power dissipation can be decrease. The output is verified by response verifier (RV) and the fault is recognizedby using testing. The operating speed is faster while the operation is carried out as parallel process and it is suitable for all the type of IC's and VLSI circuits.

This project presents a secure test wrapper (STW) design that is compatible with the IEEE 1500 standard. STW protects not only internal scan chains but also primary inputs and outputs, which may contain critical information (such as encryption keys) during the system operation. To reduce the STW area, flip-flops in the wrapper boundary cells also serve as the LFSR to generate the golden key. We propose to design a Cipher block chain based test wrapper design. We also propose the testing methodology based on Golden keys. We perform testing outside the module which provides high security. The designed module or block can be ported in to FPGA Processor. The system will be designed using Verilog HDL and simulated using Modalism Software.

We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses the existing functional logic; as a result, the design-for-testability (DFT) overhead on area or timing can be minimized. In this paper we show an algorithm which considers the test point insertion for reducing the area overhead for the full scan design. We also discuss its application to timing-driven partial scan design