Two general approaches to control unit design:

One approach views the controller as a sequential logic circuit or

finite state machine that generates specific sequence of control
signals in response to externally supplied instructions.

•It is designed with minimum number of components and maximize the speed
of operation.
• Once the unit is constructed ,the only way to implement changes in control
unit is by redesigning the entire unit—therefore said to be HARDWIRED.

Alternate method of designing program control unit is Micro

programmed control unit ,it is build around a storage unit called a
control memory, where all the control signals are stored in a program
like format.

•The control memory stores a set of micro programs designed to implement the
behavior of the given instruction set.
•Each instruction causes the corresponding micro program to be fetched and its
Control Unit Implementation
Hardwired
Memory Instruction code

Sequential . Control
Status Signals
Logic Circuits . signals

Micro programmed control unit

2
•Microprogramming control unit design is more systematic organization.

•The control signals are embedded in a kind of low-level software—firmware.

•Design changes can be easily made by modifying the contents of control

memory.

Disadvantages:

•Micro programmed control units are costly than hardwired.

•Slower because of the extra time required to fetch microinstructions from

the control memory

RISC /Application specific processors-----Micro programmed organization

3
 Hardwired
Method 1 (Classical method): The classical method of sequential circuit design is used. It attempts to
minimize the amount of Hardware in particular, by using only log 2P flip-flops to realize a P-state circuit.

Method 2 (One-hot encoding): An approach that uses one flip-flop per state and is known as the one-hot
method. While expensive in terms flip-flops; this method simplifies Control Unit design and debugging.
Definitions:
Control signals
◦ Group of bits used to select paths in
multiplexers, decoders, arithmetic logic
units
Control variables
◦ Binary variables specify microoperations
 Certain microoperations initiated while others
idle
Control word
◦ String of 1’s and 0’s represent control
variables

5
Definitions
 Control memory
◦ Memory contains control words
 Microinstructions
◦ Control words stored in control memory
◦ Specify control signals for execution of
microoperations
 Microprogram routine
◦ Sequence of microinstructions
◦ Each computer instruction has its own
micro program routine to generate micro
operations that execute the instruction

cpe 252: Computer Organization 6

Control Memory (its function)
 Read-only memory (ROM)
 Content of word in ROM at given address specifies
microinstruction
 Each computer instruction initiates series of
microinstructions (micro program) in control
memory.

 These microinstructions generate micro operations to

◦ Fetch instruction from main memory
◦ Evaluate effective address
◦ Execute operation specified by instruction
◦ Return control to fetch phase for next instruction

Control Control word

Address memory (microinstruction)
(ROM)
7
Micro Programmed Control Organization

CAR: Control Address Register

Memory Instruction code CDR: Control Data Register

Next Address Decoding . Control

Generator CAR Control CDR
Memory Circuit . signals
(sequencer)
Microprogrammed Control
Organization
External Next Address Control
input CDR Control
Generator CAR Memory word
(sequencer) (ROM)

 Control memory
◦ Contains microprograms (set of
microinstructions)
◦ Microinstruction contains
 Bits initiate microoperations
 Bits determine address of next microinstruction
 Control address register (CAR)
◦ Specifies address of next microinstruction

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 Microprogrammed Control
Organization
Next address generator (Micro program
sequencer)
◦ Determines address sequence for control
memory

Micro program sequencer functions (Important)

◦ Increment CAR by one
◦ Transfer external address into CAR
◦ Load initial address into CAR to start control
operations

10
 Microprogrammed Control
Organization
Control data register (CDR)- or pipeline
register
◦ Holds microinstruction read from control
memory
◦ Allows execution of microoperations
specified by control word simultaneously
with generation of next microinstruction
Control unit can
External
input operate
Next Address without
Control CDR
Control
Generator CAR Memory word
(sequencer) (ROM)

cpe 252: Computer Organization 11

Micro program Routines
(extra)
Subroutine
◦ Sequence of microinstructions used by
other routines to accomplish particular
task
Example
◦ Subroutine to generate effective
address of operand for memory
reference instruction
Subroutine register (SBR)
◦ Stores return address during
subroutine call
12
Conditional Branching (extra)
Branching from one routine to another
depends on status bit conditions
Status bits provide parameter info such as
◦ Carry-out of adder
◦ Sign bit of number
◦ Mode bits of instruction
Info in status bits can be tested and
actions initiated based on their conditions:
1 or 0
Unconditional branch
◦ Fix value of status bit to 1
13
Address Sequencing
Address sequencing capabilities
required in control unit explained
in next slide.
◦ Incrementing CAR
◦ Unconditional or conditional branch,
depending on status bit conditions
◦ Mapping from bits of instruction to
address for control memory
◦ Facility for subroutine call and return

14
Selection of address for
control memory
Instruction code

Mapping
logic

Status Branch MUX Multiplexers

bits logic select

Subroutine
Register
Control Address Register (SBR)
(CAR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

15
The diagram shows control memory and the associated H/W needed for
selecting the next microinstruction address.

The diagram shows four different paths from which the CAR receives the
address.---Address sequencing capabilities

•The Incrementer increments the content of the CAR by one, to select the next
microinstruction in sequence.

•Branching is achieved by specifying the branch address in one of the fields of the
microinstruction.

•Conditional branching is obtained by using a part of the microinstruction to select a

specific status bit in order to determine its condition.

•An external address is transferred into control memory via a mapping logic circuit.

The return address for a subroutine is stored in a special register whose

value is then used when the micro-program wishes to return from the sub-
routine.
Mapping of Instruction
Each computer instruction has its
own microprogram routine stored
in a given location of the control
memory
Mapping
◦ Transformation from instruction code
bits to address in control memory
where routine is located

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Mapping of Instruction
Example
◦ Mapping 4-bit operation code to 7-bit
address
OP-codes of Instructions
ADD 0000
0001
AND 0010 Control
LDA
memory
Mapping bits 0 xxxx 00
Address
0 0000 00 ADD Routine

0 0001 00 AND Routine

0 0010 00 LDA Routine

cpe 252: Computer Organization 18

Micro program Example
Computer instruction format
15 14 11 10 0
I Opcode Address

Four computer instructions

Symbol OP-code Description
EA is the effective address
ADD 0000 AC AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC  EA)
STORE 0010 M[EA]  AC
EXCHANGE 0011 AC M[EA], M[EA] 
AC

Microinstruction Format ( important)

3 3 3 2 2 7
F1 F2 F3 CD BR AD

F1, F2, F3: Microoperation fields

CD: Condition for branching
BR: Branch field
AD: Address field

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 Don’t read
Microinstruction Fields
F1 Microoperation Symbol F2 Microoperation Symbol
000 None NOP 000 None NOP
001 AC  AC + DR ADD 001 AC  AC - DR SUB
010 AC  0 CLRAC 010 AC  AC  DR OR
011 AC  AC + 1 INCAC 011 AC  AC  DR AND
100 AC  DR DRTAC 100 DR  M[AR] READ
101 AR  DR(0-10) DRTAR 101 DR  AC ACTDR
110 AR  PC PCTAR 110 DR  DR + 1 INCDR
111 M[AR]  DR WRITE 111 DR(0-10)  PC PCTDR

F3 Microoperation Symbol
000 None NOP
001 AC  AC  DR XOR
010 AC  AC’ COM
011 AC  shl AC SHL
100 AC  shr AC SHR
101 PC  PC + 1 INCPC
110 PC  AR ARTPC
111 Reserved

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Microinstruction Fields
Don’t read

CD Condition Symbol Comments

00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC

BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
10 RET CAR  SBR (Return from subroutine)
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0

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Fetch Routine
 Fetch routine Don’t read
- Read instruction from memory
- Decode instruction and update PC
Microinstructions for fetch routine:
AR PC
DR  M[AR], PC  PC + 1
AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0

Symbolic microprogram for fetch routine:

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP

Binary microporgram for fetch routine:

Binary
address F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000

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Binary Microprogram Don’t read

Address Binary Microinstruction

Micro Routine Decimal Binary F1 F2 F3 CD BR
AD
ADD 0 0000000 000 000 000 01 01 1000011
1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00
1000000
3 0000011 000 000 000 00 00
1000000
BRANCH 4 0000100 000 000 000 10 00 0000110
5 0000101 000 000 000 00 00 1000000
6 0000110 000 000 000 01 01 1000011
7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011
9 0001001 000 101 000 00 00 0001010
10 0001010 111 000 000 00 00
1000000
11 0001011 000 000 000 00 00
1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011
13 0001101 001 000 000 00 00
0001110
14 0001110 100 101 000 00 00
0001111
15 0001111 111 000 000 00 00
1000000

FETCH 64 1000000 110 000 000 00 00 1000001

Microprogram Sequencer
External
(MAP)

L
I0 3 2 1 0
Input Load
I1 logic S1 MUX1 SBR
T S0

1 Incrementer
I MUX2 Test
S
Z Select
Clock CAR

Control memory

Microops CD BR AD
... ...

24
The control memory is included in the diagram to show the interaction between
the sequencer and memory.

There are two MUX’s in the circuit. The first MUX selects an address from one of four
Sources

1. The Incrementer increments the content of the CAR by one, to select the next
microinstruction in sequence.

2. Branching is achieved by specifying the branch address in one of the fields

of the microinstruction.

3. Conditional branching is obtained by using a part of the microinstruction

to select a specific status bit in order to determine its condition.

4. An external address is transferred into control memory via a mapping logic circuit.

• The CD field of the microinstruction selects one of the status bits in the second MUX .

• If the bit selected is equal to 1,the T (test)variable is equal to 1;otherwise ,it is equal to 0

The T value together with two bits from the BR (branch) field go to an input logic circuit.
The input logic circuit has three inputs I0,I1 and T and three outputs S0,S1 and L.

Variables S0 and S1 select one of the source addresses for CAR.

Variable L enables the load input in SBR.

The binary values of the two selection variables determine the path in the MUX.

The I1 and I0 are identical to the bit values in the BR field.

The bit values for s1 & s0 are determined from the stated function and path in the
Multiplexer that establishes the required transfer .
The SBR register is loaded with the incremented value of CAR during a call
Micro instruction (BR=01) provided that the status bit condition is satisfied (T=1).

The truth table can be used to obtain the simplified boolean functions for the input logic.

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