Unit 2 – Microprogrammed Control

Hardwired Control Unit:

When the control signals are generated by hardware using conventional logic design techniques,
the control unit is said to be hardwired.

Micro programmed control unit:

A control unit whose binary control variables are stored in memory is called a micro programmed
control unit.

Dynamic microprogramming:
A more advanced development known as dynamic microprogramming permits a microprogram to
be loaded initially from an auxiliary memory such as a magnetic disk. Control units that use
dynamic microprogramming employ a writable control memory. This type of memory can be
used for writing.

Control Memory:
Control Memory is the storage in the microprogrammed control unit to store the microprogram.

Writeable Control Memory:

Control Storage whose contents can be modified, allow the change in microprogram and
Instruction set can be changed or modified is referred as Writeable Control Memory.

Control Word:
The control variables at any given time can be represented by a control word string of 1 's and 0's
called a control word.

Microoperation, Microinstruction, Micro program, Microcode.

Microoperations:
 In computer central processing units, micro-operations (also known as a micro-ops or
μops) are detailed low-level instructions used in some designs to implement complex
machine instructions (sometimes termed macro-instructions in this context).

Micro instruction:
 A symbolic microprogram can be translated into its binary equivalent by means of an
assembler.
 Each line of the assembly language microprogram defines a symbolic microinstruction.
 Each symbolic microinstruction is divided into five fields: label, microoperations, CD,
BR, and AD.

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 Unit 2 – Microprogrammed Control

Micro program:
 A sequence of microinstructions constitutes a microprogram.
 Since alterations of the microprogram are not needed once the control unit is in operation,
the control memory can be a read-only memory (ROM).
 ROM words are made permanent during the hardware production of the unit.
 The use of a micro program involves placing all control variables in words of ROM for
use by the control unit through successive read operations.
 The content of the word in ROM at a given address specifies a microinstruction.

Microcode:
 Microinstructions can be saved by employing subroutines that use common sections of
microcode.
 For example, the sequence of micro operations needed to generate the effective address of
the operand for an instruction is common to all memory reference instructions.
 This sequence could be a subroutine that is called from within many other routines to
execute the effective address computation.

Organization of micro programmed control unit

 The general configuration of a micro-programmed control unit is demonstrated in the
block diagram of Figure 4.1.
 The control memory is assumed to be a ROM, within which all control information is
permanently stored.

figure 4.1: Micro-programmed control organization

 The control memory address register specifies the address of the microinstruction, and the
control data register holds the microinstruction read from memory.
 The microinstruction contains a control word that specifies one or more microoperations
for the data processor. Once these operations are executed, the control must determine the
next address.
 The location of the next microinstruction may be the one next in sequence, or it may be
located somewhere else in the control memory.

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 Microprogrammed Control

 While the microoperations are being executed, the next address is computed in the next
address generator circuit and then transferred into the control address register to read the
next microinstruction.
 Thus a microinstruction contains bits for initiating microoperations in the data processor
part and bits that determine the address sequence for the control memory.
 The next address generator is sometimes called a micro-program sequencer, as it
determines the address sequence that is read from control memory.
 Typical functions of a micro-program sequencer are incrementing the control address
register by one, loading into the control address register an address from control memory,
transferring an external address, or loading an initial address to start the control
operations.
 The control data register holds the present microinstruction while the next address is
computed and read from memory.
 The data register is sometimes called a pipeline register.
 It allows the execution of the microoperations specified by the control word
simultaneously with the generation of the next microinstruction.
 This configuration requires a two-phase clock, with one clock applied to the address
register and the other to the data register.
 The main advantage of the micro programmed control is the fact that once the hardware
configuration is established; there should be no need for further hardware or wiring
changes.
 If we want to establish a different control sequence for the system, all we need to do is
specify a different set of microinstructions for control memory.

Address Sequencing
 Microinstructions are stored in control memory in groups, with each group specifying a
routine.
 To appreciate the address sequencing in a micro-program control unit, let us specify the
steps that the control must undergo during the execution of a single computer instruction.

Step-1:
 An initial address is loaded into the control address register when power is turned on in
the computer.
 This address is usually the address of the first microinstruction that activates the
instruction fetch routine.
 The fetch routine may be sequenced by incrementing the control address register through
the rest of its microinstructions.
 At the end of the fetch routine, the instruction is in the instruction register of the
computer.

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 Microprogrammed Control

Step-2:
 The control memory next must go through the routine that determines the effective
address of the operand.
 A machine instruction may have bits that specify various addressing modes, such as
indirect address and index registers.
 The effective address computation routine in control memory can be reached through a
branch microinstruction, which is conditioned on the status of the mode bits of the
instruction.
 When the effective address computation routine is completed, the address of the operand
is available in the memory address register.

Step-3:
 The next step is to generate the microoperations that execute the instruction fetched from
memory.
 The microoperation steps to be generated in processor registers depend on the operation
code part of the instruction.
 Each instruction has its own micro-program routine stored in a given location of control
memory.
 The transformation from the instruction code bits to an address in control memory where
the routine is located is referred to as a mapping process.
 A mapping procedure is a rule that transforms the instruction code into a control
memory address.
Step-4:
 Once the required routine is reached, the microinstructions that execute the instruction
may be sequenced by incrementing the control address register.
 Micro-programs that employ subroutines will require an external register for storing the
return address.
 Return addresses cannot be stored in ROM because the unit has no writing capability.
 When the execution of the instruction is completed, control must return to the fetch
routine.
 This is accomplished by executing an unconditional branch microinstruction to the first
address of the fetch routine.

In summary, the address sequencing capabilities required in a control memory are:

1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on status bit conditions.
3. A mapping process from the bits of the instruction to an address for control memory.
4. A facility for subroutine call and return.

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 Microprogrammed Control

selection of address for control memory

Figure 4.2: Selection of address for control memory

 Above figure 4.2 shows a block diagram of a control memory and the associated hardware
needed for selecting the next microinstruction address.
 The microinstruction in control memory contains a set of bits to initiate microoperations
in computer registers and other bits to specify the method by which the next address is
obtained.
 The diagram shows four different paths from which the control address register (CAR)
receives the address.
 The incrementer increments the content of the control address register by one, to select the
next microinstruction in sequence.
 Branching is achieved by specifying the branch address in one of the fields of the
microinstruction.
 Conditional branching is obtained by using part of the microinstruction to select a specific
status bit in order to determine its condition.
 An external address is transferred into control memory via a mapping logic circuit.
 The return address for a subroutine is stored in a special register whose value is then used
when the micro-program wishes to return from the subroutine.

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 Microprogrammed Control

 The branch logic of figure 4.2 provides decision-making capabilities in the control unit.
 The status conditions are special bits in the system that provide parameter information
such as the carry-out of an adder, the sign bit of a number, the mode bits of an instruction,
and input or output status conditions.
 The status bits, together with the field in the microinstruction that specifies a branch
address, control the conditional branch decisions generated in the branch logic.
 A 1 output in the multiplexer generates a control signal to transfer the branch address
from the microinstruction into the control address register.
 A 0 output in the multiplexer causes the address register to be incremented.

Mapping of an Instruction
 A special type of branch exists when a microinstruction specifies a branch to the first
word in control memory where a microprogram routine for an instruction is located.
 The status bits for this type of branch are the bits in the operation code part of the
instruction.
For example, a computer with a simple instruction format as shown in figure 4.3 has an
operation code of four bits which can specify up to 16 distinct instructions.
 Assume further that the control memory has 128 words, requiring an address of seven
bits.
 One simple mapping process that converts the 4-bit operation code to a 7-bit address for
control memory is shown in figure 4.3.
 This mapping consists of placing a 0 in the most significant bit of the address, transferring
the four operation code bits, and clearing the two least significant bits of the control
address register.
 This provides for each computer instruction a microprogram routine with a capacity of
four microinstructions.
 If the routine needs more than four microinstructions, it can use addresses 1000000
through 1111111. If it uses fewer than four microinstructions, the unused memory
locations would be available for other routines.

Figure 4.3: Mapping from instruction code to microinstruction

address

 One can extend this concept to a more general mapping rule by using a ROM to specify
the mapping function.
 The contents of the mapping ROM give the bits for the control address register.

6
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 Microprogrammed Control

 In this way the microprogram routine that executes the instruction can be placed in any
desired location in control memory.
 The mapping concept provides flexibility for adding instructions for control memory as
the need arises.

Computer Hardware Configuration

Figure 4.4: Computer hardware configuration

The block diagram of the computer is shown in Figure 4.4. It consists of
1. Two memory units:
Main memory -> for storing instructions and data, and
Control memory -> for storing the microprogram.
2. Six Registers:
Processor unit register: AC(accumulator),PC(Program Counter), AR(Address Register),
DR(Data Register)
Control unit register: CAR (Control Address Register), SBR(Subroutine Register)
3. Multiplexers:
The transfer of information among the registers in the processor is done through
multiplexers rather than a common bus.
4. ALU:
The arithmetic, logic, and shift unit performs microoperations with data from AC and DR
and places the result in AC.

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 Unit 2 – Microprogrammed Control

 DR can receive information from AC, PC, or memory.

 AR can receive information from PC or DR.
 PC can receive information only from AR.
 Input data written to memory come from DR, and data read from memory can go only to
DR.

Microinstruction Format
The microinstruction format for the control memory is shown in figure 4.5. The 20 bits of the
microinstruction are divided into four functional parts as follows:
1. The three fields F1, F2, and F3 specify microoperations for the computer.
The microoperations are subdivided into three fields of three bits each. The three bits in
each field are encoded to specify seven distinct microoperations. This gives a total of 21
microoperations.
2. The CD field selects status bit conditions.
3. The BR field specifies the type of branch to be used.
4. The AD field contains a branch address. The address field is seven bits wide, since the
control memory has 128 = 27 words.

Figure 4.5: Microinstruction Format

 As an example, a microinstruction can specify two simultaneous microoperations from
F2 and F3 and none from F1.
DR M[AR] with F2 = 100
PC PC + 1 with F3 = 101
 The nine bits of the microoperation fields will then be 000 100 101.
 The CD (condition) field consists of two bits which are encoded to specify four status bit
conditions as listed in Table 4.1.

Table 4.1: Condition Field

 The BR (branch) field consists of two bits. It is used, in conjunction with the address field
AD, to choose the address of the next microinstruction shown in Table 4.2.

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 Microprogrammed Control

Table 4.2: Branch Field

Symbolic Microinstruction.
 Each line of the assembly language microprogram defines a symbolic microinstruction.
 Each symbolic microinstruction is divided into five fields: label, microoperations, CD,
BR, and AD. The fields specify the following Table 4.3.

1. Label The label field may be empty or it may specify a symbolic

address. A label is terminated with a colon (:).
2. Microoperations It consists of one, two, or three symbols, separated by
commas, from those defined in Table 5.3. There may be no
more than one symbol from each F field. The NOP symbol
is used when the microinstruction has no microoperations.
This will be translated by the assembler to nine zeros.
3. CD The CD field has one of the letters U, I, S, or Z.
4. BR The BR field contains one of the four symbols defined in
Table 5.2.
5. AD The AD field specifies a value for the address field of the
microinstruction in one of three possible ways:
i. With a symbolic address, this must also appear as a
label.
ii. With the symbol NEXT to designate the next
address in sequence.
iii. When the BR field contains a RET or MAP symbol,
the AD field is left empty and is converted to seven
zeros by the assembler.
Table 4.3: Symbolic Microinstruction

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 Microprogrammed Control

Micro programmed sequencer for a control memory

Microprogram sequencer:
 The basic components of a microprogrammed control unit are the control memory and the
circuits that select the next address.
 The address selection part is called a microprogram sequencer.
 A microprogram sequencer can be constructed with digital functions to suit a particular
application.
 To guarantee a wide range of acceptability, an integrated circuit sequencer must provide
an internal organization that can be adapted to a wide range of applications.
 The purpose of a microprogram sequencer is to present an address to the control memory
so that a microinstruction may be read and executed.
 Commercial sequencers include within the unit an internal register stack used for
temporary storage of addresses during microprogram looping and subroutine calls.
 Some sequencers provide an output register which can function as the address register for
the control memory.
 The block diagram of the microprogram sequencer is shown in figure 4.6.
 There are two multiplexers in the circuit.
 The first multiplexer selects an address from one of four sources and routes it into a
control address register CAR.
 The second multiplexer tests the value of a selected status bit and the result of the test is
applied to an input logic circuit.
 The output from CAR provides the address for the control memory.
 The content of CAR is incremented and applied to one of the multiplexer inputs and to
the subroutine registers SBR.
 The other three inputs to multiplexer 1 come from the address field of the present
microinstruction, from the output of SBR, and from an external source that maps the
instruction.
 Although the figure 4.6 shows a single subroutine register, a typical sequencer will have a
register stack about four to eight levels deep. In this way, a number of subroutines can be
active at the same time.
 The CD (condition) field of the microinstruction selects one of the status bits in the
second multiplexer.
 If the bit selected is equal to 1, the T (test) variable is equal to 1; otherwise, it is equal to
0.
 The T value together with the two bits from the BR (branch) field goes to an input logic
circuit.
 The input logic in a particular sequencer will determine the type of operations that are
available in the unit.

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 Microprogrammed Control

l0 Input 3 2 1 0
Load
S MU
l1 Logic 1 X 1 SBR
S
T 0

1
Test Increment
MUX 2
L Clock CAR
Select

Control
Memory
Microo AD
ps CD BR

Figure 4.6: Microprogram Sequencer for a control memory

Input Logic : Truth Table

BR Input MUX 1 Load SBR
I1 I0 T S1 S0 L
00 0 0 0 0 0 0
00 0 0 1 0 1 0
01 0 1 0 0 0 0
01 0 1 1 0 1 1
10 1 0 X 1 0 0
11 1 1 X 1 1 0
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 Table 4.4: Input Logic Truth Table for Microprogram Sequencer

Microprogrammed Control

Boolean Function:
S0 = I0
S1 = I0I1 + I0’T
L = I0’I1T

 Typical sequencer operations are: increment, branch or jump, call and return from
subroutine, load an external address, push or pop the stack, and other address sequencing
operations.
 With three inputs, the sequencer can provide up to eight address sequencing operations.
 Some commercial sequencers have three or four inputs in addition to the T input and thus
provide a wider range of operations.

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Computer Organization and Architecture Chapter 2 : Central Processing Unit

Chapter – 2
Central Processing Unit

The part of the computer that performs the bulk of data processing operations is called the
Central Processing Unit (CPU) and is the central component of a digital computer. Its purpose is
to interpret instruction cycles received from memory and perform arithmetic, logic and control
operations with data stored in internal register, memory words and I/O interface units. A CPU is
usually divided into two parts namely processor unit (Register Unit and Arithmetic Logic Unit)
and control unit.

Fig: Components of CPU

Processor Unit:
The processor unit consists of arithmetic unit, logic unit, a number of registers and internal buses
that provides data path for transfer of information between register and arithmetic logic unit. The
block diagram of processor unit is shown in figure below where all registers are connected
through common buses. The registers communicate each other not only for direct data transfer
but also while performing various micro-operations.

Here two sets of multiplexers select register which perform input data for ALU. A decoder
selects destination register by enabling its load input. The function select in ALU determines the
particular operation that to be performed.

For an example to perform the operation: R3  R1 + R2

1. MUX A selector (SELA): to place the content of R1 into bus A.
2. MUX B selector (SELB): to place the content of R2 into bus B.
3. ALU operation selector (OPR): to provide arithmetic addition A + B.
4. Decoder destination selector (SELD): to transfer the content of the output bus into R3.
Computer Organization and Architecture Chapter 2 : Central Processing Unit

Fig: Processor Unit

Control unit:
The control unit is the heart of CPU. It consists of a program counter, instruction register, timing
and control logic. The control logic may be either hardwired or micro-programmed. If it is a
hardwired, register decodes and a set of gates are connected to provide the logic that determines
the action required to execute various instructions. A micro-programmed control unit uses a
control memory to store micro instructions and a sequence to determine the order by which the
instructions are read from control memory.

The control unit decides what the instructions mean and directs the necessary data to be moved
from memory to ALU. Control unit must communicate with both ALU and main memory and
coordinates all activities of processor unit, peripheral devices and storage devices. It can be
characterized on the basis of design and implementation by:
 Defining basic elements of the processor
 Describing the micro-operation that processor performs
 Determining the function that the control unit must perform to cause the micro-operations
to be performed.
Control unit must have inputs that allow determining the state of system and outputs that allow
controlling the behavior of system.

The input to control unit are:

 Flag: flags are headed to determine the status of processor and outcome of previous ALU
operation.
Computer Organization and Architecture Chapter 2 : Central Processing Unit

 Clock: All micro-operations are performed within each clock pulse. This clock pulse is
also called as processor cycle time or clock cycle time.

 Instruction Register: The op-code of instruction determines which micro-operation to

perform during execution cycle.

 Control signal from control bus: The control bus portion of system bus provides interrupt,
acknowledgement signals to control unit.

The outputs from control unit are:

 Control signal within processor: These signals causes data transfer between registers,
activate ALU functions.

 Control signal to control bus: These are signals to memory and I/O module. All these
control signals are applied directly as binary inputs to individual logic gate.

Fig: Control Unit

2.1 CPU Structure and Function

Processor Organization
 Things a CPU must do:
- Fetch Instructions
- Interpret Instructions
- Fetch Data
- Process Data
- Write Data
Computer Organization and Architecture Chapter 2 : Central Processing Unit

Fig: The CPU with the System Bus

 A small amount of internal memory, called the registers, is needed by the CPU to fulfill
these requirements

Fig: Internal Structure of the CPU

 Components of the CPU
- Arithmetic and Logic Unit (ALU): does the actual computation or processing of
data
- Control Unit (CU): controls the movement of data and instructions into and out of
the CPU and controls the operation of the ALU.

Register Organization
 Registers are at top of the memory hierarchy. They serve two functions:
1. User-Visible Registers - enable the machine- or assembly-language programmer
to minimize main-memory references by optimizing use of registers
2. Control and Status Registers - used by the control unit to control the operation
Computer Organization and Architecture Chapter 2 : Central Processing Unit

of the CPU and by privileged, OS programs to control the execution of programs

User-Visible Registers
Categories of Use
- General Purpose registers - for variety of functions
- Data registers - hold data
- Address registers - hold address information
- Segment pointers - hold base address of the segment in use
- Index registers - used for indexed addressing and may be auto indexed
- Stack Pointer - a dedicated register that points to top of a stack. Push, pop, and
other stack instructions need not contain an explicit stack operand.
- Condition Codes (flags)

Design Issues
 Completely general-purpose registers or specialized use?
- Specialized registers save bits in instructions because their use can be implicit
- General-purpose registers are more flexible
- Trend is toward use of specialized registers
 Number of registers provided?
- More registers require more operand specifier bits in instructions
- 8 to 32 registers appears optimum (RISC systems use hundreds, but are a
completely different approach)
 Register Length?
- Address registers must be long enough to hold the largest address
- Data registers should be able to hold values of most data types
- Some machines allow two contiguous registers for double-length values
 Automatic or manual save of condition codes?
- Condition restore is usually automatic upon call return
- Saving condition code registers may be automatic upon call instruction, or may be
manual

Control and Status Registers

 Essential to instruction execution
- Program Counter (PC)
- Instruction Register (IR)
- Memory Address Register (MAR) - usually connected directly to address lines
of bus
- Memory Buffer Register (MBR) - usually connected directly to data lines of bus
 Program Status Word (PSW) - also essential, common fields or flags contained
include:
- Sign - sign bit of last arithmetic operation
- Zero - set when result of last arithmetic operation is 0
- Carry - set if last op resulted in a carry into or borrow out of a high-order bit
- Equal - set if a logical compare result is equality
- Overflow - set when last arithmetic operation caused overflow
- Interrupt Enable/Disable - used to enable or disable interrupts
- Supervisor - indicates if privileged ops can be used
Computer Organization and Architecture Chapter 2 : Central Processing Unit

 Other optional registers

- Pointer to a block of memory containing additional status info (like process
control blocks)
- An interrupt vector
- A system stack pointer
- A page table pointer
- I/O registers
 Design issues
- Operating system support in CPU
- How to divide allocation of control information between CPU registers and first
part of main memory (usual tradeoffs apply)

Fig: Example Microprocessor Register Organization

The Instruction Cycle

Basic instruction cycle contains the following sub-cycles.
 Fetch - read next instruction from memory into CPU
 Execute - Interpret the opcode and perform the indicated operation
 Interrupt - if interrupts are enabled and one has occurred, save the current process
state and service the interrupt
Computer Organization and Architecture Chapter 2 : Central Processing Unit

Fig: Instruction Cycles

Fig: Instruction Cycle State Diagram

The Indirect Cycle

- Think of as another instruction sub-cycle
- May require just another fetch (based upon last fetch)
- Might also require arithmetic, like indexing

Fig: Instruction Cycle with Indirect

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Computer Organization and Architecture Chapter 2 : Central Processing Unit

Data Flow
- Exact sequence depends on CPU design
- We can indicate sequence in general terms, assuming CPU employs:
 a memory address register (MAR)
 a memory buffer register (MBR)
 a program counter (PC)
 an instruction register (IR)
Fetch cycle data flow
- PC contains address of next instruction to be fetched
- This address is moved to MAR and placed on address bus
- Control unit requests a memory read
- Result is
 placed on data bus
 result copied to MBR
 then moved to IR
- Meanwhile, PC is incremented

Fig: Data flow, Fetch Cycle

t1: MAR  (PC)

t2: MBR  Memory
PC  PC + 1
t3: IR(Address)  (MBR(Address))

Indirect cycle data flow

- Decodes the instruction
- After fetch, control unit examines IR to see if indirect addressing is being used. If so:
- Rightmost n bits of MBR (the memory reference) are transferred to MAR
- Control unit requests a memory read, to get the desired operand address into the
MBR
Computer Organization and Architecture Chapter 2 : Central Processing Unit

t1: MAR  (IR(Address))

t2: MBR  Memory
t3: IR(Address)  (MBR(Address))

Fig: Data Flow, Indirect Cycle

Execute cycle data flow

- Not simple and predictable, like other cycles
- Takes many forms, since form depends on which of the various machine instructions
is in the IR
- May involve
 transferring data among registers
 read or write from memory or I/O
 invocation of the ALU
For example: ADD R1, X
t1: MAR  (IR(Address))
t2: MBR  Memory
t3: R1  (R1) + (MBR)

Interrupt cycle data flow

- Current contents of PC must be saved (for resume after interrupt), so PC is
transferred to MBR to be written to memory
- Save location’s address (such as a stack ptr) is loaded into MAR from the control unit
- PC is loaded with address of interrupt routine (so next instruction cycle will begin by
fetching appropriate instruction)
t1: MBR  (PC)
t2: MAR  save_address
PC  Routine_address
t3: Memory  (MBR)
Computer Organization and Architecture Chapter 2 : Central Processing Unit

Fig: Data Flow, Interrupt Cycle

2.2 Arithmetic and Logic Unit

ALU is the combinational circuit of that part of computer that actually performs arithmetic and
logical operations on data. All of the other elements of computer system- control unit, registers,
memory, I/O are their mainly to bring data into the ALU for it to process and then to take the
result back out. An ALU & indeed all electronic components in computer are based on the use of
simple digital logic device that can store binary digit and perform simple Boolean logic function.
Figure indicates in general in general term how ALU is interconnected with rest of the processor.

Data are presented to ALU in register and the result of operation is stored in register. These
registers are temporarily storage location within the processor that are connected by signal path
to the ALU. The ALU may also set flags as the result of an operation. The flags values are also
stored in registers within the processor. The control unit provides signals that control the
operation of ALU and the movement of data into an out of ALU.

The design of ALU has three stages.

1. Design the arithmetic section
The basic component of arithmetic circuit is a parallel adder which is constructed with a
number of full adder circuits connected in cascade. By controlling the data inputs to the
parallel adder, it is possible to obtain different types of arithmetic operations. Below
figure shows the arithmetic circuit and its functional table.
Computer Organization and Architecture Chapter 2 : Central Processing Unit

Fig: Block diagram of Arithmetic Unit

Functional table for arithmetic unit:

Select Input Output Microoperation
S1 S0 Y Cin = 0 Cin = 1 Cin = 0 Cin = 1
0 0 0 A A+1 Transfer A Increment A

0 1 B A+B A+B+1 Addition Addition with

carry
1 0 B’ A+B’ A+B’+1 Subtraction with Subtraction
borrow
1 1 -1 A-1 A Decrement A Transfer A

2. Design the logical section

The basic components of logical circuit are AND, OR, XOR and NOT gate circuits
connected accordingly. Below figure shows a circuit that generates four basic logic
micro-operations. It consists of four gates and a multiplexer. Each of four logic
operations is generated through a gate that performs the required logic. The two selection
input S1 and S0 choose one of the data inputs of the multiplexer and directs its value to
the output. Functional table lists the logic operations.
Ai
Bi

4X1
Ei
MUX

S0 S1

Fig: Block diagram of Logic Unit

Computer Organization and Architecture Chapter 2 : Central Processing Unit

Functional table for logic unit:

S1 S0 output Microoperation
0 0 Ai && Bi AND
0 1 Ai || Bi OR
1 0 Ai XOR Bi XOR
1 1 Ai’ NOT

3. Combine these 2 sections to form the ALU

Below figure shows a combined circuit of ALU where n data input from A are combined
with n data input from B to generate the result of an operation at the G output line. ALU
has a number of selection lines used to determine the operation to be performed. The
selection lines are decoded with the ALU so that selection lines can specify distinct
operations. The mode select S2 differentiate between arithmetic and logical operations.
The two functions select S1 and S0 specify the particular arithmetic and logic operations
to be performed. With three selection lines, it is possible to specify arithmetic operation
with S2 at 0 and logical operation with S2 at 1.

Fig: Block diagram of ALU

Computer Organization and Architecture Chapter 2 : Central Processing Unit

Example: Design a 2-bit ALU that can perform addition, AND, OR, & XOR.

Cin

A0
B0 FA
A1
B1
Cout

4X1
Result0
MUX

S1 S0

4X1
Result1
MUX

2.3 Instruction Formats

The computer can be used to perform a specific task, only by specifying the necessary steps to
complete the task. The collection of such ordered steps forms a ‘program’ of a computer. These
ordered steps are the instructions. Computer instructions are stored in central memory locations
and are executed sequentially one at a time. The control reads an instruction from a specific
address in memory and executes it. It then continues by reading the next instruction in sequence
and executes it until the completion of the program.

A computer usually has a variety of Instruction Code Formats. It is the function of the control
unit within the CPU to interpret each instruction code and provide the necessary control
functions needed to process the instruction. An n bit instruction that k bits in the address field
and m bits in the operation code field come addressed 2k location directly and specify 2m
different operation.
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 The bits of the instruction are divided into groups called fields.
 The most common fields in instruction formats are:
o An Operation code field that specifies the operation to be performed.
o An Address field that designates a memory address or a processor
register.
o A Mode field that specifies the way the operand or the effective address is
determined.

n-1 m-1 k-1 0

Fig: Instruction format with mode field
The operation code field (Opcode) of an instruction is a group of bits that define various
processor operations such as add, subtract, complement, shift etcetera. The bits that define the
mode field of an instruction code specify a variety of alternatives for choosing the operands from
the given address. Operation specified by an instruction is executed on some data stored in the
processor register or in the memory location. Operands residing in memory are specified by their
memory address. Operands residing in processor register are specified with a register address.

Types of Instruction
 Computers may have instructions of several different lengths containing varying
number of addresses.
 The number of address fields in the instruction format of a computer depends on
the internal organization of its registers.
 Most computers fall into one of 3 types of CPU organizations:

Single accumulator organization:- All the operations are performed with an

accumulator register. The instruction format in this type of computer uses one address
field. For example: ADD X, where X is the address of the operands .

General register organization:- The instruction format in this type of computer needs
three register address fields. For example: ADD R1,R2,R3

Stack organization:- The instruction in a stack computer consists of an operation code

with no address field. This operation has the effect of popping the 2 top numbers from the
stack, operating the numbers and pushing the sum into the stack. For example: ADD

Computers may have instructions of several different lengths containing varying number of
addresses. Following are the types of instructions.
1. Three address Instruction
With this type of instruction, each instruction specifies two operand location and a result
location. A temporary location T is used to store some intermediate result so as not to
alter any of the operand location. The three address instruction format requires a very
complex design to hold the three address references.
Format: Op X, Y, Z; X  Y Op Z
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Example: ADD X, Y, Z; X  Y + Z
 ADVANTAGE: It results in short programs when evaluating arithmetic
expressions.
 DISADVANTAGE: The instructions requires too many bits to specify 3
addresses.

2. Two address instruction

Two-address instructions are the most common in commercial computers. Here again
each address field can specify either a processor register, or a memory word. One address
must do double duty as both operand and result. The two address instruction format
reduces the space requirement. To avoid altering the value of an operand, a MOV
instruction is used to move one of the values to a result or temporary location T, before
performing the operation.
Format: Op X, Y; X  X Op Y
Example: SUB X, Y; X  X - Y

3. One address Instruction

It was generally used in earlier machine with the implied address been a CPU register
known as accumulator. The accumulator contains one of the operand and is used to store
the result. One-address instruction uses an implied accumulator (Ac) register for all data
manipulation. All operations are done between the AC register and a memory operand.
We use LOAD and STORE instruction for transfer to and from memory and Ac register.
Format: Op X; Ac  Ac Op X
Example: MUL X; Ac  Ac * X

4. Zero address Instruction

It does not use address field for the instruction like ADD, SUB, MUL, DIV etc. The
PUSH and POP instructions, however, need an address field to specify the operand that
communicates with the stack. The name “Zero” address is given because of the absence
of an address field in the computational instruction.
Format: Op; TOS  TOS Op (TOS – 1)
Example: DIV; TOS  TOS DIV (TOS – 1)

Example: To illustrate the influence of the number of address on computer programs, we will
evaluate the arithmetic statement X=(A+B)*(C+D) using Zero, one, two, or three address
instructions.

1. Three-Address Instructions:
ADD R1, A, B; R1  M[A] + M[B]
ADD R2, C, D; R2  M[C] + M[D]
MUL X, R1,R2; M[X]  R1 * R2
It is assumed that the computer has two processor registers R1 and R2. The symbol M[A]
denotes the operand at memory address symbolized by A.
2. Two-Address Instructions:
MOV R1, A; R1  M[A]
ADD R1, B; R1  R1 + M[B]
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MOV R2, C; R2  M[C]

ADD R2, D; R2  R2 + M[D]
MUL R1, R2; R1  R1 * R2
MOV X, R1; M[X]  R1

3. One-Address Instruction:
LOAD A; Ac  M[A]
ADD B; Ac  Ac + M[B]
STORE T; M[T]  Ac
LOAD C; Ac  M[C]
ADD D; Ac  Ac + M[D]
MUL T; Ac  Ac * M[T]
STORE X; M[X]  Ac
Here, T is the temporary memory location required for storing the intermediate result.

4. Zero-Address Instructions:
PUSH A; TOS  A
PUSH B; TOS  B
ADD; TOS  (A + B)
PUSH C; TOS  C
PUSH D; TOS  D
ADD; TOS  (C + D)
MUL; TOS  (C + D) * (A + B)
POP X ; M[X]  TOS

2.4 Addressing Modes

 Specifies a rule for interpreting or modifying the address field of the instruction before
the operand is actually referenced.
 Computers use addressing mode techniques for the purpose of accommodating the
following purposes:-
o To give programming versatility to the user by providing such facilities as
pointers to memory, counters for loop control, indexing of data and various other
purposes.
o To reduce the number of bits in the addressing field of the instructions.
 Other computers use a single binary for operation & Address mode.
 The mode field is used to locate the operand.
 Address field may designate a memory address or a processor register.
 There are 2 modes that need no address field at all (Implied & immediate
modes).

Effective address (EA):

 The effective address is defined to be the memory address obtained from the computation
dictated by the given addressing mode.
 The effective address is the address of the operand in a computational-type instruction.
Computer Organization and Architecture Chapter 2 : Central Processing Unit

The most well known addressing mode are:

 Implied Addressing Mode.
 Immediate Addressing Mode
 Register Addressing Mode
 Register Indirect Addressing Mode
 Auto-increment or Auto-decrement Addressing Mode
 Direct Addressing Mode
 Indirect Addressing Mode
 Displacement Address Addressing Mode
 Relative Addressing Mode
 Index Addressing Mode
 Stack Addressing Mode

Implied Addressing Mode:

 In this mode the operands are specified implicitly in the definition of the instruction.
For example:- CMA - “complement accumulator” is an implied-mode instruction because
the operand in the accumulator register is implied in the definition of the instruction. In
fact, all register reference instructions that use an accumulator are implied-mode
instructions.
Instruction
Opcode
Advantage: no memory reference. Disadvantage: limited operand

Immediate Addressing mode:

 In this mode the operand is specified in the instruction itself. In other words, an
immediate-mode instruction has an operand field rather than an address field.
 This instruction has an operand field rather than an address field. The operand field
contains the actual operand to be used in conjunction with the operation specified in the
instruction.
 These instructions are useful for initializing register to a constant value;
For example MVI B, 50H
Instruction
Opcode Operand
It was mentioned previously that the address field of an instruction may specify either a memory
word or a processor register. When the address field specifies a processor register, the instruction
is said to be in register-mode.
Advantage: no memory reference. Disadvantage: limited operand

Register direct addressing mode:

 In this mode, the operands are in registers that reside within the CPU.
 The particular register is selected from the register field in the instruction.
For example MOV A, B
Computer Organization and Architecture Chapter 2 : Central Processing Unit

Instruction
Opcode Register Register

Operand

Effective Address (EA) = R

Advantage: no memory reference. Disadvantage: limited address space

Register indirect addressing mode:

 In this mode the instruction specifies a register in the CPU whose contents give the
address of the operand in the memory.
 In other words, the selected register contains the address of the operand rather than the
operand itself.
 Before using a register indirect mode instruction, the programmer must ensure that the
memory address of the operand is placed in the processor register with a previous
instruction.
For example LDAX B
Instruction
Opcode Register Register
Memory

Operand

Effective Address (EA) = (R)

Advantage: Large address space.
The address field of the instruction uses fewer bits to select a register than would have been
required to specify a memory address directly.
Disadvantage: Extra memory reference

Auto increment or Auto decrement Addressing Mode:

 This is similar to register indirect mode except that the register is incremented or
decremented after (or before) its value is used to access memory.
 When the address stored in the registers refers to a table of data in memory, it is
necessary to increment or decrement the registers after every access to the table.
 This can be achieved by using the increment or decrement instruction. In some computers
it is automatically accessed.
 The address field of an instruction is used by the control unit in the CPU to obtain the
operands from memory.
 Sometimes the value given in the address field is the address of the operand, but
sometimes it is the address from which the address has to be calculated.
Computer Organization and Architecture Chapter 2 : Central Processing Unit

Direct Addressing Mode

 In this mode the effective address is equal to the address part of the instruction. The
operand resides in memory and its address is given directly by the address field of the
instruction.
For example LDA 4000H
Instruction
Opcode Address Memory

Operand

Effective Address (EA) = A

Advantage: Simple. Disadvantage: limited address field

Indirect Addressing Mode

 In this mode the address field of the instruction gives the address where the effective
address is stored in memory.
 Control unit fetches the instruction from the memory and uses its address part to access
memory again to read the effective address.
Instruction
Opcode Address Memory

Operand

Effective Address (EA) = (A)

Advantage: Flexibility. Disadvantage: Complexity

Displacement Addressing Mode

 A very powerful mode of addressing combines the capabilities of direct addressing and
register indirect addressing.
 The address field of instruction is added to the content of specific register in the CPU.
Instruction
Opcode R A

Register Memory

+ Operand

Effective Address (EA) = A + (R)

Advantage: Flexibility. Disadvantage: Complexity
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Relative Addressing Mode

 In this mode the content of the program counter (PC) is added to the address part of the
instruction in order to obtain the effective address.
 The address part of the instruction is usually a signed number (either a +ve or a –ve
number).
 When the number is added to the content of the program counter, the result produces an
effective address whose position in memory is relative to the address of the next
instruction.
Effective Address (EA) = PC + A

Indexed Addressing Mode

 In this mode the content of an index register (XR) is added to the address part of the
instruction to obtain the effective address.
 The index register is a special CPU register that contains an index value.
 Note: If an index-type instruction does not include an address field in its format, the
instruction is automatically converted to the register indirect mode of operation.
Effective Address (EA) = XR + A

Base Register Addressing Mode

 In this mode the content of a base register (BR) is added to the address part of the
instruction to obtain the effective address.
 This is similar to the indexed addressing mode except that the register is now called a
base register instead of the index register.
 The base register addressing mode is used in computers to facilitate the relocation of
programs in memory i.e. when programs and data are moved from one segment of
memory to another.
Effective Address (EA) = BR + A

Stack Addressing Mode

 The stack is the linear array of locations. It is some times referred to as push down list or
last in First out (LIFO) queue. The stack pointer is maintained in register.
Instruction

Implicit
Top of Stack

Effective Address (EA) = TOS

Computer Organization and Architecture Chapter 2 : Central Processing Unit

Let us try to evaluate the addressing modes with as example.

Fig: Numerical Example for Addressing Modes

Fig: Tabular list of Numerical Example

Computer Organization and Architecture Chapter 2 : Central Processing Unit

2.5 Data Transfer and Manipulation

Data transfer instructions cause transfer of data from one location to another without changing
the binary information. The most common transfer are between the
 Memory and Processor registers
 Processor registers and input output devices
 Processor registers themselves
Typical Data Transfer Instructions

Data manipulation Instructions

Data manipulation instructions perform operations on data and provide the computational
capabilities for the computer. These instructions perform arithmetic, logic and shift
operations.

Arithmetic Instructions
Computer Organization and Architecture Chapter 2 : Central Processing Unit

Logical and Bit Manipulation Instructions

Shift Instructions

Program Control Instructions

The program control instructions provide decision making capabilities and change the
path taken by the program when executed in computer. These instructions specify
conditions for altering the content of the program counter. The change in value of
program counter as a result of execution of program control instruction causes a break in
sequence of instruction execution. Some typical program control instructions are:
Computer Organization and Architecture Chapter 2 : Central Processing Unit

Subroutine call and Return

A subroutine call instruction consists of an operation code together with an address that
specifies the beginning of the subroutine. The instruction is executed by performing two
tasks:
 The address of the next instruction available in the program counter (the return
address) is stored in a temporary location (stack) so the subroutine knows where
to return.
 Control is transferred to the beginning of the subroutine.
The last instruction of every subroutine, commonly called return from subroutine;
transfer the return address from the temporary location into the program counter. This
results in a transfer of program control to the instruction where address was originally
stored in the temporary location.

Interrupt
The interrupt procedure is, in principle, quite similar to a subroutine call except for three
variations:
 The interrupt is usually initiated by an external or internal signal rather than from
execution of an instruction.
 The address of the interrupt service program is determined by the hardware rather
than from the address field of an instruction.
 An interrupt procedure usually stores all the information necessary to define the
state of the CPU rather than storing only the program counter.