Control Unit

Prof. Dr. S.Shakya

 Topics covered

•Control Memoryy
•Addressing sequencing
•Computer configuration
•Microinstruction
Mi i i fformat
•Symbolic microinstructions
•Symbolic microprogram
•Control unit operation
•Design
Design of control unit
Control Unit
 Control Memory
 Control Unit
 Initiate sequences of microoperations

 Control signal (that specify microoperations) in a bus-organized system

 groups of bits that select the paths in multiplexers, decoders, and arithmetic logic units

 Two major types of Control Unit

 Hardwired Control :

 The control logic is implemented with gates, F/Fs, decoders, and other digital circuits

 + Fast operation, - Wiring change(if the design has to be modified)

 Microprogrammed
p g Control :
 The control information is stored in a control memory, and the control memory is
programmed to initiate the required sequence of microoperations
 + Any required change can be done by updating the microprogram in control memory,
- Slow operation
 Control Word
 The control variables at any given time can be represented by a string of 1’s and 0’s.

 Microprogrammed Control Unit

 A control unit whose binary y control variables are stored in memoryy (control
( memory).
y)
 Microinstruction : Control Word in Control Memory
 The microinstruction specifies one or more microoperations
 Microprogram
 A sequence of microinstruction
 Dynamic microprogramming : Control Memory = RAM
 RAM can be used for writing g ((to change
g a writable control
memory))
 Microprogram is loaded initially from an auxiliary memory such
as a magnetic disk
 Static microprogramming : Control Memory = ROM
 Control words in ROM are made permanent during the hardware
production.
 Microprogrammed control Organization :
 1) Control Memory
 A memory is part of a control unit : Microprogram
 Computer
C t Memory
M (employs
( l a microprogrammed
i d control
t l unit)
it)
 Main Memory : for storing user program (Machine
User Program
instruction/data)
 Control Memory : for storing microprogram (Microinstruction) Machine
 2)
) Control Address Register
g Instruction
 Specify the address of the microinstruction
Microprogram
 3) Sequencer (= Next Address Generator)
 Determine the address sequence that is read from control memory Microinstruction
 Next address of the next microinstruction can be specified several
Microoperation
way depending on the sequencer input :
  4)) Control
C lDData R i
Register ((= Pipeline
Pi li R i
Register )
 Hold the microinstruction read from control memory
 Allows the execution of the microoperations specified by the control word
simultaneously with the generation of the next microinstruction
 RISC Architecture Concept
 RISC(Reduced Instruction Set Computer) system use hardwired control rather than
microprogrammed control :
 Address Sequencing
 Address
Add Sequencing
S i = Sequencer
S : Next Address Generator
 Selection of address for control memory
 Routine
 Microinstruction are stored in control memory y in g
groups
p
 Mapping Subroutine : program used by other ROUTINES
 Instruction Code Address in control memory(where routine is located)
 Address Sequencing Capabilities : control memory address
 1) Incrementing of the control address register
 2) Unconditional branch or conditional branch, depending on status bit conditions
 3) Mapping process ( bits of the instruction address for control memory )
 4) A facility for subroutine return
Microprogrammed Control Organization

External Control
Next-address Control Control Control word
input generator address memory data
((sequencer)
q ) g
register ((ROM)) g
register

Next-address information

Control Memory
»A memory is part of a control unit :
»Computer Memory (employs a microprogrammed control unit)

•Main Memory : for storing user program (Machine instruction/data)

•Control Memory : for storing microprogram (Microinstruction)
Control Address Register
»Specify the address of the microinstruction

Sequencer
»Determine the address sequence that is read from control memory
»Next address of the next microinstruction can be specified several way
depending on the sequencer input.

Sequencing Capabilities Required in a Control Storage

1. Incrementing of the control address register
2. Unconditional and conditional branches
3. A mapping process from the bits of the machine instruction to an
address for control memory
4. A facility for subroutine call and return

Control data register

»Hold the microinstruction read from control memory
»Allows the execution of the microoperations specified by the control word
simultaneously y with the ggeneration of the next microinstruction
 Selection of address for control memory :
 Multiplexer
 CAR Increment
 JMP/CALL Instruction code

 Mapping Mapping

 Subroutine Return logic

 CAR : Control Address Register    

Status Branch MUX
 CAR receive
i the
h address
dd from
f bits logic select
M lti l
Multiplexers

Subroutine
4 different paths regiser
(SBR)
1) Incrementer Clock
Control address register
(CAR)
2) Branch address from
control memory Incrementer

3) Mapping Logic
4) SBR : Subroutine Register
 SBR : Subroutine Register Control memory

 Return Address can not be stored

in ROM Select a status
bit
Microoperations

 Return Address for a subroutine is Branch address

stored in SBR
Sequencer (Microprogram Sequencer)
A Microprogram Control Unit that determines
the Microinstruction Address to be executed
in the next clock cycle

- In-line Sequencing
- Branch
- Conditional Branch
- Subroutine
- Loop
- Instruction OP-code mapping
ADDRESS SEQUENCING
Instruction code

Mapping
logic

Status Branch MUX Multiplexers

bits logic select

Subroutine
register
Control address register (SBR)
(CAR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

Sequencing Capabilities Required in a Control Storage

- Incrementing of the control address register
- Unconditional and conditional branches
- A mapping process from the bits of the machine
instruction to an address for control memory
- A facility for subroutine call and return
 CONDITIONAL BRANCHING
Load address
Control address register

Increment

MUX
Control memory

...
Status bits
(condition)

Condition select Micro-operations

Next address

Conditional Branch
If Condition is true, then Branch (address from
the next address field of the current microinstruction)
else Fall Through
Conditions to Test: O(overflow), N(negative),
Z(zero), C(carry), etc.

Unconditional Branch
Fixing the value of one status bit at the input of the multiplexer to 1
 MAPPING OF INSTRUCTIONS
Di t Mapping
Direct M i Address
OP-codes of Instructions 0000 ADD Routine
0001 AND Routine
ADD 0000
. 0010 LDA Routine
AND 0001 . 0011 STA Routine
LDA 0010 . 0100 BUN Routine
STA 0011
BUN 0100 Control
Storage

Mapping
Bits 10 xxxx 010
Address
10 0000 010 ADD Routine
BUN-Branch Unconditionally
10 0001 010 AND Routine

10 0010 010 LDA Routine

10 0011 010 STA Routine

10 0100 010 BUN Routine

MAPPING OF INSTRUCTIONS TO MICROROUTINES
Mapping from the OP-code of an instruction to the
address of the Microinstruction which is the starting
microinstruction of its execution microprogram

Machine OP-code
OP d
Instruction 1 0 1 1 Address

Mapping bits 0 x x x x 0 0
Microinstruction
address 0 1 0 1 1 0 0

Mapping
g function implemented by
y ROM or PLA
OP-code

Mapping memory
(ROM or PLA)

Control address register

Control Memory
 Computer Configuration
Once the configuration
g of a computer
p and its microprogrammed
p g control unit is established , the
Designer’s task is to generate the microcode for control memory.

 2 Memory : Main memory(instruction/data), Control

memory(microprogram)
 Data written to memory come from DR, and Data read
from memory can go only to DR
 4 CPU Register and ALU : DR,
DR ARAR, PC,
PC AC
AC, ALU
 DR can receive information from AC, PC, or Memory
(selected by MUX)
 AR can receive information from PC or DR (selected by
MUX)
 PC can receive information only from AR

 ALU performs microoperation with data from AC and DR

 2 Control Unit Register : SBR, CAR (Subroutine register,

Control address register)
 MICROPROGRAM EXAMPLE
C t C
Computer fi ti
Configuration

MUX
10 0
AR
Address Memory
10 0 2048 x 16
PC

MUX

15 0
6 0 6 0 DR
SBR CAR

Control memory Arithmetic

128 x 20 logic and
shift unit
Control unit
15 0
AC
MACHINE INSTRUCTION FORMAT

Instruction format
15 14 11 10 0
I p
Opcode Address

Sample machine instructions(Four Computer Instructions)

Symbol OP
OP-code
code Description
EA is the effective address
ADD 0000 AC AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC  EA)
STORE 0010 M[EA]  AC
EXCHANGE 0011 AC  M[EA], M[EA]  AC

Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD

F1, F2, F3: Microoperation fields

CD: Condition for branching
BR: Branch field
AD: Address field •The CD field selects status bit conditions.
•The BR field specifies the type of branch to be used.
•The AD field contains a branch address
 MICROINSTRUCTION FIELD DESCRIPTIONS ‐ F1,F2,F3
F1 Microoperation Symbol F2 Microoperation Symbol
000 None NOP 000 None NOP
001 AC  AC + DR ADD 001 AC  AC - DR SUB
010 AC  0 CLRAC 010 AC  AC  DR OR
011 AC  AC + 1 INCAC 011 AC  AC  DR AND
100 AC  DR DRTAC 100 DR  M[AR] READ
101 AR  DR(0-10) DRTAR 101 DR  AC ACTDR
110 AR  PC PCTAR 110 DR  DR + 1 INCDR
111 M[AR]  DR WRITE 111 DR(0 10)  PC
DR(0-10) PCTDR

F3 Microoperation Symbol
000 None NOP
001 AC  AC  DR XOR
010 AC  AC’ COM
011 AC  shl AC SHL
DRTAC-stands
DRTAC stands for a transfer from DR to AC
100 AC  shr AC SHR
101 PC  PC + 1 INCPC
110 PC  AR ARTPC
111 Reserved
MICROINSTRUCTION FIELD DESCRIPTIONS ‐ CD, BR

CD Condition Symbol Comments

00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC

BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
10 RET CAR  SBR (Return from subroutine)
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0
 SYMBOLIC MICROINSTRUCTIONS
• Symbols are used in microinstructions as in assembly language
• A symbolic microprogram can be translated into its binary equivalent
by a microprogram assembler.

Sample Format
five fields: label; micro-ops; CD; BR; AD

Label: may be empty or may specify a symbolic

address terminated with a colon

Micro-ops: consists of one, two, or three symbols

separated by commas

CD: one of {U, I, S, Z}, where U: Unconditional Branch

I: Indirect address bit
S Si
S: Sign off AC
Z: Zero value in AC

BR: one of {JMP, CALL, RET, MAP}

AD: one of {Symbolic address, NEXT, empty}

SYMBOLIC MICROPROGRAM ‐ FETCH ROUTINE

During FETCH, Read an instruction from memory

and decode the instruction and update PC

Sequence of microoperations in the fetch cycle:

AR  PC
DR  M[AR], PC  PC + 1
AR  DR(0-10),
( ( )  DR(11-14),
), CAR(2-5) ( ( , , )0
), CAR(0,1,6)

Symbolic microprogram for the fetch cycle:

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP

Binary equivalents translated by an assembler

Binary
address F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000
 SYMBOLIC MICROPROGRAM
Storage 128 20-bit
• Control Storage: 20 bit words
ords
• The first 64 words: Routines for the 16 machine instructions
• The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)
• Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are
( 0000 00),
0(0 ) 4(0
( 0001 00),
) 8, 12, 16, 20, ..., 60

Partial Symbolic Microprogram

Label Microops CD BR AD
ORG 0
ADD: NOP I CALL INDRCT
READ U JMP NEXT
ADD U JMP FETCH

ORG 4
BRANCH: NOP S JMP OVER
NOP U JMP FETCH
OVER: NOP I CALL INDRCT
ARTPC U JMP FETCH

ORG 8
STORE: NOP I CALL INDRCT
ACTDR U JMP NEXT
WRITE U JMP FETCH

ORG 12
EXCHANGE: NOP I CALL INDRCT
READ U JMP NEXT
ACTDR, DRTAC U JMP NEXT
WRITE U JMP FETCH

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
INDRCT: READ U JMP NEXT
DRTAR U RET
 BINARY MICROPROGRAM
Address Binary Microinstruction
Micro Routine Decimal Binary F1 F2 F3 CD BR AD
ADD 0 0000000 000 000 000 01 01 1000011
1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00 1000000
3 0000011 000 000 000 00 00 1000000
BRANCH 4 0000100 000 000 000 10 00 0000110
5 0000101 000 000 000 00 00 1000000
6 0000110 000 000 000 01 01 1000011
7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011
9 0001001 000 101 000 00 00 0001010
10 0001010 111 000 000 00 00 1000000
11 0001011 000 000 000 00 00 1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011
13 0001101 001 000 000 00 00 0001110
14 0001110 100 101 000 00 00 0001111
15 0001111 111 000 000 00 00 1000000

FETCH 64 1000000 110 000 000 00 00 1000001

65 1000001 000 100 101 00 00 1000010
66 1000010 101 000 000 00 11 0000000
INDRCT 67 1000011 000 100 000 00 00 1000100
68 1000100 101 000 000 00 10 0000000

This microprogram can be implemented using ROM

DESIGN OF CONTROL UNIT
‐ DECODING ALU CONTROL INFORMATION ‐

microoperation fields
F1 F2 F3

3 x 8 decoder 3 x 8 decoder 3 x 8 decoder

7 6 54 3 21 0 7 6 54 3 21 0 76 54 3 21 0

AND
ADD AC
Arithmetic
logic and DR
DRTAC shift unit
PCTAR

DRTAR

From From
PC DR(0-10) Load
AC

Select 0 1
Multiplexers

Load Clock
AR
 Implementation of Control Unit

COMPARISON OF CONTROL UNIT IMPLEMENTATIONS

Control Unit Implementation
Combinational Logic Circuits (Hard-wired)
Control Data
Memory IR Status F/Fs

Control Unit's State

Timing State
Combinational Control CPU
Logic Circuits Points
Ins. Cycle State

Microprogram

M Control Data
e
m
o IR Status F/Fs
r
y

C Control C
Next Address Storage C
S S D P CPU
Generation A (-program D
Logic s
R memory) R }
 MICROPROGRAM SEQUENCER
‐ NEXT MICROINSTRUCTION ADDRESS LOGIC ‐
Branch CALL Address
Branch,
External RETURN form Subroutine
(MAP)
In-Line
S1S0 Address Source
00 CAR + 1,, In-Line 3 2 1 0
S1 MUX1 L
01 SBR RETURN SBR Subroutine
S0 CALL
10 CS(AD), Branch or CALL Address
11 MAP source
selection
Incrementer

Clock CAR

Control Storage

MUX-1 selects an address from one of four sources and routes it into a CAR

- In-Line Sequencing  CAR + 1

- Branch, Subroutine Call  CS(AD)
- Return from Subroutine  Output of SBR
- New Machine instruction  MAP
MICROPROGRAM SEQUENCER
‐ CONDITION AND BRANCH CONTROL ‐

1 L L(load SBR with PC)

From I MUX2 Test
CPU S T for
f subroutine
b ti Call
C ll
BR field Input
Z Select I0 logic S0 for next address
of CS I
S1 selection
1

CD Field of CS

Input Logic
I0I1T Meaning
g Source of Address S1S0 L

000 In-Line CAR+1 00 0

001 JMP CS(AD) 10 0
010 In-Line CAR+1 00 0
011 CALL CS(AD) and SBR <- CAR+1 10 1
10x RET SBR 01 0
11x MAP DR(11-14) 11 0

S0 = I0
S1 = I0I1 + I0’T
T
L = I0’I1T
Microprogram sequencer for a control memory
External
(MAP)

L
I0 3 2 1 0
Input Load
L d
I1
Logic S1 MUX1 SBR
T S0

1 Incrementer
I MUX2 Test
S
Z Select
Clock CAR

Control memory

Microops CD BR AD
... ...
 MICROINSTRUCTION FORMAT
Information in a Microinstruction
- Control Information
- Sequencing Information
- Constant
Information which is useful when feeding into the system

These information needs to be organized in some way for

- Efficient use of the microinstruction bits
- Fast decoding

Field Encoding
g

- Encoding the microinstruction bits

- Encoding slows down the execution speed
g delay
due to the decoding y
- Encoding also reduces the flexibility due to
the decoding hardware