19E014- VLSI

DESIGN
GENERAL ARRANGEMENT
OF
4 –BIT ARITHMETIC
PROCESSOR ,DESIGN OF BY
A 4 BIT SHIFTERA P Rishwan (22E101)
Aadav Pon Shankar S (22E102)
Abinaya AP (22E103)
Akalya P (22E104)
Aniruthan B (22E106)
Archana A (22E107)
Subsystem Design
Processor
BY
A P Rishwan(22E101)
Objective of designing
• Lower unit cost
• Higher reliability
• Lower power dissipation , lower weight and lower volume
• Better performance
• Enhanced repeatability
• Possibility of reduced design/development periods
Some problems
• How to design large complex systems in a reasonable time and with
reasonable effort.
• The nature of architectures best suited to take full advantage of VLSI
and the technology.
• The testability of large/complex systems once implemented on silicon.
Solutions
• Problem 1 and 3 are greatly reduced if two aspects of standard
practices are accepted:
• 1.a) Top-down design approach with adequate CAD tools to do the
job
b) Partitioning the system sensibly
c) Aiming for simple interconnections
d) High regularity within subsystem
e) Generate and then verify each section of the design.
2.Devote significant portion of total chip area to test and diagnostic
facility
3. Select architectures that allow design objectives and high
regularity in realization
An Illustration of Design
Process
• Structured design begins with the concept of hierarchy
• It is possible to divide any complex function into less complex subfunctions that is up to leaf
cells
• Process is known as top-down design
• As a systems complexity increases, its organization changes as different factors become
relevant to its creation
• Coupling can be used as a measure of how much submodels interact
• It is crucial that components interacting with high frequency be physically proximate, since
one may pay severe penalties for long, high-bandwidth interconnects
• Concurrency should be exploited it is desirable that all gates on the chip do useful work most
of the time
• Because technology changes so fast, the adaptation to a new process must occur
in a short time.
Approaches used at Different
Stages
• Conventional circuit symbols
• Logic symbols
• Stick diagram
• Any mixture of logic symbols and stick diagram that is convenient at a
stage
• Mask layouts
• Architectural block diagrams and floor plans
Floor plan for 4-bit data path

• The above picture shows tentative floor plan of 4-bit data path in arithmetic
processor.
• This indicates a possible relative disposition of the blocks and also indicates
acceptable and sensible interconnection strategy indicated by the lines showing
the preferred direction of data flow and control signal distribution.
4 – bit Arithmetic
Processor
Akalya P
22E104
4 – bit Arithmetic Processor
• ALU is a major component of central processing unit of the computer
system. It does all processes related to arithmetic and logic operations that
need to be done on instruction words.
• Different operations as carried out by ALU can be categorized as follows-
• Logical operation- these include operations like AND, OR, NOT, XOR, NOR,
NAND, etc.
• Bit shifting operations – this pertains to shifting the positions of the bits by
a certain number of places either towards the right or left.
• Arithmetic operations - This refers to bit addition and subtraction although
multiplication and divisions are sometimes used operations are more
expensive to make multiplication and Division can also be done by
repetitive additions and subtraction respectively.
Basic digital processor
• Structure comprises a unit which processes data applied at one port
and presents its output at a second port.
• alternatively., two data ports may be combined as a single
bidirectional of port if storage facility exist in a date path . control
over the functions to be performed is effected by control signals as
indicated.
• At this early stage it is essential to evolve the interconnection
strategy to which we will then adhere.
• Now we will decompose the date path into the block diagram
showing the main subunits.
In doing this it is useful to anticipate a possible floor plan to show the
planned relative disposition of the subunits on the chip and thus on the
mask layouts.
• A further decision must then be made about the nature of the bus
architecture linking the subunits. The choices in this case range from
one bus two bus or 3 bus architecture. Some of the possibilities are
shown here
One bus architecture
Sequence:
1. First operand from registers to ALU. Operand is stored there.
2. Second operand from registers to ALU. Operands are added,. And
the result is say stored in the ALU.
3. The result is passed through shifter and stored in the registers.
4. Suitable for early or basic microprocessors where simplicity and
cost-saving are prioritized over performance.
Two bus architecture
Sequence :
1. Two operands are sent from registers to ALU and are operated upon
and the result is stored in ALU.
2. Result is passed through the shifter and stored in the registers.
3. Used in small embedded systems, simple microcontrollers, or low-
power devices to improve speed without adding much complexity.
Three bus architecture
Sequence:
1. The two operand are sent from the registers operated upon and
the shifted result returned to another register all in the same clock
period.
2. Often used in more advanced 4-bit processors and early computer
systems to handle multiple instructions or operations
simultaneously.
Care Taken In Allocating the
layers to various data or
control paths
BY
AADAV PON SHANKAR S
22E102
 Metal can cross polysilicon or diffusion without any significant
effect (with some reservation to be discussed later)

 Wherever polysilicon crosses diffusion a transistor will be

formed. This includes the second polysilicon layer for processes
that have two

 Wherever lines touch on the same level an interconnection is

formed

 Simple contacts can be used to join diffusion or polysilicon to

metal
 To join diffusion and polysilicon we must use either a buried
contact or a butting contact (in which case all three layers are
joined together
at the contact) or two contacts, diffusion to metal then metal to
polysilicon

 In some processes, a second metal layer is available. This can cross

over any other layers and is conveniently employed for power rails

 First and second metal layers may be joined using a via

 Each layer has particular electrical properties which must be
taken into account

 For CMOS layouts, p- and n- diffusion wires must not directly

join each other, nor may they cross either a p-well or an n-well
boundary
 Signal Integrity
Crosstalk Reduction: Data and control signals on adjacent layers
can interfere with each other, leading to signal distortion
(crosstalk). To mitigate this, adjacent routing layers are often
separated by ground or power planes that provide shielding

 Performance Optimization
Critical Path Routing: Performance-critical paths, such as high-
speed data signals or clock lines, are usually allocated to higher
metal layers, which have lower resistance and capacitance. This
ensures faster signal propagation and minimizes signal delays
 Thermal and Power Management
Power Distribution: Layers dedicated to power delivery are critical
in preventing voltage drops and ensuring that sufficient power is
delivered to all components. These layers are generally thicker and
capable of carrying more current to reduce resistive losses

Heat Dissipation: Since high-speed data and power lines can

generate heat, layers are allocated considering the need to spread
or dissipate heat, preventing hot spots in the design that could
degrade performance
 Multi-layer Complexity
Wire-Length Considerations: Minimizing the wire length by
allocating layers intelligently can reduce resistance and capacitance,
leading to lower power consumption and faster signal transmission

 Timing Management
Timing Closure: To meet the timing constraints, data and
control paths may be placed on different layers with
appropriate buffering and routing strategies. Delay and
timing are optimized by routing critical paths through
higher-performance layers.
4x4 crossbar switch

-ABINAYA AP(22E103)
THE DESIGN OF A 4-BIT SHIFTER:

 Any general purpose n-bit shifter should be able to shift incoming data by up to n-1
places in a right-shift or left-shift direction.

 The shifter must have:

- Input from a four line parallel data bus.
- Four output lines for the shifted data.
- Means of transferring input data to output lines with any shift from 0 to 3 bits.
CROSSBAR SWITCH MODEL:

 Crossbar switch(also know as cross point or matrix switch)is a switch connecting multiple
inputs to multiple outputs in a matrix manner.
 The point of intersection of horizontally and vertical lines is known as crosspoint.
 A crossbar switching system is also know as coordinate switching system.
4X4 CROSSBAR SWITCH USING MOS:

 In a 4x4 crossbar switch , there are four input lines and four output lines.
 Each input can be connected to any output , providing a high degree of flexibility in data
routing.
 A 4x4 crossbar switch can be implemented using a matrix of MOSFETs.
 Each intersection point in a matrix represents a switch that can be turned on or off.
ADVANTAGES:

 Flexibility
 Scalability
 Simplicity
 Controllability
 Low power consumption.
 Compactness
DISADVANTAGES:

 Complexity
 Crosstalk
 Delay
 Manufacturing Cost
 Limited scalability
APPLICATIONS:

 Telecommunications
 Computer systems
 Signal processing
 Industrial control
 Custom logic
 Biomedical engineering
4x4 BARREL SHIFTER

BY:
ARCHANA A
22E107
WHAT IS BARREL SHIFTER?

● A barrel shifter is a digital circuit that can shift a data word by a specified number of bits without the
use of any sequential logic,only pure combinational logic.

● A barrel shifter is often used to shift and rotate n-bits in modern microprocessors ,typically within a
single clock cycle.
Basic Operation of a 4x4 Barrel Shifter:

A 4x4 barrel shifter is designed to take a 4-bit input and shift it either left or right by 0 to 3 positions in a
single operation. The output will also be a 4-bit value.

Functionality:

The main functions of a 4x4 barrel shifter are:

● Left Shift (LS): Moves bits to the left, filling the rightmost bits with zeros or ones.
● Right Shift (RS): Moves bits to the right, with options for zero-fill or sign-fill.
● Control Signals: The shifter accepts control signals that specify the shift direction (left or right) and the
number of bit positions (0 to 3).
Design of 4x4 Barrel Shifter:

● The circuit is designed using a pass transistor.

● It is placed in a matrix format.
● The input to the shifter is the value to be shifted in [3:0] and shift
amount sh[3:0].
● Function depends on the connections of bus and output is in
out[3:0].
● The interbus switches have their gates inputs connected in a
staircase fashion in groups of four and there are 4 control inputs.
● CMOS transmission gates may be used in place simple pass
transistor switches.
Working of 4x4 Barrel Shifter:

● By doing zero bit shift right

● By doing one bit shift right
● By doing two bit shift right
● By doing three bit shift right
4x4 Barrel Shifter:

● All 16 transistors are connected in

a single diagram is represented.

● This circuit is capable of performing

0 to 3 bit shift operation with only 4

Control signals.
Regularity:

● Regularity should be high as possible to minimize the design effort required for any system.
Advantages: Disadvantages:

● ● Increased Complexity with Larger

Single-Cycle Operation
Shifts
● Flexible Shifting ● Signal Integrity
● Efficient Area Utilization ● Limited Functionality
● Reduced Complexity ● Potential for Increased Delay
● Low Power Consumption ● Design Complexity for Control
Signals
Applications:

● Arithmetic Operations
● Data Manipulation
● Digital Signal Processing
● Microprocessor Design
● Graphics Processing
● Cryptography
STICK DIAGRAM AND BOUNDING
BOX FOR 4x4 BARREL SHIFT
REGISTER

BY
ANIRUTHAN B
22E106
STICK DIAGRAM

• The stick diagram clearly Conveys regular topology and allows the choice of a
standard cell from which complete barrel shifters of any size may be formed by
replication of the standard cell.
• It should be noted that standard cell boundaries must be carefully chosen to
allow for butting together side by side and top to bottom to retain the overall
topology.
• Once the standard cell dimensions have been determined, then any n x n barrel
shifter may be configured and its outline, or bounding box, arrived at by summing
up the dimensions of the replicated standard cell.
BOUNDING BOX
• In VLSI (Very Large Scale Integration) design, a bounding box refers
to the smallest rectangular area that completely encloses a particular
layout or group of components (such as transistors, logic gates, or
cells).
• It is often used to define the physical boundaries of a design, which
helps in placement, routing, and optimization of the chip design
during the layout process.
• A minimum bounding box for a 4x4 barrel shifter is the smallest
rectangular region that fully contains all the components (such as
multiplexers, transmission gates, and interconnects) required for the
barrel shifter circuit.
• This box defines the minimum area needed to implement the design,
ensuring that no part of the layout extends beyond its edges.
• The dimensions of the bounding box are determined by the
outermost horizontal and vertical positions of the circuit elements,
and it is used to optimize the design for area and layout efficiency in
VLSI.
OBSERVATIONS

Approach to the design of a system and of a particular subsystem steps

involved may be set out as follows:
1. Set out a specification together with an architectural block diagram.
2. Suitably partition the architecture into subsystems which are, as far
as possible, self-contained and which give as simple interconnection
requirements as possible.
3. Set out a tentative floor plan showing the proposed physical
disposition of subsystems on the chip.
4. Determine interconnection strategy.
5. Revise 2, 3 and 4 interactively as necessary.
6. Choose layers on which to run buses and the main control signals.
7. Take each subsystem in turn and conceive a regular architecture to conform to
the strategy set out in 4. Set out circuit and/or logic diagrams as appropriate.
Remember that MOS switch-based logic is such that both the logic 1 and logic
0 conditions of an output must be deliberately satisfied (not as in TTL logic,
where if logic 1 conditions are satisfied then logic 0 conditions follow
automatically).
8. Develop stick diagrams adopting suitable tactics to observe the overall strategy
(4) and choice of layers (6). Determine suitable standard cell(s) from which VLSI
Design the subsystem may be formed
9. Produce mask layouts for the standard cell(s), making sure that cells can be
butted together, side by side and top to bottom, without design rule violation
or waste of space. Determine overall dimension of the standard cell(s).
10. Cascade and replicate standard cells as necessary to complete the desired
subsystem .This may now be characterized in bounding box form with positions
and layers of inlets and outlets.
THANK YOU