Field programmable gate arrays (FPGAs) contain programmable logic blocks (CLBs), input/output blocks (IOBs), and a programmable interconnect structure. IOBs interface between external pins and internal logic and contain D flip-flops and signal paths. The FPGA interconnect structure includes programmable switch matrices and programmable interconnect points (PIPs) that allow connections between CLBs, IOBs, and routing resources like wire segments and channels. Programming technologies for the interconnect switches include SRAM, antifuse, and floating gate which provide different levels of reprogrammability and resistance characteristics.
Field programmable gate arrays (FPGAs) contain programmable logic blocks (CLBs), input/output blocks (IOBs), and a programmable interconnect structure. IOBs interface between external pins and internal logic and contain D flip-flops and signal paths. The FPGA interconnect structure includes programmable switch matrices and programmable interconnect points (PIPs) that allow connections between CLBs, IOBs, and routing resources like wire segments and channels. Programming technologies for the interconnect switches include SRAM, antifuse, and floating gate which provide different levels of reprogrammability and resistance characteristics.
Field programmable gate arrays (FPGAs) contain programmable logic blocks (CLBs), input/output blocks (IOBs), and a programmable interconnect structure. IOBs interface between external pins and internal logic and contain D flip-flops and signal paths. The FPGA interconnect structure includes programmable switch matrices and programmable interconnect points (PIPs) that allow connections between CLBs, IOBs, and routing resources like wire segments and channels. Programming technologies for the interconnect switches include SRAM, antifuse, and floating gate which provide different levels of reprogrammability and resistance characteristics.
Field programmable gate arrays (FPGAs) contain programmable logic blocks (CLBs), input/output blocks (IOBs), and a programmable interconnect structure. IOBs interface between external pins and internal logic and contain D flip-flops and signal paths. The FPGA interconnect structure includes programmable switch matrices and programmable interconnect points (PIPs) that allow connections between CLBs, IOBs, and routing resources like wire segments and channels. Programming technologies for the interconnect switches include SRAM, antifuse, and floating gate which provide different levels of reprogrammability and resistance characteristics.
Field programmable gate array 2-D arrays cells separated by wiring channels Basic structure: CLB - logic function generators IOB interface between IO pins & internal logic PI connect CLB & IOB 1 Programmable interconnections
IO BLOCKS
Interface between external package pins & internal logic Configured as an input, output, or bidirectional port. D flip-flops are included to provided registered inputs and outputs. Direct and Registered inputs can be selected by Mux Three main signal paths within the IOB: input path Output path 3-state path Input path: Delay element can be set to ensure a hold time of zero Output path: Tri-state driver is present
IO BLOCKS
IO BLOCKS
Output driver is active low enabled. D Flip Flop can be edge or level triggered Selectable polarity of signals from CLB using invertors CE is common to all FF CLK is separate for input and output Slew rate controlled to avoid noise Pull up and pull down used to connect unused IO to VCC or GRND
XILINX FPGA-INTERCONNECT
Routing resources: wires & switches (antifuse or pass transistors) Wire Segments: Wire unbroken by programmable switches Track: A sequence of one or more wire segments in a line. Routing Channels: group of parallel tracks (Horizontal channel or vertical channel) Switch box wires
Logic cell wires
Logic cell
Wire segment
Horizontal channel
Logic cell
Logic cell
Logic cell 5
Vertical channel
GENERAL FPGA ROUTING ARCHITECTURE
1.
2.
The model contains two basic structures: Connection block : connects the inputs and outputs of a logic block to the wire segments in the channels. Switch block: provides connectivity between the horizontal as well as vertical wire segments. In some architectures, the switch block and connection block are intermingled, and in others they are combined into a single structure.
General FPGA Routing Architecture
INTERCONNECT - WIRES 1. 2.
3.
4. 5.
Five types of wire segments: Global Clk: Clock inputs to CLBs Direct connect : between two adjacent CLBs Single groups: flexible connectivity between adjacent CLBs which pass through switch matrix Double groups: travel past 2 CLBs Long groups: span entire chips length or width
INTERCONNECT - WIRES
ROUTING RESOURCE WIRE SEGMENTS
10
CLB
11 12
PROGRAMMABLE INTERCONNECTS CLB 1 CLB 2 CLB 3
CLB1
CLB3
CLB 4
CLB 5
CLB 6
CLB9
CLB 7
CLB 8
CLB 9
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PROGRAMMABLE SWITCH MATRIX
Long wires
Horizontal channel
Double length wires Single length wires
Programmable Switch Matrix (PSM) is used to interconnect CLBs & IOBs
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ROUTING RESOURCE - PROGRAMMABLE SWITCH ELEMENT
PSE
PSM
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ROUTING RESOURCE - PROGRAMMABLE SWITCH ELEMENT
Programmable switch Element (PSE) connect to other lines For 4 lines, 6 possible pairwise connections can be formed 6 gates in each PSE
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ROUTING RESOURCE - PIP
PIP are programmable pass transistors that connects CLB inputs outputs to routing network
Static RAM cells to control pass gates or multiplexers
Pass transistor For SRAM = 1, switch is closed For 0, switch is open
MUX controls which one of the multiplexer inputs are connected to the output 18
SRAM Programming Technology
Advantage: Fast reprogrammability Standard integrated circuit process technology Disadvantage: Large Area External Permanent memory required during power up
19
ANTIFUSE Programming Technology
At the intersection of routing traces, a special contact is placed called an antifuse Unprogrammed state very high resistance between terminals Programmed state low resistance 11- 20 V and 5mA current is used for anitfuse programming
Horizontal wire 20
Vertical wire
ANTIFUSE
3 sandwiched layers: conductors at top and bottom and an insulator in the middle. Antifuses consist of either of the following: ONO dielectric between N+ diffusion and poly-silicon Amorphous silicon between metal layers Amorphous silicon between polysilicon and the first layer of metal
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ANTIFUSE Programming Technology
Advantage: Small Size Relatively low series resistance and parasitic resistance ONO 300 to 500 ohm Amorphous si 50 to 100 ohm
Disadvantage: One time Programmable External Pass transistor required during programming
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Floating Gate Programming Technology
UV erasable EPROM and EEPROM devices used Transistor Permanently disabled by injecting charge on floating gate
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Floating Gate Programming Technology
Advantage: Re-programmability No external permanent memory Disadvantage: High ON resistance High Static power consumption due to pull up resistor
