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D. Text Based: The Time Period For The Clock #10 Clock Clock

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Netlist is a text-based representation of a circuit. Verilog HDL originated at Defense Advanced Research Projects Agency (DARPA). For programming sequential circuits like flip flops, the always statement is used. RTL stands for register-transfer logic. The @posedge operator can be understood as a transition from 0 to 1. For triggering an event, the => operator is used.

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D. Text Based: The Time Period For The Clock #10 Clock Clock

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balu
770 views5 pages
Netlist is a text-based representation of a circuit. Verilog HDL originated at Defense Advanced Research Projects Agency (DARPA). For programming sequential circuits like flip flops, the always statement is used. RTL stands for register-transfer logic. The @posedge operator can be understood as a transition from 0 to 1. For triggering an event, the => operator is used.

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Verilog questions

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Netlist is a text-based representation of a circuit. Verilog HDL originated at Defense Advanced Research Projects Agency (DARPA). For programming sequential circuits like flip flops, the always statement is used. RTL stands for register-transfer logic. The @posedge operator can be understood as a transition from 0 to 1. For triggering an event, the => operator is used.

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770 views5 pages

D. Text Based: The Time Period For The Clock #10 Clock Clock

Uploaded by

balu
Netlist is a text-based representation of a circuit. Verilog HDL originated at Defense Advanced Research Projects Agency (DARPA). For programming sequential circuits like flip flops, the always statement is used. RTL stands for register-transfer logic. The @posedge operator can be understood as a transition from 0 to 1. For triggering an event, the => operator is used.

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1. Netlist is a known as ______ representation of a circuit.

a. graphic

b. handwritten

d. pictorial

d. text‐based

2. Verilog HDL had been at originated at

a. Defense Advanced Research Projects Agency

b. Institute of Electrical and Electronics Engineers(IEEE)

c. Gateway Design Automation

d. AT&T Bell laboratories (DARPA)

3. For programming sequential circuits like flip flops, which type of statement is used

a. Entity

b. Always

c. Initial

d. Component

4. RTL is called as ________

a. register‐transistor logic .

b. resistor‐transfer logic

c. register‐transfer logic

d. none of these

5. The time period for the clock

#10 clock = ~clock

a.5

b. 10

c.20
d.15

6. @posedge can be understood as


a. Transition from z to 1,x
b. Transition from 0 to 1
c, ransition from 0 to 1,x or z
d. ransition from x to 1,x or z

7.  What is execution order for code given below

module zero;
reg a,b,c;
//initial block with zero delay
initial begin
#0 a = 1;
#0 b = 1;
#0 c = 1;
(" Zero delay control a= %b, b= %b, c=%b
",a,b,c);
end

//initial block without zero delay


initial c = 0;

initial begin
a = 0;
b = 0;
("Non-zero delay control a= %b, b= %b, c=%b ",a,b,c);
end

endmodule

a. Zero delay is executed only after all other statements are executed in that simulation
time and order of zero
b. Zero delay control statement is executed last
c. Both
d. None
8. For triggerring an event, ----------------------- operator is used.
a. --->
b. =>
c. @
d. ==

9. left hand side of a In continuous assignment must be


a. Scalar or Vector reg
b. Scalar or Vector net
c. Reg
d. net
10. Default value for data type “reg”
a. X
b. 1
c. 0
d.z
11. For a non blocking assignment
a. Evaluates all RHS for current time unit and assign to LHS at the end of time unit
b. Evaluates all RHS for current time unit and assign to LHS at current time
c. both
d. none
12. Clock skew is present in
a. asynchronous
b. synchronous
c. both
d. none
13. The Verilog can be used for transistor-level descriptions but the VHDL cannot provide this
description.

a. yes
b. no
c. may be
d. none
14. ______ is a superset of Verilog

a. system C

b. VHDL

c. Helio

d. System verilog

15. Many companies are switching from ASICs to FPGAs for their CPU architectures.
Why?
a. The development cycle for FPGA is much shorter.
b. FPGAs are both smaller and faster.
c. FPGAs are more space‐efficient
d. FPGAs always outperform an ASIC  
16. EDA stands for ____________________ .
a. Electricity Distributors Association
b. Electronic Design Automation
c. Electronic Design Agency
d.none
17. Most FPGA logic modules utilize which approach to create the desired logic functions.
a. c. OR array
b. AND array
c. Look‐up table
d. AND and OR array

18. What is the design flow of VLSI system?

i. architecture design

ii. market requirement


iii. logic design

iv. HDL coding

a. iii-ii-i-iv
b. iv-i-iii-ii
c. ii-i-iii-iv
d.i-ii-iii-iv

19. Arrange the blocks of the netlist on the chip.


A, Floor planning

b. placement

c. system partitioning’

d. routing

20. Decide the locations of cells in a block.


A, Floor planning

b. placement

c. system partitioning’

d. routing

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