100343
Low Power 8-Bit Latch
General Description
Features
The 100343 contains eight D-type latches, individual inputs,
(Dn), outputs (Qn), a common enable pin (E), and a latch enable pin (LE). A Q output follows its D input when both E and
LE are LOW. When either E or LE (or both) are HIGH, a latch
stores the last valid data present on its D input prior to E or
LE going HIGH.
The 100343 outputs are designed to drive a 50 termination
resistor to 2.0V. All inputs have 50 k pull-down resistors.
n
n
n
n
Low power operation
2000V ESD protection
Voltage compensated operating range = 4.2V to 5.7V
Available to MIL-STD-883
Logic Symbol
DS100298-1
Pin Names
Description
D0D7
Data Inputs
Enable Input
LE
Latch Enable Input
Q0Q7
Data Inputs
NC
No Connect
1998 National Semiconductor Corporation
DS100298
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100343 Low Power 8-Bit Latch
August 1998
Connection Diagrams
24-Pin DIP
24-Pin Quad Cerpak
DS100298-3
DS100298-2
Logic Diagram
DS100298-5
Truth Table
Inputs
Outputs
Dn
LE
Latched (Note 1)
Latched (Note 1)
Qn
H = HIGH voltage level
L = LOW voltage level
X = Dont care
Note 1: Retains data present before either LE or E went HIGH
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Absolute Maximum Ratings (Note 2)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature (TSTG)
Maximum Junction Temperature (TJ)
Ceramic
VEE Pin Potential to Ground Pin
Input Voltage (DC)
Output Current (DC Output HIGH)
ESD (Note 3)
Case Temperature (TC)
Military
Supply Voltage (VEE)
65C to +150C
+175C
7.0V to +0.5V
VEE to +0.5V
50 mA
2000V
55C to +125C
5.7V to 4.2V
Note 2: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
VEE = 4.2V to 5.7V, VCC = VCCA = GND, TC = 55C to +125C
Symbol
VOH
Parameter
Output HIGH Voltage
Min
Max
Units
TC
1025
870
mV
0C to
1085
870
mV
55C
1830 1620
mV
0C to
1830 1555
mV
55C
1035
mV
0C to
+125C
VOL
Output LOW Voltage
Conditions
Notes
VIN = VIH (Max)
or VIL (Min)
Loading with
50 to 2.0V
1, 2, 3
VIN = VIH (Max)
or VIL (Min)
Loading with
50 to 2.0V
1, 2, 3
+125C
VOHC
Output HIGH Voltage
+125C
1085
VOLC
Output LOW Voltage
mV
55C
1610
mV
0C to
1555
mV
55C
870
mV
55C to
+125C
VIH
Input HIGH Voltage
1165
Guaranteed HIGH Signal for All Inputs
1, 2, 3, 4
Guaranteed LOW Signal for All Inputs
1, 2, 3, 4
VEE = 4.2V
VIN = VIL (Min)
VEE = 5.7V
VIN = VIH (Max)
1, 2, 3
+125C
VIL
Input LOW Voltage
1830 1475
mV
55C to
+125C
IIL
Input LOW Current
0.50
55C to
+125C
IIH
Input HIGH Current
240
0C to
+125C
340
IEE
Power Supply Current
55C
55C to
100
35
105
35
mA
1, 2, 3
+125C
Inputs Open
VEE = 4.2V to 4.8V
VEE = 4.2V to 5.7V
1, 2, 3
Note 4: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals 55C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides cold start specs which can be considered a worst case
condition at cold temperatures.
Note 5: Screen tested 100% on each device at 55C, +25C, and +125C, Subgroups 1, 2, 3, 7, and 8.
Note 6: Sample tested (Method 5005, Table I) on each manufactured lot at 55C, +25C, and +125C, Subgroups A1, 2, 3, 7, and 8.
Note 7: Guaranteed by applying specified input condition and testing VOH/VOL.
Military Version
AC Electrical Characteristics
VEE = 4.2V to 5.7V, VCC = VCCA = GND
Symbol
Parameter
tPLH
Propagation Delay
tPHL
Dn to Output
TC = 55C
TC = +25C
TC = +125C
Min
Max
Min
Max
Min
Max
0.50
2.70
0.50
2.30
0.50
2.80
Units
ns
Conditions
Figures 1, 2, 3
Notes
(Notes 8, 9,
10, 12)
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Military Version
AC Electrical Characteristics
(Continued)
VEE = 4.2V to 5.7V, VCC = VCCA = GND
Symbol
Parameter
tPLH
Propagation Delay
tPHL
LE, E to Output
tTLH
Transition Time
tTHL
20% to 80%, 80% to 20%
ts
Setup Time
th
Hold Time
tpw(H)
Pulse Width HIGH
TC = 55C
TC = +25C
TC = +125C
Min
Max
Min
Max
Min
Max
0.90
3.40
1.0
3.10
1.10
3.90
ns
0.40
2.50
0.40
2.40
0.40
2.70
ns
Figures 1, 3
(Note 11)
Units
Conditions
Figures 1, 2, 3
Notes
(Notes 8, 9,
10, 12)
D0D7
0.60
0.60
0.60
ns
Figures 1, 4
(Note 11)
D0D7
1.50
1.50
1.70
ns
Figures 1, 4
(Note 11)
LE, E
2.40
2.40
2.40
ns
Figures 1, 4
(Note 11)
Note 8: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals 55C), then testing immediately
after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures.
Note 9: Screen tested 100% on each device at +25C temperature only, Subgroup A9.
Note 10: Sample tested (Method 5005, Table I) on each manufactured lot at +25C, Subgroup A9, and at +125C and 55C temperatures, Subgroups A10 and A11.
Note 11: Not tested at +25C, +125C, and 55C temperature (design characterization data).
Note 12: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
Test Circuitry
DS100298-6
Note 13: VCC, VCCA = +2V, VEE = 2.5V
Note 14: L1 and L2 = equal length 50 impedance lines
RT = 50 terminator internal to scope
Decoupling 0.1 F from GND to VCC and VEE
All unused outputs are loaded with 50 to GND
CL = Fixture and stray capacitance 3 pF
FIGURE 1. AC Test Circuit
Switching Waveforms
DS100298-7
FIGURE 2. Propagation Delays
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Switching Waveforms
(Continued)
DS100298-8
FIGURE 3. Propagation and Transition Times
DS100298-9
FIGURE 4. Setup, Hold and Pulse Width Times
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Physical Dimensions
inches (millimeters) unless otherwise noted
24-Pin Ceramic Dual-In-Line Package (D)
NS Package Number J24E
24-Lead Quad Cerpak (F)
NS Package Number W24B
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100343 Low Power 8-Bit Latch
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