VIGNAN’S INSTITUTE OF ENGINEERING FOR WOMEN
Kapujaggarajupeta , VSEZ (P.O), Visakhapatnam -530 049 .A.P
DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING
UNIT WISE QUESTION BANK
DIGITAL IC DESIGN (R16)
UNIT 1
1. Explain criteria for voltage threshold for high level and low level in NMOS inverter
characteristics?
2. Relate all the parameters of pseudo NMOS inverter using expressions?
3. Determine the pull-up to pull-down ratio for an NMOS inverter.
4. Explain the voltage transfer characteristics of a CMOS inverter with a neat diagram.
5. Write short notes on(a) Pseudo NMOS logic gate(b) Dynamic pass transistor
6. Deduce the necessary DC region equations of a CMOS inverter.
7. Explain the DC noise margin of CMOS logic.
8. Describe Threshold Voltage?
9. Discuss the gain of CMOS inverter?
10. Distinguish Pseudo NMOS logic and CMOS logic?
11. Explain Transistor equivalency with necessary proofs?
12. Discuss dependency of VT on various parameters.
13. Determine the input high voltage, low voltage and threshold voltage ofCMOS inverter?
UNIT 2
1. Illustrate CMOS transmission gate full adder
2. Explain the operation of a CMOS full adder circuit?
3. Develop an EX-OR gate using pass transistor Logic.
4. Discuss transmission gates with the relevant circuits.
5. Distinguish Pass Transistor logic and transmission gate logic.
6. Examine the operation of 2 inputs NMOS NAND.
7. Explain the procedure to design an adder circuit using CMOS logic.
8. Sketch AOI and OIA using CMOS.
9. Model NMOS complex logic gates using the Boolean function Z=A(D+C)+BE.
10. Discuss the DC analysis of CMOS Transmission gate by considering its region of
operations?
11. Develop an EX-NOR gate using Transmission gate Logic.
12. Illustrate CPL?
13. Explain depletion load two input NOR gate with necessary calculations?
14. Explain CMOS 2 input NAND gate with necessary calculations?
UNIT 3
1. Explain the behavior of a bistable element?
2. Deduce the output voltage equations of CMOS bistable element?
3. Illustrate D latch with necessary schematics?
4. Analyze CMOS clocked SR flip-flop with the help of necessary diagrams and truth table.
5. Distinguish NAND and NOR based SR latch?
6. Illustrate NOR based SR latch?
7. Illustrate NAND based SR latch?
8. Examine the Transient analysis of SR latch?
9. Discuss Clocked JK latch?
10. Sketch D latch by using tri state inverter?
11. Write short notes on SR latch in sequential MOS logic.
12. Explain SR latch using depletion load transistor with necessary diagrams and truth table?
13. Illustrate Master slave flip flop in detail?
UNIT-4
1. Explain the speed and power dissipation in dynamic CMOS logic.
2. What are the various issues in CMOS dynamic logic design? Explain anyone with a neat
sketch.
3. Explain voltage boots trapping with an example.
4. Explain the concept of charge storage and charge leakage associated with pass transistor
logic.
5. Draw the D latch by using CMOS logic and explain its operation in detail.
6. Write short notes SR latch in sequential MOS logic.
7. Write about dynamic pass transistor
UNIT-5
1. Explain capacitive parasitics?
2. Discuss the design techniques to reduce crosstalk?
3. Discuss the importance of ohmic voltage drop in resistive parasitics?
4. Explain electromigration?
5. Give a note on inductive parasitics?
6. Describe advanced interconnect techniques?
7. Explain the methods used to overcome capacitive and resistive parasitic?
UNIT-6
1. What are the types of DRAM? Explain any one.
2. Describe the leakage currents in DRAM cell.
3. Explain the principle of NOR gate flash memory with a neat diagram.
4. Write notes on Ferro electric Random Access Memory (FRAM).
5. Write about the leakage currents in SRAM.
6. Explain NOR flash memory.
7. Mention different types of RAM cells. Draw and explain the operation of a single bit
dynamic RAM cell.
8. Compare the performance of SRAM and DRAM.
