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William Stallings Computer Organization and Architecture 8 Edition Control Unit Operation

The document summarizes the operation of a computer's control unit through micro-operations. It discusses how the control unit sequences the fetch-execute cycle by coordinating the movement of data between registers and memory through micro-operations. These include fetching instructions from memory, executing operations, handling interrupts, and indirect addressing. The control unit ensures each micro-operation is performed atomically in the correct order through the use of control signals and a hardwired or programmable implementation.

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Zersh Ethio
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111 views18 pages

William Stallings Computer Organization and Architecture 8 Edition Control Unit Operation

The document summarizes the operation of a computer's control unit through micro-operations. It discusses how the control unit sequences the fetch-execute cycle by coordinating the movement of data between registers and memory through micro-operations. These include fetching instructions from memory, executing operations, handling interrupts, and indirect addressing. The control unit ensures each micro-operation is performed atomically in the correct order through the use of control signals and a hardwired or programmable implementation.

Uploaded by

Zersh Ethio
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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William Stallings

Computer Organization
and Architecture
8th Edition

Chapter 15
Control Unit Operation
Micro-Operations
• A computer executes a program
• Fetch/execute cycle
• Each cycle has a number of steps
• Called micro-operations
• Each step does very little
• Atomic operation of CPU
Constituent Elements of
Program Execution
00: Fetch
01: Indirect
10: Execute
11: Interrupt
Fetch - 4 Registers
• Memory Address Register (MAR)
—Connected to address bus
—Specifies address for read or write op
• Memory Buffer Register (MBR)
—Connected to data bus
—Holds data to write or last data read
• Program Counter (PC)
—Holds address of next instruction to be fetched
• Instruction Register (IR)
—Holds last instruction fetched
Fetch Sequence
• Address of next instruction is in PC
• Address (MAR) is placed on address bus
• Control unit issues READ command
• Result (data from memory) appears on
data bus
• Data from data bus copied into MBR
• PC incremented by 1 (in parallel with data
fetch from memory)
• Data (instruction) moved from MBR to IR
• MBR is now free for further data fetches
Fetch Sequence (symbolic)
• t1: MAR <- (PC)
• t2: MBR <- (memory)
• PC <- (PC) +1
• t3: IR <- (MBR)
• or
• t1: MAR <- (PC)
• t2: MBR <- (memory)
• t3: PC <- (PC) +1
• IR <- (MBR)
Indirect Cycle
• MAR <- (IRaddress) - address field of IR
• MBR <- (memory)
• IRaddress <- (MBRaddress)

• MBR contains an address


• IR is now in same state as if direct
addressing had been used
Interrupt Cycle
• t1: MBR <-(PC)
• t2: MAR <- save-address
• PC <- routine-address
• t3: memory <- (MBR)
• This is a minimum
—May be additional micro-ops to get addresses
—N.B. saving context is done by interrupt
handler routine, not micro-ops
Execute Cycle (ADD)
• Different for each instruction
• e.g. ADD R1,X - add the contents of
location X to Register 1 , result in R1
• t1: MAR <- (IRaddress)
• t2: MBR <- (memory)
• t3: R1 <- R1 + (MBR)
• Note no overlap of micro-operations
Execute Cycle (ISZ)
• ISZ X - increment and skip if zero
—t1: MAR <- (IRaddress)
—t2: MBR <- (memory)
—t3: MBR <- (MBR) + 1
—t4: memory <- (MBR)
— if (MBR) == 0 then PC <- (PC) + 1
• Notes:
—if is a single micro-operation
—Micro-operations done during t4
Execute Cycle (BSA)
• BSA X - Branch and save address
—Address of instruction following BSA is saved
in X
—Execution continues from X+1
—t1: MAR <- (IRaddress)
— MBR <- (PC)
—t2: PC <- (IRaddress)
— memory <- (MBR)
—t3: PC <- (PC) + 1
Types of Micro-operation
• Transfer data between registers
• Transfer data from register to external
• Transfer data from external to register
• Perform arithmetic or logical ops
Functions of Control Unit
• Sequencing
—Causing the CPU to step through a series of
micro-operations
• Execution
—Causing the performance of each micro-op
• This is done using Control Signals
Control Signals
• Clock
—One micro-instruction (or set of parallel micro-
instructions) per clock cycle
• Instruction register
—Op-code for current instruction
—Determines which micro-instructions are
performed
• Flags
—State of CPU
—Results of previous operations
• From control bus
—Interrupts
—Acknowledgements
Model of Control Unit
Hardwired Implementation (1)
• Control unit inputs
• Flags and control bus
—Each bit means something
• Instruction register
—Op-code causes different control signals for
each different instruction
—Unique logic for each op-code
—Decoder takes encoded input and produces
single output
—n binary inputs and 2n outputs
Hardwired Implementation (2)
• Clock
—Repetitive sequence of pulses
—Useful for measuring duration of micro-ops
—Must be long enough to allow signal
propagation
—Different control signals at different times
within instruction cycle
—Need a counter with different control signals
for t1, t2 etc.
Control Unit with Decoded Inputs
Problems With Hard Wired Designs
• Complex sequencing & micro-operation
logic
• Difficult to design and test
• Inflexible design
• Difficult to add new instructions

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