+ Unit 3

The Control Unit

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+ Road Way
The Control Unit
Chapter
◼ Control
of the
◼ Single Bus Organization processor
◼ Functional requirements
◼ Multiple Bus Organization ◼ Control signals
◼ Micro-operations ◼ Internal processor
organization
◼ The fetch cycle
◼ The Intel 8085
◼ The indirect cycle
◼ The interrupt cycle ◼ Hardwired
◼ The execute cycle implementation
◼ The instruction cycle ◼ Control unit inputs
◼ Control unit logic
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+ Cont…
Microprogrammed Control

Chapter
◼ Microinstruction sequencing
◼ Basic concepts ◼ Design considerations
◼ Microinstructions ◼ Sequencing techniques
◼ Micro programmed control ◼ Address generation
unit ◼ LSI-11 microinstruction
◼ Wilkes control sequencing
◼ Advantages and
disadvantages ◼ Microinstruction execution
◼ Taxonomy of microinstructions
◼ Microinstruction encoding
◼ LSI-11 Microinstruction
execution
◼ IBM 3033 Microinstruction
execution
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 1. Single Bus Organization

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
2. Micro-Operations
◼ The functional, or atomic, operations of a processor

◼ Series of steps, each of which involves the processor

registers

◼ Micro refers to the fact that each step is very simple and
accomplishes very little

◼ The execution of a program consists of the sequential

execution of instructions
◼ Each instruction is executed during an instruction cycle
made up of shorter subcycles (fetch, indirect, execute,
interrupt)
◼ The execution of each subcycle involves one or more
shorter operations (micro-operations)

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 Program Execution

Instruction Cycle Instruction Cycle Instruction Cycle

Fetch Indirect Execute Interrupt

µOP µOP µOP µOP µOP

Figure 20.1 Constituent Elements of a Program Execution

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+
The Fetch Cycle
◼ Occurs at the beginning of each instruction cycle and
causes an instruction to be fetched from memory

◼ Four registers are involved:

◼ Memory Address Register (MAR)
◼ Connected to address bus
◼ Specifies address for read or write operation
◼ Memory Buffer Register (MBR)
◼ Connected to data bus
◼ Holds data to write or last data read
◼ Program Counter (PC)
◼ Holds address of next instruction to be fetched
◼ Instruction Register (IR)
◼ Holds last instruction fetched

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 tMAR MAR 0000000001100100
MBR MBR
PC 0000000001100100 PC 0000000001100100
IR IR
AC AC

(a) Beginning (before t1) (b) After first step

MAR 0000000001100100 MAR 0000000001100100

MBR 0001000000100000 MBR 0001000000100000
PC 0000000001100101 PC 0000000001100101
IR IR 0001000000100000
AC AC

(c) After second step (d) After third Step

Figure 20.2 Sequence of Events, Fetch Cycle

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+
Rules for Micro-Operations
Grouping
◼ Proper sequence must be followed
◼ MAR  (PC) must precede MBR  (memory)

◼ Conflicts must be avoided

◼ Must not read and write same register at same time
◼ MBR  (memory) and IR  (MBR) must not be in same cycle

◼ One of the micro-operations involves an addition

◼ To avoid duplication of circuitry, this addition could
be performed by the ALU
◼ The use of the ALU may involve additional
micro-operations, depending on the functionality
of the ALU and the organization of the processor

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+
Indirect Cycle

◼ Once an instruction is fetched, the next step is to fetch

source operands

◼ Assuming a one-address instruction format, with direct

and indirect addressing allowed:
◼ If the instruction specifies an indirect address, then an
indirect cycle must precede the execute cycle
◼ The address field of the instruction is transferred to the MAR
◼ This is then used to fetch the address of the operand
◼ Finally, the address field of the IR is updated from the MBR, so
that it now contains a direct rather than an indirect address
◼ The IR is now in the same state as if indirect addressing had
not been used, and it is ready for the execute cycle

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+
Interrupt Cycle
◼ At the completion of the execute cycle, a test is made to determine
whether any enabled interrupts have occurred, and if so, the interrupt
cycle occurs

◼ The nature of this cycle varies greatly from one machine to another

◼ In a simple sequence of events:

◼ In the first step the contents of the PC are transferred to the MBR so that they
can be saved for return from the interrupt
◼ Then the MAR is loaded with the address at which the contents of the PC are to
be saved, and the PC is loaded with the address of the start of the interrupt-
processing routine
◼ These two actions may each be a single micro-operation
◼ Because most processors provide multiple types and/or levels of interrupts,
it may take one or more additional micro-operations to obtain the
Save_Address and the Routine_Address before they can be transferred to
the MAR and PC respectively
◼ Once this is done, the final step is to store the MBR, which contains the old
value of the PC, into memory
◼ The processor is now ready to begin the next instruction cycle

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+
Execute Cycle

◼ Because of the variety of opcodes, there are a number of

different sequences of micro-operations that can occur

◼ Instruction decoding
◼ The control unit examines the opcode and generates a sequence of
micro-operations based on the value of the opcode

◼ A simplified add instruction:

◼ ADD R1, X (which adds the contents of the location X to register R1)
◼ In the first step the address portion of the IR is loaded into the MAR
◼ Then the referenced memory location is read
◼ Finally the contents of R1 and MBR are added by the ALU
◼ Additional micro-operations may be required to extract the register
reference from the IR and perhaps to stage the ALU inputs or
outputs in some intermediate registers
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 11 (interrupt) 00 (fetch)
ICC?

10 (execute) 01 indirect

Setup Read Fetch

Opcode
interrupt address intstruction

Execute
ICC = 00 instruction ICC = 10 No Indirect Yes
addressing?

Yes Interrupt No
for enabled ICC = 10 ICC = 01
interrupt?

ICC = 11 ICC = 00

Figure 20.3 Flowchart for Instruction Cycle

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+
3.Control Unit
Functional Requirements
◼ By reducing the operation of the processor to its most
fundamental level we are able to define exactly what it is that
the control unit must cause to happen

◼ Three step process to lead to a characterization of the control

unit:
◼ Define basic elements of processor
◼ Describe micro-operations processor performs
◼ Determine the functions that the control unit must perform to
cause the micro-operations to be performed

◼ The control unit performs two basic tasks:

◼ Sequencing
◼ Execution

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 Instruction register

Control signals
within CPU

Control bus
Flags
Control signals
Control from control bus
Unit

Clock
Control signals
to control bus

Figure 20.4 Block Diagram of the Control Unit

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 C5

M C11
B
R
C10
C12 C3 C4
C8 C1 AC

PC IR
C7 C9
C6

C2 C13 Control
C0 ALU signals
M
A
R Control
Flags
unit

Clock
Control
signals

Figure 20.5 Data Paths and Control Signals

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 Table 20.1 Micro-operations and Control Signals

Micro-operations Active Control

Signals
t1: MAR ¬ (PC) C2

t2: MBR ¬ Memory

Fetch: C5, CR
PC ¬ (PC) + 1
t3: IR ¬ (MBR) C4
t1: MAR ¬ (IR(Address)) C8
Indirect: t2: MBR ¬ Memory C5, CR
t3: IR(Address) ¬ (MBR(Address)) C4

t1: MBR ¬ (PC) C1

t2: MAR ¬ Save-address
Interrupt:
PC ¬ Routine-address
t3: Memory ¬ (MBR) C12, CW

CR = Read control signal to system bus.

CW = Write control signal to system bus.
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. (Table can be found on page 719 in the textbook.)
 Control
unit

IR

PC

Address
lines MAR

Internal CPU bus

Data
lines MBR

AC

+
ALU

Figure 20.6 CPU with Internal Bus

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 INTA RST 6.5 TRAP
INTR RST 5.5 RST 7.5 SID SOD

Interrupt control Serial I/O

control

8-bit internal data bus

(8) (8) (8) (8) (8)

(8) instruction
Accumulator temp. reg. flags B reg. C reg.
register
(8) (8)
D reg. E reg.
(8) (8)
instruction H reg. L reg.
register
decoder (16) array
ALU and stack pointer
machine
cycle (16)
encoding program counter
incrementer/ (16)
decrementer
address latch
Power +5V
supply GND Timing and control
X1
Clk (8) (8)
X2
Gen Control Status DMA Reset address buffer address buffer

ClkOut RD WR ALE S0 S1 IO/M HLDA Reset out

A15 – A8 AD7 – AD0
Ready Hold Reset in
address bus address/data bus

Figure 20.7 Intel 8085 CPU Block Diagram

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 Address and Data Signals
High Address (A15–A8)
The high-order 8 bits of a 16-bit address.
Address/Data (AD7 –AD0)
The lower-order 8 bits of a 16-bit address or 8 bits of data. This multiplexing saves on pins.
Serial Input Data (SID)
A single-bit input to accommodate devices that transmit serially (one bit at a time).
Serial Output Data (SOD) Table
A single-bit output to accommodate devices that receive serially.
20.2
Timing and Control Signals
CLK (OUT)
The system clock. The CLK signal goes to peripheral chips and synchronizes their timing.
X1, X2
Intel
These signals come from an external crystal or other device to drive the internal clock 8085
generator.
Address Latch Enabled (ALE) External
Occurs during the first clock state of a machine cycle and causes peripheral chips to store the
address lines. This allows the address module (e.g., memory, I/O) to recognize that it is being Signals
addressed. (page 1 of 2)
Status (S0, S1)
Control signals used to indicate whether a read or write operation is taking place.
IO/M
Used to enable either I/O or memory modules for read and write operations.
Read Control (RD)
Indicates that the selected memory or I/O module is to be read and that the data bus is
available for data transfer.
Write Control (WR)
Indicates that data on the data bus is to be written into the selected memory or I/O location.

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(Table can be found on page 722 in the textbook.)
 Table 20.2 Intel 8085 External Signals (page 2 of 2)

Memory and I/O Initiated Symbols

Hold
Requests the CPU to relinquish control and use of the external system bus. The CPU will complete
execution of the instruction presently in the IR and then enter a hold state, during which no signals are
inserted by the CPU to the control, address, or data buses. During the hold state, the bus may be used
for DMA operations.
Hold Acknowledge (HOLDA)
This control unit output signal acknowledges the HOLD signal and indicates that the bus is now
available. Table
READY
Used to synchronize the CPU with slower memory or I/O devices. When an addressed device asserts
READY, the CPU may proceed with an input (DBIN) or output (WR) operation. Otherwise, the CPU
20.2
enters a wait state until the device is ready.

Interrupt-Related Signals
TRAP Intel
Restart Interrupts (RST 7.5, 6.5, 5.5)
Interrupt Request (INTR) 8085
These five lines are used by an external device to interrupt the CPU. The CPU will not honor the
request if it is in the hold state or if the interrupt is disabled. An interrupt is honored only at the
completion of an instruction. The interrupts are in descending order of priority.
External
Interrupt Acknowledge
Acknowledges an interrupt.
Signals
(page 2 of 2)
CPU Initialization
RESET IN
Causes the contents of the PC to be set to zero. The CPU resumes execution at location zero.
RESET OUT
Acknowledges that the CPU has been reset. The signal can be used to reset the rest of the system.

Voltage and Ground

VCC
+5-volt power supply
VSS
Electrical ground

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 X1 1 40 Vcc
X2 2 39 HOLD
Reset out 3 38 HLDA
SOD 4 37 CLK (out)
SID 5 36 Reset in
Trap 6 35 Ready
RST 7.5 7 34 IO/M
RST 6.5 8 33 S1
RST 5.5 9 32 Vpp
INTR 10 31 RD
INTA 11 30 WR
AD0 12 29 S0
AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
Vss 20 21 A8

Figure 20.8 Intel 8085 Pin Configuration

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 OUT Byte
M1 M2 M3
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3
3-MHz
CLK

A15 – A8 PCH PCH IO PORT

AD7 – AD0 PCH INSTR INSTR INSTR INSTR ACCUM

ALE

RD

WR

IO/M

PC out PC+1 PC INSTR IR X PC out PC+1 PC byte Z,W WZ out A Port

Instruction fetch Memory read Output write

Figure 20.9 Timing Diagram for Intel 8085 OUT Instruction

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+
4. Hardwired Implementation (1)

◼ Control unit inputs

◼ Flags and control bus

◼ Each bit means something

◼ Instruction register
◼ Op-code causes different control signals for each different
instruction
◼ Unique logic for each op-code
◼ Decoder takes encoded input and produces single output
◼ n binary inputs and 2n outputs
+
Hardwired Implementation (2)

◼ Clock
◼ Repetitive sequence of pulses
◼ Useful for measuring duration of micro-ops
◼ Must be long enough to allow signal propagation
◼ Different control signals at different times within instruction cycle
◼ Need a counter with different control signals for t1, t2 etc.
Control Unit with Decoded Inputs
Instruction register

Decoder

I0 I1 Ik

T1
T2
Timing Control
Clock
generator Unit Flags

Tn

C0 C1 Cm

Figure 20.10 Control Unit with Decoded Inputs

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+
Problems With Hard Wired
Designs
◼ Complex sequencing & micro-operation logic

◼ Difficult to design and test

◼ Inflexible design

◼ Difficult to add new instructions

 Table 21.1
5. Machine Instruction Set for Wilkes Example
Order Effect of Order
An C(Acc) + C(n) to Acc1
Sn C(Acc) – C(n) to Acc1
Hn C(n) to Acc2
Vn C(Acc2) ´ C(n) to Acc, where C(n) ³ 0
Tn C(Acc1) to n, 0 to Acc
Un C(Acc1) to n
Rn C(Acc) ´ 2–(n+1) to Acc
Ln C(Acc) ´ 2n+1 to Acc
Gn IF C(Acc) < 0, transfer control to n; if C(Acc) ³ 0, ignore (i.e., proceed serially)
In Read next character on input mechanism into n
On Send C(n) to output mechanism

Notation: Acc = accumulator

Acc1 = most significant half of accumulator
Acc2 = least significant half of accumulator
n = storage location n
C(X) = contents of X (X = register or storage location)
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 Microinstruction address
Jump condition
—Unconditional
—Zero
—Overflow
—Indirect bit
System bus control signals
Internal CPU control signals

(a) Horizontal microinstruction

Microinstruction address
Jump condition

Function codes

(b) Vertical microinstruction

Figure 21.1 Typical Microinstruction Formats

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 Fetch
cycle
routine
Jump to indirect or execute

Indirect
cycle
routine
Jump to execute

Interrupt
cycle
routine
Jump to fetch
Jump to opcode routine Execute cycle beginning

AND routine
Jump to fetch or interrupt

ADD routine
Jump to fetch or interrupt

Jump to fetch or interrupt

IOF routine

Figure 21.2 Organization of Control Memory

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 Control Address Register
Sequencing
Logic

Read

Control
Memory

Control Buffer Register

Figure 21.3 Control Unit Microarchitecture

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 Instruction Register

Control
Unit Decoder

ALU
Control Address Register
Flags Sequencing
Clock Logic

Read

Control
Memory

Control Buffer Register

Next Address Control

Decoder

Control Signals Control Signals

Within CPU to System Bus

Figure 21.4 Functioning of Microprogrammed Control Unit

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 from
instruction
register

Register II

Clock

Register I

Control Address
signals decoder

Conditional
signal
Control signals

Figure 21.5 Wilkes's Microprogrammed Control Unit

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 Table 21.2 Microinstructions for Wilkes Example (page 1 of 2)

Notation: A, B, C, . . . stand for the various registers in the arithmetical and control register units. C
to D indicates that the switching circuits connect the output of register C to the input register D;
(D + A) to C indicates that the output register of A is connected to the one input of the adding
unit (the output of D is permanently connected to the other input), and the output of the adder to
register C. A numerical symbol n in quotes (e.g., 'n') stands for the source whose output is the
number n in units of the least significant digit.

Control Next Micro-

Arithmetical Unit Register Unit Conditional Flip-Flop instruction
Set Use 0 1
0 F to G and E 1
1 (G to '1') to F 2
2 Store to G 3
3 G to E 4
4 E to decoder —
A 5 C to D 16
S 6 C to D 17
H 7 Store to B 0
V 8 Store to A 27
T 9 C to Store 25
U 10 C to Store 0
R 11 B to D E to G 19
L 12 C to D E to G 22
G 13 E to G (1)C5 18
I 14 Input to Store 0
O 15 Store to Output 0
16 (D + Store) to C 0
17 (D – Store) to C 0
18 1 0 1
19 D to B (R)* (G – '1') to E 20
20 C to D (1)E5 21
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(Table can be found on page 738 in the textbook.)
 Table 21.2 Microinstructions for Wilkes Example (page 2 of 2)

21 D to C (R) 1 11 0
22 D to C (L)† (G – ‘1’) to E 23
23 B to D (1)E5 24
24 D to B (L) 1 12 0
25 ‘0’ to B 26
26 B to C 0
27 ‘0’ to C ‘18’ to E 28
28 B to D E to G (1)B1 29
29 D to B (R) (G – ‘1’) to E 30
30 C to D (R) (2)E5 1 31 32
31 D to C 2 28 33
32 (D + A) to C 2 28 33
33 B to D (1)B1 34
34 D to B (R) 35
35 C to D (R) 1 36 37
36 D to C 0
37 (D – A) to C 0

*Right shift. The switching circuits in the arithmetic unit are arranged so that the least significant
digit of the register C is placed in the most significant place of register B during right shift micro-
operations, and the most significant digit of register C (sign digit) is repeated (thus making the
correction for negative numbers).
†Left shift. The switching circuits are similarly arranged to pass the most significant digit of
register B to the least significant place of register C during left shift micro-operations.

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+
6. Microinstruction Sequencing

◼ The two basic tasks performed by a microprogrammed

control unit are:
◼ Microinstruction sequencing
◼ Get the next microinstruction from the control memory
◼ Microinstruction execution
◼ Generate the control signals needed to execute the
microinstruction
◼ In designing a control unit, these tasks must be considered
together because both affect the format of the microinstruction
and the timing of the control unit

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 Design Considerations
In executing a microprogram the
Two concerns are involved in the design
address of the next microinstruction to
of a microinstruction sequencing
be executed is in one of these
technique:
categories:

The size of the microinstruction Determined by instruction register

• Minimizing the size of the control memory • Occurs only once per instruction cycle, just
reduces the cost of that component after an instruction is fetched

The address-generation time Next sequential address

• Execute microinstruction as fast as possible • Most common in most designs

Branch
• Are a necessary part of a microprogram

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 control address
register

address
decoder

control
memory

address address control

control buffer
1 2
register

address
branch selection
flags multiplexer instruction
logic
register

Figure 21.6 Branch Control Logic: Two Address Fields

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 address
decoder

control
memory

control
control address
buffer control address +1
register
register

branch
flags multiplexer instruction
logic
address register
selection

Figure 21.7 Branch Control Logic: Single Address Field

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 address
decoder

control
memory

control
buffer
register control address
branch entire +1
control register
field
field address
field
gate and
function
logic

branch multiplexer instruction

logic address register
flags
selection

Figure 21.8 Branch Control Logic: Variable Format

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 Table 21.3
Microinstruction Address Generation Techniques

Explicit Implicit
Two-field Mapping
Unconditional branch Addition
Conditional branch Residual control

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 00 07 08 09 10 11 12

BC(4) BE(4)
BB(4) BD(4) BF(7)
BA(8)

Figure 21.9 IBM 3033 Control Address Register

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+
7. LSI-11 Microinstruction
Sequencing
◼ LSI-11 is a microcomputer version of a PDP-11, with the main
components of the system residing on a single board

◼ The LSI-11 is implemented using a microprogrammed control

unit

◼ Makes use of a 22-bit microinstruction and a control memory of

2K 22-bit words

◼ The next microinstruction address is determined in one of five

ways:
◼ Next sequential address
◼ Opcode mapping
◼ Subroutine facility
◼ Interrupt testing
◼ Branch
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 Instruction
Register

ALU
Control Address Register
Flags Sequencing
Clock Logic

Control
Memory

Control
Control Buffer Register Logic

Internal External
Control Control
Signals Signals

Figure 21.10 Control Unit Organization

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 Table 21.4
The Microinstruction Spectrum

Characteristics
Unencoded Highly encoded
Many bits Few bits
Detailed view of hardware Aggregated view of hardware
Difficult to program Easy to program
Concurrency fully exploited Concurrency not fully exploited
Little or no control logic Complex control logic
Fast execution Slow execution
Optimize performance Optimize programming
Terminology
Unpacked Packed
Horizontal Vertical
Hard Soft

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 Field Field Field

Decode Decode Decode

logic logic logic

Control signals

(a) Direct encoding

Field Field Field

Decode Decode Decode

logic logic logic

Decode
logic

Control signals

(b) Indirect encoding

Figure 21.11 Microinstruction Encoding

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 Simple register transfers Special sequencing operations
0 0 0 0 0 0 MDR Register 0 1 0 0 0 0 CSAR Decoded MDR

0 0 0 0 0 1 Register MDR 0 1 0 0 0 1 CSAR Constant (in next byte)

0 0 0 0 1 0 MAR Register 0 1 0 0 1 0 Skip

Register ALU operations

Memory operations select 0 1 1 0 0 0 ACC ACC + Register
0 0 1 0 0 0 Read
0 1 1 0 0 1 ACC ACC – Register
0 0 1 0 0 1 Write
0 1 1 0 1 0 ACC Register

0 1 1 0 1 1 Register ACC

0 1 1 1 0 0 ACC Register + 1

Register
select
(a) Vertical microinstruction format

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Field 1 2 3 4 5 6

Field definition
1 - register transfer 4 - ALU operation
2 - memory operation 5 - register selection
3 - sequencing operation 6 - Constant

(b) Horizontal microinstruction format

Figure 21.12 Alternative Microinstruction Formats for a Simple Machine

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 Control
store

11
22
22 Microinstruction
bus
18 16

Control Data
chip chip

With no number indicated,

4 a path with multiple signals
16

Bus control
and other Bus logic
procesor
board logic
LSI-11 system
bus

Figure 21.13 Simplified Block Diagram of the LSI-11 Processor

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 Control data register

Control
store

Control address register

Microprogram
sequence
control

Return register

Translation
array INT
Instruction register

Figure 21.14 Organization of the LSI-11 Control Unit

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 Table 21.5
Some LSI-11 Microinstructions
Arithmetic Operations General Operations
Add word (byte, literal) MOV word (byte)
Test word (byte, literal) Jump
Increment word (byte) by 1 Return
Increment word (byte) by 2 Conditional jump
Negate word (byte) Set (reset) flags
Conditionally increment (decrement) byte Load G low
Conditionally add word (byte) Conditionally MOV word (byte)
Add word (byte) with carry
Conditionally add digits Input/Output Operations
Subtract word (byte) Input word (byte)
Compare word (byte, literal) Input status word (byte)
Subtract word (byte) with carry Read
Decrement word (byte) by 1 Write
Read (write) and increment word (byte) by 1
Logical Operations Read (write) and increment word (byte) by 2
AND word (byte, literal) Read (write) acknowledge
Test word (byte) Output word (byte, status)
OR word (byte)
Exclusive-OR word (byte)
Bit clear word (byte)
Shift word (byte) right (left) with (without)
carry
Complement word (byte)
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 4 1 1 16
Special
Encoded micro-operations
functions

Load return register

Translate
(a) Format of the full LSI-11 microinstruction

5 11 4 8 4

Opcode Jump address Opcode Literal value A register

Unconditional jump microinstruction format Literal microinstruction format

4 4 8 8 4 4

Opcode Test code Jump address Opcode B register A register

Conditional jump microinstruction format Register jump microinstruction format

(b) Format of the encoded part of the LSI-1 1 microinstruction

Figure 21.15 LSI-11 Microinstruction Format

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 0 35

P AA AB AC AD AE AF AG AH AJ AK AL

A, B, C, D registers Arithmetic Shift

36 71

P BA BB BC BD BE BF BH

Next address Storage address

72 107

P BH CA CB CC CD CE CF CG CH

Shift control Local storage Miscellaneous controls

Storage address
108 125

P DA DB DC DD DE

Testing and condition code setting

Figure 21.16 IBM 3033 Microinstruction Format

 ALU Control Fields
AA(3) Load A register from one of data registers
AB(3) Load B register from one of data registers
AC(3) Load C register from one of data registers
AD(3) Load D register from one of data registers
AE(4) Route specified A bits to ALU
AF(4)
AG(5)
Route specified B bits to ALU
Specifies ALU arithmetic operation on A input
Table 21.6
AH(4) Specifies ALU arithmetic operation on B input
AJ(1) Specifies D or B input to ALU on B side
AK(4) Route arithmetic output to shifter IBM 3033
CA(3) Load F register
CB(1) Activate shifter Microinstruction
Control
CC(5) Specifies logical and carry functions
CE(7) Specifies shift amount

AL(1)
Sequencing and Branching Fields
End operation and perform branch
Fields
BA(8) Set high-order bits (00–07) of control address register
BB(4) Specifies condition for setting bit 8 of control address register
BC(4) Specifies condition for setting bit 9 of control address register
BD(4) Specifies condition for setting bit 10 of control address register
BE(4) Specifies condition for setting bit 11 of control address register
BF(7) Specifies condition for setting bit 12 of control address register
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
(Table can be found on page 755 in the textbook.)
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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.