Chapter 5

CONTROL UNIT DESIGN

Contents:
1. Basic Micro-sequencer (Control Unit) Design and Operations
2. Micro-instruction Formats
3. Design and Implementation of a Very Simple Micro-sequencer
4. Control Unit: Layout, Control Sequence Generation, Mapping Logic
5. Generation of Micro-operations using Horizontal and Vertical Microcode
6. Directly generating the control signal from the Microcode
7. Reducing tile Number of Micro-instructions
8. Micro-programmed Vs Hardwired Control Unit

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5.0 Introduction to Micro sequencer
• Hardwired control is one of the two most commonly used control
methods.
• The another popular control method is the micro-sequencing.
• Instead of generating the control signals using combinational and
sequential logic, a microsequencer stores its control signals in a lookup
ROM, the microcode memory.
• By accessing the locations of the ROM in the correct order, the lookup
ROM asserts the control signals in the proper sequence to realize the
instructions in the processor’s instruction set.

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5.1 Basic Microsequencer (CU) Design and Operations
• Like in hardwired control unit, a
microsequencer is also designed as a finite
state machine.
• Figure aside shows a generic
microsequencer.

Generic microsequencer Organization

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5.1 Basic Microsequencer (CU) Design and Operations
1. Generate Next Address: It’s a block of micro-sequencer, typically
generate all possible next address and then select correct next address to
pass to the register.
– One possible value of the next address is the current address + 1.
– Another possible address is an absolute address supplied by the
micro-code memory
2. REGISTER: stores a value that corresponds to 1-state in the CPU state
diagram.
– It serves as the address i.e. input to the micro-code memory.
3. MICRO-CODE memory: outputs a micro-instruction (the content of
memory location for this address). Collectively, all of the
microinstructions comprise the microcode, or microprogram, for the
CPU. It consists of micro-instructions.
– MICRO-INSTRUCTION: consists of several bit of fields which can be
broadly classified into two groups:
a) micro-operation that generates the control signal.
b) Sequencer is used to generate the next address to be stored in
the register. Generic microsequencer Organization

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2.5 Micro-instruction formats
SELECT MICRO-OPERATIONS ADDR

Each micro-instruction in the Microcode memory

consists of : Example:
1. SELECT field: determines source of address of next
microinstruction. It doesn’t specify the actual address, but
only the source of the address.

2. ADDR field: specifies an absolute address. Used when

performing absolute jump. => Microinstructions that specify
another source for the next address, such as mapping address
do not use bits of this field.

3. MICRO-OPERATIONS field: three primary methods.

• horizontal microcode
• vertical microcode
• Direct generation of control signals

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 a) Horizontal Microcode

Figure: Horizontal microinstruction format

• In horizontal micro-instruction, each control signal is represented by a single bit in the control word.
• Thus, if the design has 500 control signals, it requires 500 bits in each control word to store the control bits.
• In this format, the control store looks horizontal in shape, since the control words are wide.
• The format of the horizontal instruction is as:
– One bit for each internal processor control line
– One bit for each system bus control line
– Condition bit for flags
– Address field
• Advantage: Fast operation as the control signals will be ready as soon as the control word is fetched form the control store.
• Disadvantages: The control word occupies more space of the control store.

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a) Horizontal Microcode
• Firstly, Listing every microoperation performed by CPU (mnemonics
are used).
• Assign one bit in the microoperations field of microinstruction to
each microoperation. This will result in large microinstruction.
• For example:
– If a CPU performs 50 different microoperations, the micro-operation
field uses 50 bits for every micro-operation.

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b) Vertical Microcode

Figure: Vertical microinstruction format

• A vertical micro-instruction format is quite similar to the horizontal micro-instruction. It also consists of four fields:
– Microinstruction address field
– Condition field
– Control signals to CPU
– Control signals to system bus
• Here, the difference is that: instead of a single 1-bit for each element, a code is used for each action to be performed.
However, a decoder is used for translation of these codes into individual control signals.
• These are more compact than the horizontal microinstruction. Hence, called vertical since the width is reduced.
• For eg: for each 16 ALU operations, 16 individual bits are required in horizontal micro-instruction. But only 4 encoded bits
are used in vertical micro-operation.
• Advantage: shorter width of control word
• Disadvantage: slower implementation

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b) Vertical Microcode
• The number of bits in micro-operation filed can be reduced by using vertical micro-
code.
• In vertical microcode, the micro-operations are grouped into fields.
• Each microoperation is assigned a unique encoded value in this field.
• For example:
• 16 microoperations can be encoded using 4 bits, from 0000 to 1111.
• Vertical microinstruction require fewer bits than their equivalent horizontal micro-
instructions. However, micro sequencers that use vertical microcode must include a
decoder for each micro-operation field to generate actual micro-operation signals.

In both horizontal and vertical microcode, the CPU must convert micro-operation signals
to the control signals that load, clear and increment registers, enable buffers and select
the functions to be performed by ALU.

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5.3 Design and Implementation of a Very
Simple Micro-sequencer
• To illustrate the process of microsequencer design, let us consider the
very simple CPU that was developed in the previous chapter.
• We redesign this CPU ,this time using a microsequencer instead of
hardwired control.
• The instruction set, finite state machine, data paths and ALU are the
same.

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5.3 Design and Implementation of a Very
Simple Micro-sequencer
• Here, only two possible next address are
used:
– i) the opcode mapping and
– ii) Absolute jump.
• The last state of fetch cycle, fetch 3, goes
to one of the 4 execute routines (ADD,
AND , JMP, INC). This is implemented by
mapping input.
• The remaining states , each must go to
one specific next state, which is
implemented by using an absolute jump.
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5.3 Design and Implementation of a Very
Simple Micro-sequencer
• Since, there are two possible addresses, the micro-sequencer must select one of them. So, there is a multiplexer to do this.
• The select bit is generated by microsequencer to choose the correct next address.
• The minimum number of bits needed to select is 4, which is the size of absolute address (because for our CPU, a total of 9 states
are there).
– The mapping hardware also generates an address of 4 bits wide.
– The output of multiplexer is also 4 bits that is input to register and
output of register that is input to address inputs of microcode memory.

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5.4 Control unit :

Layout, Control Sequence Generation,

Mapping Logic

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• Consider below state diagram and Hardwired Control Unit for a relatively
small CPU (from previous chapter).

RTL code

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• For this CPU, the micro-sequencer use the same mapping
function that was used for hardwired control unit. 1
IR[1..0]0
• This produces address of 1000, 1010, 1100 and 1110 (8,
10, 12 and 14) for ADD1, AND1, JMP and INC1.
• The address for remaining states can be assigned
somewhat randomly. Here we assign consecutive states to
consecutive location in microcode memory (control
memory)

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• To go from Fetch1 to Fetch2, SEL=0
and ADDR=0001
– Setting SEL=0 causes micro-sequencer
to get its next address from ADDR field;
– and setting ADDR field to 0001 causes
it to go to location corresponding to
state Fetch2.
• But Fetch 3 must map to correct
execute routine.
– So, it requires SEL=1 to select mapping
address.
– Now, the contents of ADDR field are
not used in microinstruction, it does
not matter what value it has.

Partial Microcode for the very simple microprocessor

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5.5 Generation of Micro-operations

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i) Generating the micro-operations using Horizontal Microcode
• Microsequencer has two tasks:
– i) to generate the correct micro-operations, and
– ii) to follow the correct sequence of states.
• One task is complete.
• Now, the other task is to generate correct micro-
operations, and associated control signals. This can
be done by horizontal microcode or vertical
microcode and Direct generation of control signals.
• In horizontal microcode, each microoperation is
represented by one-bit in each micro-instruction.
The greater the number of microoperation, the
larger the microcode will be.
• The microoperations and their mnemonics are:

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Horizontal Microcode
• Since there are 9 micro-
operations, each word of
microcode requires 9 bits
to represent them, 1 bit References
per micro-operation.
• A value of 1 means the
micro-operation is to
occur and a value of 0
means that it does not.
• To complete the
microcode, we simply fill
in the values for micro-
operations.
• The resultant microcode is
shown in table aside
(below).

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Horizontal Microcode
• Here, for all the states,
ARDR and IRDS have the
same value. References

• So, we can use one

output to drive both
micro-operations.
• Hence, we use AIDR that
combines both
operations ARDR[5..0]
and IRDR[7..6]

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ii) Generating Micro-operation using Vertical Microcode
• Vertical microcode reduce the number of
bits in section of microcode.
• In vertical microcode, the microoperations
are grouped into fields such that no more
than one microoperation in a field is active
during any state. Then a unique value is
assigned to each microoperation in the
field.
• For eg, a field with 8 (i.e. 23=8) different
microoperations would require 3 bits each
value from 000 to 111 would be assigned to
one of the eight microoperations. The
microoperation field bits are output from
microcode memory to a decoder.

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a) When two microoperations occurs during
the same state, assign them to different
fields.
For eg, DRM and PCIN both occur during
Fetch2 states. So, must be assigned to References
different fields, one in M1 field and other in
M2
b) Include a NOP (No operation ) if necessary,
when no microoperation is active.
c) Group together micro-operation in same
field that modify some register.

The CPU requires at least two fields for its

microoperation labeled as M1 and M2.

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 References

Vertical Microcode for the Very Simple Micro-sequencer Generating micro-operations from vertical
microcode for the very simple CPU
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iii) Directly generating the control signals from the Microcode
• Instead of outputting micro-operations form the microcode memory and
then generating the control signals from these micro-operations, we can
output the control signals directly.
• As before, the sequencing portion of the control unit design remains the
same.
• This portion includes the mapping logic, next address multiplexer, register,
and microcode memory as well as microcode fields SEL and ADDR.
• In place of the micro-operations( in the horizontal microcode design) or
M1 and M2 (in the vertical microcode design), the micro-sequencer can
include 1 bit for each control signal.
• For each word of microcode memory, each control bit is set to 1 if the
signal is to be active , and 0 otherwise.

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 • To illustrate this, consider the micro-
operations that occur during FETCH2, DR M
and PC PC +1
• To implement DR M , we must enable:
– READ to output data from memory,
– MEMBUS to allow this data onto the internal
system bus, and
– DRLOAD to load the data from the bus into DR.
• Also, we must enable:
– PCINC to perform the second microoperation.
• All the other signals must be
– set to zero for this microinstruction so that no
other micro-operation is triggered.
• Doing this for every microinstruction
produces the microcode shown in Table in
next slide.

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• To illustrate this, consider the micro-
operations that occur during FETCH2,
DR M and PC PC +1 References
• To implement DR M , we must
enable:
– READ to output data from memory,
– MEMBUS to allow this data onto the
internal system bus, and
– DRLOAD to load the data from the bus
into DR.
• Also, we must enable:
– PCINC to perform the second
microoperation.
• All the other signals must be
– set to zero for this microinstruction so
that no other micro-operation is triggered.
• Doing this for every microinstruction
produces the microcode shown in
Table in next slide
• In table above, it is to be noted that
DRLOAD, MEMBUS and READ always
have the same value.

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• Directly generating the control signals offers advantage over the other two
methods.
• It does not require additional logic to convert the outputs of the
microcode memory to control signals.
• However, this type of code is less readable and thus more difficult to
debug.

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5.6 Reducing the number of micro-instructions
• Just as with the micro-
operations ARDR and
IRDR in the horizontal
microcode design, we can
combine these signals
because they always have
the same value.
• One bit can be used
instead of three; that one
bit can drive all three
signals.
• The revised microcode
with the one bit labeled
DMR is shown in Table
7.10

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5.6 Reducing the number of micro-instructions

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5.8 Micro-programmed Vs Hardwired Control Unit
Hardwired Micro-programmed
1. Uses flags, decoder, logic gates and 1. Uses sequence of micro-instruction in
other digital circuits micro-programming language
2. As name implies, it is a hardware 2. It is midway between Hardware and
control unit. software.
3. On the basis of input signal, output is 3. It generates a set of control signal on
generated. the basis of control line.
4. Difficult to design, test and 4. Easy to design and implement
implement.
5. Inflexible to modify 5. Flexible to modify
6. Faster mode of operation 6. Slower mode of operation
7. Expensive and high error 7. Cheaper and less error
8. Used in RISC processor 8. Used in CISC processor

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Exam questions:

1. Design a microsequencer control unit with horizontal microcode for

the CPU described in question 7 (i.e. above question). [PU 2017 Fall]

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7. There is a very simple CPU for the given set of Instruction: [PU 2017 Spring]

Let the instruction width be 8 bits and address is 6 bits. Design the CPU’s register
section, state diagram and ALU.

2. Design a microsequencer control unit which directly generate control signals for
the CPU described in question 7 (Above question) . [PU 2017 Spring]

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7. There is a very simple CPU for the given set of Instruction: [PU 2018 Fall]

Let the instruction width be 8 bits and address is 6 bits. Design the CPU’s
register section, state diagram and ALU.

3. Design a microsequencer control unit with horizontal microcode for the

CPU described in question 7 (above question) [PU 2018 Fall]

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 4. Design a microsequencer control unit with horizontal microcode for
the CPU described in question 7. [PU 2018 Spring]

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 5. Design a microsequencer control unit with horizontal microcode for the
CPU described in question 7. [PU 2019 Spring]

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 End of chapter 5

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