[go: up one dir, main page]
Scribd
Upload
24 views1 page

Lab On Arrays

The document outlines a lab assignment focused on arrays and SystemVerilog programming. It includes tasks such as declaring enumerated types, implementing logic circuits, performing loop operations, managing associative arrays, and creating a queue with specific functionalities. Additionally, it requires the creation of a packed structure and displaying specific parts of it.

Uploaded by

brajeshkp7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
24 views1 page

Lab On Arrays

The document outlines a lab assignment focused on arrays and SystemVerilog programming. It includes tasks such as declaring enumerated types, implementing logic circuits, performing loop operations, managing associative arrays, and creating a queue with specific functionalities. Additionally, it requires the creation of a packed structure and displaying specific parts of it.

Uploaded by

brajeshkp7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

Lab on Arrays

1)Declare enumerated type variable and assign it a value from Monday to Sunday. Display first,
last values also print total elements of the enumerated type variable. Declare two variables a and
b with logic and bit respectively. Assign b value to a. Print both a and b.

2) Implement Full Adder using always_comb, Model D latch using always _latch and DFF using
always_ff. Write a task to count the number of 1’s in a binary word.

3) Write a code to multiply a loop variable by 2 starting from 1 to 25. Use break and continue in
the loops to control the loop flow and print statements for the result.

4) Add 50 integer values at random locations (between 1 to 100) of an integer associative array.
Check value at index 2 and 45 exists..?
Print the value at first index along with index.
Print the value at last index along with index.
Check the array size.
Delete 5th, 10th and 15th index if they exists..
Print array size again.

5) Create the SystemVerilog code for the following requirements


a. Create a 3-byte queue and initialize it with 2, −1, and 127
b. Print out the sum of the queue in the decimal radix
c. Print out the min and max values in the queue
d. Sort all values in the queue and print out the resulting queue
e. Print out the index of any negative values in the queue
f. Print out the positive values in the queue
g. Reverse sort all values in the queue and print out the resulting queue

6) Declare the packed structure for the following format. Display the part select [24:13].

You might also like