30 Premium SystemVerilog Coding
Interview Questions
Designed for ASIC/FPGA/VLSI Aspirants
Curated by KITTU K PATEL
May 21, 2025
Instructions
• These questions are strictly based on SystemVerilog core coding concepts.
• Practice each by implementing and simulating in your preferred simulator (ModelSim,
Questa, etc.).
• Focus on logic building, syntax accuracy, and modularity.
SystemVerilog Coding Questions
1. Write a ‘for‘ loop in SystemVerilog to display even numbers between 0 and 100.
2. Create a task that takes a dynamic array and returns the reversed version of it.
3. Define a function to find the maximum value in a dynamic array of integers.
4. Write a function to check whether a given number is prime.
5. Declare a queue and write code to calculate the sum of all its elements.
6. Demonstrate how to use ‘foreach‘ loop with an associative array to print keys and
values.
7. Write a task to perform the transpose of a 3x3 2D array.
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8. Use constraints to randomize two integers such that one is always twice the other.
9. Implement a ‘foreach‘ loop to compute the factorial of numbers from 1 to 5.
10. Create a SystemVerilog interface containing ‘clk‘, ‘reset‘, and a data bus. Instantiate
it in a testbench.
11. Write a recursive function to calculate factorial of a number ‘n‘.
12. Implement a task to check whether a given string is a palindrome.
13. Write a function that swaps the odd and even bits in an 8-bit number.
14. Create a module that acts as a clock divider dividing input clock by 4.
15. Implement matrix multiplication for two 3x3 matrices using 2D arrays.
16. Write a function to toggle a specific bit in a given number using bitwise operators.
17. Create a FIFO using SystemVerilog queue (‘push_back‘, ‘pop_front‘) with overflow
checking.
18. Write a task to detect duplicate values in a dynamic array and display them.
19. Create a covergroup that samples values from a 3-bit counter and ensures full bin
coverage.
20. Write a SystemVerilog assertion to check that a ‘req‘ signal is followed by ‘ack‘ within
3 clocks.
21. Implement the bubble sort algorithm on a dynamic array of 10 elements.
22. Write a function to reverse the bits of an 8-bit unsigned value.
23. Implement a function that counts the number of 1’s in a binary number (population
count).
24. Write a function to split a string into tokens using spaces as delimiters.
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25. Create a simple clock generator module that toggles every 5 time units.
26. Demonstrate blocking vs non-blocking assignments using two ‘always‘ blocks with a
simulation result.
27. Sort a SystemVerilog queue of integers using a sorting algorithm of your choice.
28. Implement an 8-bit serial shift register with parallel load.
29. Write a function to convert a binary number to Gray code.
30. Create a static task to demonstrate variable retention between calls.
Prepared with passion by VeriCore – Empowering VLSI Minds
