Verilog 1
Verilog interview questions
1.) Verilog code for Flip Flop and Latch ?
2.) Verilog Code for D latch with Asynchronous enable , then to convert in
to a Flip Flop?
3.) Verilog Data types?
4.) Difference between Functions and Tasks? Default return type and width
of function ,How do function return a value?
5.) Verilog code for bidirectional memory having read ,write ,address, input
and bidirectional data line?
6.) Event queue of verilog?
7.) Basic Structure of verilog code for FSM?
8.) Blocking and Non-Blocking Statements?
9.) Synchronous and Asynchronous resets?
10.) Types of delays, Significance of inertiak and Transport delays?
11.) Significance of Scoreboard?
12.) Difference between initial block and final block?
13.) What are parallel blocks in Verilog?
14.) What are race conditions?
15.) How to we avoid races in Verilog?
16.) Difference between $display , $monitor and $strobe ?
17.) Discuss $monitor in always block?
18.) Verilog code for MUX?
19.) Verilog code for DeMUX?
20.) Verilog code for up-down Counter ?
Manjunadha
7207534529
manjusairao22@gmail.com
Verilog 2
21.) What changes will happen if we wire $monitor with inter assignment
delay (#10 $monitor(“ “)) ?
22.) Which will be faster , 4x1 MUX using if else or case ?
23.) Verilog Nets and reg their default values?
24.) Write a code in which there is a race condition?
25.) Parameterized module question was there ?
26.) Generate statement question was there?
27.) Difference between Verilog and System Verilog?
28.) Difference between case, caseX, caseZ ?
29.) Write a Verilog code for a design that gives output 1 when the input
receives ‘1’ 16times?
30.) Write a Verilog code for a counter that counts upto 16 with
asynchronous reset?
31.) FSM
a.) What is FSM ?
b.) Need of FSM?
c.) Where have you used them give Practical application?
32.) Draw FSM for a Sequence detector that detects the sequence 1101 .
Also, write the Verilog code for it ?
33.) write code or algorithm for finding the Prime numbers?
34.) Design a mod-5 Counter which initialized with 010 ?
35.) we have a 4-bit counter which counts from 0 to 15 and we have to
show this count on two seven segment displays ass like traffic signals
which count like00,01,02_ _ _ 15 so what is the logic we have to use toshow
this count on display ?
36.) Some times they will give Circuit and they will ask draw the Wave
form?
Manjunadha
7207534529
manjusairao22@gmail.com
Verilog 3
37.) Types of ports in Verilog?
38.) What are Procedural , Continuous and Continuous Procedural
assignment ?
39.) Can we write timing Constraits in Verilog ?
40.) Wor, Wand and trireg ?
41.) Can we take output as wire in CPA ?
42.) What is delta simulation time?
43.) What is meant by inferring latches and how can you avoid it?
44.) Which will be updated first - variables or signals ?
45.) Why is it necessary to list all inputs in the sensitivity list of a
combinational circuit ?
46.) What are the main differences between VHDL and Verilog ?
47.) Give some examples of commonly used Verilog system tasks and their
purposes ?.
48.) Write Verilog code to swap contents of two registers with and without
a temporary register ?
49.) What is duty cycle ?
50.) What are parallel threads in Verilog ?
Manjunadha
7207534529
manjusairao22@gmail.com
