Verilog Interview Questions for Entry-Level (1-2 Years Experience)
🔹 Basic Concepts
1. What is the difference between ** and ** in Verilog?
2. wire is used for combinational logic and must be driven by assign statements.
3. reg is used in procedural blocks (like always ) and can hold values.
4. How does blocking ( **) differ from non-blocking (** ) assignment?
5. Blocking executes sequentially, non-blocking allows parallel updates.
6. Use <= in sequential logic to avoid race conditions.
7. What is the difference between ** and ** blocks?
8. initial executes once at time 0 (simulation only), always repeats as per sensitivity.
9. Can you synthesize an `` block? Why or why not?
10. Usually not synthesizable, used only in simulation (e.g., for testbenches).
11. What is the purpose of ** and how is it different from ** ?
12. parameter can be overridden at instantiation.
13. localparam is constant and cannot be overridden.
🔹 Combinational vs Sequential Logic
1. Write a 2:1 multiplexer in Verilog. How do you ensure it's synthesizable?
assign y = sel ? b : a;
1. Design a D flip-flop with async reset.
always @(posedge clk or posedge reset) begin
if (reset) q <= 0;
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else q <= d;
end
1. How do you infer a latch in Verilog? How would you avoid it?
2. Missing else in combinational logic creates latch. Avoid by specifying outputs for all input
conditions.
3. What happens if you miss a case in a combinational always block using ``?
4. Latch may be inferred due to incomplete assignment.
5. How would you model edge-sensitive behavior in Verilog?
6. Use always @(posedge clk) or @(negedge clk) .
🔹 Finite State Machines (FSMs)
1. How do you design a FSM in Verilog? What are Moore and Mealy machines?
◦ FSMs have states, state transitions, and outputs.
◦ Moore: output depends on state only. Mealy: output depends on state and input.
2. What is the difference between one-hot and binary encoding for FSMs?
◦ One-hot uses more flip-flops, simpler logic. Binary uses fewer bits, complex logic.
3. What should be avoided when writing a FSM to prevent synthesis/simulation mismatches?
◦ Avoid incomplete case statements, unintended latches, or ambiguous reset behavior.
🔹 Synthesis and Coding Guidelines
1. Is `` loop synthesizable in Verilog? Give an example.
◦ Yes, if bounds are static. Example: loop unrolling for shift registers.
2. How do you write a synthesizable ROM?
reg [7:0] rom [0:15];
assign data_out = rom[addr];
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3. What kind of Verilog constructs are not synthesizable?
◦ initial , $display , #delay , file I/O, dynamic memory, some procedural forks.
4. What is the difference between **, ** , and ``? Are these synthesizable?
◦ Simulation-only system tasks. Not synthesizable.
🔹 Practical & Debugging
1. Simulation works but synthesis output is wrong or stuck. What would you check?
◦ Uninitialized registers, improper reset, latches, synthesis tool warnings.
2. How do you prevent race conditions in RTL design?
◦ Use non-blocking assignments in sequential logic. Separate combinational and sequential
logic.
3. How would you write a testbench for a simple module (like adder or counter)?
◦ Instantiate module, drive inputs in initial block, observe outputs with $display or
waveform.
4. Signal expected to toggle remains constant in simulation. How to debug?
◦ Check if driving block is triggering. Confirm input stimulus and sensitivity list correctness.
🔹 Clocking and Timing
1. What is a sensitivity list? What is the danger of using `` incorrectly?
◦ Sensitivity list defines triggers. Incorrect @(*) may miss signals, inferring latches.
2. How do you implement a clock divider in Verilog?
◦ Use counter that toggles output clock when threshold reached.
3. Can you use both ** and ** of the same signal in the same always block? Why or why not?
◦ Not allowed for synthesis; simulation may allow but it's unsafe and ambiguous.
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🔹 Advanced (for 2+ yrs experience)
1. How would you do Clock Domain Crossing (CDC)? What are the risks?
◦ Use synchronizer flip-flops or handshaking. Risks: metastability, data loss.
2. Explain `` block and where you’ve used it.
◦ For parameterized code (loops, conditionals). Used in configurable designs (e.g., bus width).
3. Difference between ** and ** via module instantiation?
◦ defparam is older and not recommended. Override via #() is preferred.
4. How would you write reusable and parameterized modules?
module my_adder #(parameter WIDTH=8) (...);
