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Systemc Examples

This document describes SystemC concepts including modules, signals, and FIFO communication between modules. Key concepts covered are: 1) Modules contain processes that operate on signals. Signals can be inputs, outputs, or internal signals and are updated based on sensitivity lists. 2) Clocked signals like clocks drive stimulus and simulation time. Processes can be clocked using sensitivity to the positive edge of a clock signal. 3) FIFO channels allow communication between modules using packet data structures. Modules contain FIFO ports and channels of a set depth are created between ports for blocking communication.

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Frankie Liu
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140 views8 pages

Systemc Examples

This document describes SystemC concepts including modules, signals, and FIFO communication between modules. Key concepts covered are: 1) Modules contain processes that operate on signals. Signals can be inputs, outputs, or internal signals and are updated based on sensitivity lists. 2) Clocked signals like clocks drive stimulus and simulation time. Processes can be clocked using sensitivity to the positive edge of a clock signal. 3) FIFO channels allow communication between modules using packet data structures. Modules contain FIFO ports and channels of a set depth are created between ports for blocking communication.

Uploaded by

Frankie Liu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SYSTEMC

Cpr E 588
RTL Model

Clk

STIM ASig XOR MON


BSig FSig

 DUT Simulation
 Simulation Clock, Stimulus, Monitoring
 Hierarchy
 sc_signal: evaluate – update.
XOR

STIM XOR MON

NAND
ASig FSig
NAND NAND
BSig

NAND

*Constructor without a process.


NAND

SC_MODULE(nand2)
{
sc_in<bool> A, B;
sc_out<bool> F; STIM XOR MON

void do_nand2() {  sc_in: specialized port for


F.write( !(A.read() && B.read()) ); sc_signals.
}  sc_port<sc_signal_in_if<bool
> >

SC_CTOR(nand2) {  sc_signal:
SC_METHOD(do_nand2);  evaluate/update channel, like a
sensitive << A << B; signal in VHDL or reg in Verilog
}  The value do not changes (see
example)
};
 Static ‘sensitivity’: defined at
registration, the only sensitivity
allowed for SC_METHOD
STIM
SC_MODULE(stim)
{
sc_out<bool> A, B;
sc_in<bool> clk;

void StimGen() {
A.write(false);
STIM XOR MON
B.write(false);
wait();
A.write(false);
B.write(true);  Clk: special kind of signal.
wait();  sc_clock
A.write(true); TestClk("TestClock", 10,
B.write(false); SC_NS, 0.5, 1, SC_NS);
wait();
A.write(true);
B.write(true);
 Clock drives the stimulus,
wait(); static sensitivity.
sc_stop();  Stimulus drives the rest of
}
the simulation.
SC_CTOR(stim) {
SC_THREAD(StimGen);  Clocked SC_THREAD
sensitive << clk.pos();
}
};
STIM
SC_MODULE(mon)
{

sc_in<bool> A, B, F;
sc_in<bool> Clk;

void monitor() { STIM XOR MON


cout << setw (10) << "Time";
cout << setw (2) << "A";
cout << setw (2) << "B";
cout << setw (2) << "F" << endl;
 Clocked SC_THREAD
while(true) {
cout << setw (10) <<
sc_time_stamp();  sc_time_stamp: current
cout << setw (2) << A.read();
cout << setw (2) << B.read();
cout << setw (2) << F.read()
simulation time.
<< endl;
wait();
}
}

SC_CTOR(mon) {
SC_THREAD(monitor);
sensitive << Clk.pos();
}
};
FIFO Communication (TLM)

Link_10
Link_01
0 1

Link_03
Ring
Link_30
Network
3 2

*Two FIFOs per link


Node Model
 Port West_out East_in
 sc_fifo_out<packet> Node
east_out; West_in East_out
 Custom data ‘packet’
 FIFO Channel struct packet {
char src;
 sc_fifo<packet>
Link01("Link_01", 1); char dst;
 Depth of 1, blocking char data[2];
communication packet& operator= (const packet& rhs)
{ … };
 Dynamic sensitivity bool operator== (const packet& rhs)
 No sensitivity const { return ( … ) };
 west_out.write(pkt);
 wait( void Print(void)
east_in.data_written_e { … };
vent()); };
 See behavior… ostream& operator<< (ostream& os,
const packet& trans);

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