VERILOG HDL

Hardware Description Language

 Currently, almost all integrated circuits are designed with
using HDL

 Two widely used hardware description languages

— VHDL
— Verilog

 HDL languages can describe circuits from two perspectives

— function
— structure
 Design Specification

Behavioral Description

RTL Description (HDL)

Functional verification and

Testing B

Logic Synthesis

Gate Level Netlist

Logical verification and Testing

Floor planning automatic

place and Route
A
 B A
Physical Layout

Layout Verification

implementation
 Levels of Abstraction-1
Switch Level: Module implemented with
switches and interconnects. Lowest level of
Abstraction

 Gate Level: Module implemented in terms of

logic gates like (and ,or) and interconnection
between gates
 Levels of Abstraction-2
 Dataflow Level: Module designed by specifying dataflow.
The designer is aware of how data flows between
hardware registers and how the data is processed in the
design
 Behavioral Level :Module can be implemented in terms
of the desired design algorithm without concern for the
hardware implementation details. Very similar to C
programming
 Top module

sub block sub block sub block

Leaf Leaf Leaf Leaf Leaf Leaf

cell cell cell cell cell cell

Top down design methodology

 Top module

sub block sub block sub block

Leaf Leaf Leaf Leaf Leaf Leaf

cell cell cell cell cell cell

Bottom Up design methodology

Example
 Module definition
 Modules are the basic building blocks in Verilog. A module
definition starts with the keyword module ends with the
keyword endmodule

module <module_name>(<module terminals list>);

………….
<module internals>
…………..
endmodule

Example:
module adder(sum,a,b);
…..
<functions>
…..
endmodule
 Basic Concepts
 Lexical Conventions
―White space – blank space\b, tabs\t, newline\n
―Comments – one line”\”, multiple line “/*”
―Operators – unary – a = ~b;
binary – a = b&&c;
ternary – a = b ? C : d;
 Number specification
― Sized
― <size>'<baseformat><number>

―Unsized
― <baseformat>
 Negative numbers
— Negative numbers are represented in 2’s complement form
— - 8`d12 // stored as 11110100
— - 6’d3 // 8 bit negative number stored as 2’s complement of 3
— 7’d-2 // illegal specification
 X or Z values

— unknown and high impedance value

— 12’h13x // 12 bit hex number 4 LSB values or unknown
— 16’bz // 16 bit high impedance number
 strings
― enclosed by double space
― “ hello” // is a string
― “a/b” // is a string
Basic concepts 3
3. Data types
 value set – 4 values and 8 strength
Weakest
 NET
― A net declaration starts with keyword wire
……
addr

Processor
wire r_w; // scalar signal

Memory
data
wire [7:0] data; // vector signal
wire [9:0] addr; // vector signal r_w

……
— Selecting a single bit or a portion of vector signals
 data[2] single bit
 data [5:3] 3 bits

― wire a;
― wire b, c;
 Registers
― Registers represent data storage elements. Registers
retain value until another value is placed onto them.
― In Verilog, the term register merely means a variable
that can hold a value.
― Unlike a net, a register does not need a driver.

……
reg done; // scalar signal
reg [7:0] count; // vector signal
……

reg reset; // declare a variable reset that can hold a value

Vectors

― Arrays of Regs and Nets

Integers and Parameters
Module
 GATE LEVEL MODELING
Key words
Example

module fulladder(sum, c_out, a, b, c_in);

output sum, c_out;
input a, b, c_in;
wire s1, c1, s2; // internal nets
xor (s1, a, b); // logic primitives
and (c1, a, b);
xor (sum, s1, c1);
and (s2, s1, c_in);
or (c_out, s2, c1);
endmodule
4 – bit Full Adder
 Gate delays
Rise delay

Fall delay

Turn OFF delay

output – high impedance value
 and #(10) a1(out, a, b); // delay of 10 for all transitions

and #(5,8) a1(out, a, b); // rise delay = 5, fall delay = 8

bufif0 #(4, 5, 6) b1(out, in, control); // rise =4, fall = 5, turn off = 6
module D(out, a, b, c);
// IO ports declarations
output out;
input a, b, c;
// Internal nets
wire e;
// instantiate primitive gates to build the circuit
and #5 (e, a, b);
or #4 (out, e, c);
endmodule
Test bench
◊ Continuous Assignments
 basic statement
 keywords
 assign

 syntax
 left hand side always scalar or vector net
 always active.
 RHS can be registers or nets
 delay values are of time units
 Implicit Continuous Assignment
 instead of declaring net and then wiring both can do as
follows

 Implicit Net Declaration

wire i1, i2;

assign out = i1 & i2;
 Delays
1. Regular Assignment Delay
2. Implicit Continuous Assignment Delay

3. Net Declaration Delay

 Expressions, Operators, and Operands
1. Expressions

2. Operands
3. Operators
- operator types
3.1 Arithmetic Operators
- two types – binary and unary
Binary
- *, /, +, - , %

Unary
- +, - work as unary
3.2 Logical Operator
- logical and (&&), logical or(||), logical not(!)
3.3 Relational Operators
- greater (>), less (<), greater than or equal (>=) and less
than or equal (<=)
// A = 4, B = 3
// X = 4’b1010, Y = 4’b1101, Z = 4’b1xxx

A <= B; // Evaluates to logical 0

A > B; // Evaluates to logical 1
Y >= X; // Evaluates to logical 1
Y < Z; // Evaluates to an x
3.4 Equality Operators
- logical equality (= =), logical inequality (!=)
- case equality (===), case inequality (!==)
3.5 Bitwise Operators
- negation (~), and (&), or (|), xor (^), xnor (~^ or ^~)
- bit by bit operation

// x = 4’b1010, y = 4’b0000
x | y //result is 4’b1010
x || y //result is 1
3.6 Reduction Operators
-and (&), or (|), xor (^), xnor (~^ or ^~), nand (~&),
nor (~|)
- // x = 4’b1010

&x // 1 & 0 & 1 & 0 result is 1’b0

|x //1 | 0 | 1| 0 result is 1’b1
^x // 1 ^ 0 ^ 1 ^ 0 result is 1’b 0
3.7 Shift Operators
- right shift (>>), left shift (<<)
- arithmetic right shift (>>>), arithmetic left shift (<<<)
3.8 Concatenation Operators
- ({ }) append multiple operands
// a =1’b1, b = 2’b00, c = 2’b10, d = 3’b110

y = {b, c}; // result y is 4’b0010

y = {a, b, c, d, 3’b001} // result = 11’b100101100001
y = {a, b[0], c[1]} // 3’b101
3.9 Replication Operators
-{{}}
reg A;
reg [1:0] B, C;
reg [2:0] D;
// A =1’b1, B = 2’b00, C = 2’b10, D = 3’b110

y = { 4{A} }; // y = 4’b1111
y = { 4{A}, 2{B} } // y = 8’b11110000
3.10 Conditional Operators
- condition_expr ? True_expr : false_expr;
- assign addr_bus = driver_enable ? addr_out : 36’bz;
- assign out = control ? In1 : in0;
Condition can be nested
- assign out = (A = = 3) ? (control ? X : Y) : (control ? M : N);
3.11 Operator Precedence
4:1 MUX – method 1
module mux4_1(out, i0, i1, i2, i3, s0, s1);
output out;
input i0, i1, i2, i3;
input s0, s1;
assign out = (~s1 & ~s0 & i0) |
(~s0 & s1 & i1) |
(s0 & ~s1 & i2) |
(s0 & s1 & i3);
endmodule
4:1 MUX – method 2
module mux4_1(out, i0, i1, i2, i3, s0, s1);
output out;
input i0, i1, i2, i3;
input s0, s1;
// using net conditional operator
assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0);
endmodule
 a
x
AND
b

OR
o
c

module cir1 (o, a, b, c); module cir1 (o, a, b, c);

output o; output o;
input a, b, c; input a, b, c;
wire x; wire x = a & b;
assign x = a & b; OR assign o = x | c;
assign o = x | c; endmodule
endmodule
Comparator:
module comparator1 (a, b, c);
input a;
input b;
output c;
assign c = (a == b);
endmodule
4 – Bit Ripple Counter using –ve edged D - FF
Negative edged D -FF
And gate
Test bench Design module
And_in2_test.v And_in2.v

A
In

out
Design Module
module and_in2 (A,B,Q); //declare design module
input A, B; // declare inputs
output Q; // and output
wire Q; // declare output as net
assign Q = A & B; // realize and gate
endmodule
Test Bench Module

`include “and_in2.v” // this is the design file

`time 1ns/100ps // time base is in ns
module and_in2_test; // Declare the Test module
reg A, in; // declare design input as register as we need to hold the inputs
wire out; // declare output as net since we need to interconnect other sub modules,
// should they exist
and_in2 a1( // instantiate the design nodule
// a1 stands for the first instantiation
.A(A), .B(in), .Q(out)); // connect by ports name
initial
begin
A = 0; in = 0; // apply time stimulus at time 0
#20 A = 0; in = 1; // change input at time 20ns
#20 A = 1; in = 0; //40ns
#20 A = 1; in = 1; //60ns
#20 $stop;
$finish;
end
endmodule
Test Bench Module

`include “and_in2.v” // this is the design file

`time 1ns/100ps // time base is in ns
module and_in2_test; // Declare the Test module
reg A, in; // declare design input as register as we need to hold the inputs
wire out; // declare output as net since we need to interconnect other sub modules,
// should they exist
and_in2 a1( // instantiate the design nodule
// a1 stands for the first instantiation
.A(A), .B(in), .Q(out)); // connect by ports name
initial
begin
A = 0; in = 0; // apply time stimulus at time 0
A = 0; in = 1;
A = 1; in = 0;
A = 1; in = 1;
$stop;
$finish;
end
endmodule