Final Test

100 Marks

PART -A 40 Marks

Digital (12 Marks)

1. Construct a 10-to-1 multiplexer with minimum number of 4-to-1 multiplexers.
-- 3 Marks
2. Design a digital circuit to get the sequence 0,160,128,32,128,48,80,0,160,128,...

-- 6 Marks

3. Create 2^4 ×4 RAM from 2^2×4 RAM chips.

-- 3 Marks

Verilog (12 Marks)

1. Write a synthesizable RTL code for priority encoder -- 4 Marks
2. Display the batch mode output for the following:

-- 4 Marks
module strobe;
reg a ;
initial
begin
$monitor($time,"Value of a monitored = %d",a);
$strobe($time,"Value of a strobed = %d",a);
a = 0;
a <= 1;
$display($time,"Value of a displayed = %d",a);
#1;
a = 1'bx;
end
endmodule

3. Draw the waveform for the following code.

-- 4 Marks
module test( );
reg rst, data, clk;
parameter cycle = 10, Thold = 2, Tsetup = 2;

task apply_data;
begin
rst <= 1'b0; data <= 1'b1;
@(posedge clk);
#(Thold);
{rst,data} <= 2'bxx;
#(cycle-Thold-Tsetup);
end
 endtask

initial
begin
clk = 1'b0;
forever
#cycle clk = ~ clk;
end

initial
begin
rst = 1'b1;
repeat (2)
@ (posedge clk);
repeat (2)
apply_data ();
$stop;
end
endmodule

Verification (16 Marks)

1. In the below code, how many bins will be created? Calculate the coverage?
-- 4 Marks
module test;
class example;
bit [0:2] y;
bit z;
covergroup cg;
CP_Y : coverpoint y
{ option.auto_bin_max = 4 ; }
CP_Z : coverpoint z;
Y X Z : cross CP_Y, CP_Z;
endgroup
function new();
cg=new();
endfunction
endclass

example e_h=new();
initial
begin
for( int i=0; i< 5; i++)
begin
e_h.y= i;
e_h.z= ~e_h.z;
e_h. cg.sample;
end
end

endmodule

2. Refer the below picture and write assertions for the following conditions.
-- 4 Marks
a. When PSEL is asserted, after one clock cycle PENABLE should be asserted
 b. When PENABLE is asserted, it should be held high till PREADY is high

3. What is the bug in the following snippet of code? And what is the correct way?
-- 4 Marks
class packet;
rand int addr, data;
endclass

class generator;
packet pkt;
//Generator to Scoreboard Mailbox
mailbox#(packet) gen2sb;
function new();
gen2sb = new;
endfunction

task gen_packet;
pkt = new();
repeat(100)
begin
pkt.randomize();
gen2sb.put(pkt)
end
endtask
endclass
 4. For the following architecture, write snippets of code for following instructions in the
proper phases: Do not use configuration class, Set and get individually using config db.
-- 4 Marks
a. Set no_agents to 2 in test and get it in env .
b. Make agent1 to active agent in test.[Note: is_active= 0 : passive, is_active=1:
active];
c. Make agent 2 to passive agent in test.
d. Get the above set values in corresponding components.

Test
Env

int no_agents;

Agent1 Agent2
bit is_active; bit is_active;

PART - B 40 Marks

Digital (12 Marks)

4. Design a combinational circuit to find 2’s complement of a given 8 bit input by using only
logic gates. Note that adder circuit should not be used. -- 6 Marks

5. Design a overlapping Moore type FSM (Finite State Machine) to detect more than one "1"s
in last 3 samples. -- 6 Marks
For example: If the input sampled at clock edges is 0 1 0 1 0 1 1 0 0 1
then output should be 0 0 0 1 0 1 1 1 0 0
Verilog (12Marks)
1. Write RTL code for designing a 10bit SIPO right shift register such that:
-- 6 Marks
a. Serial input “din” is shifted at 1250MHZ (system clock) frequency.
b. The 10bit parallel output “dout” will be latched only at a clock frequency of
125MHZ(derived clock).
c. Clock is an active high signal with active low synchronous reset.
d. P.S : There is only one synchronous clock domain .

2. Write Verilog Testbench model in order to perform the following FILE READ operation:
-- 6 Marks
a. seed_input.txt is the external file to be read whose path is ../sim/seed_input.txt.
b. File has the following contents
@1
123a
c. The data value read from the file at @1 has to be used as a seed parameter for
randomizing an integer variable “var”.

Verification (16 Marks)

1. Write code to generate both waddr and raddr values in between 10 to 20 for the below
transaction class and start both the sequences inside virtual sequence by showing all
connections between sub sequencer & virtual sequencer. (Note: both write and read
drivers should drive the data at the same time) -- 6 Marks

class write_xtn extends uvm_sequence_item;

`uvm_object_utils(write_xtn)
function new(string name);
super.new(name);
endfunction
rand int waddr;
endclass

class read_xtn extends uvm_sequence_item;

`uvm_object_utils(read_xtn)
function new(string name);
super.new(name);
endfunction
rand int raddr;
endclass
2. Define transaction for the minute counter with valid constraints.(When one_min is high
the inputs get loaded & when low the counter should start counting and counter works in
12 hour format)
-- 6 Marks

3. What is the default size of the mailbox, how to restrict the size of the mailbox? Explain
with a snippet of code, how to connect two transactors using mailbox. -- 4 Marks

PART – C(CMOS,FPGA,STA,Basic Electronics) 20 Marks

1. Draw a divide by 2 circuit using D FF. What is the maximum clock frequency at which
you can operate the circuit, given that Setup and hold times of the FF are 5 ns and 2 ns
respectively. The propagation delay of the FF can vary between 1 ns and 10 ns. Assume
that the net delay is 0.5ns. -- 4 Marks

2. Draw the waveform for the following circuit. -- 4 Marks

3. Define a LUT4. Draw the FPGA schematic for the Boolean equation y = a&b&c&f.
-- 4 Marks

4. Implement f(a,b,c)=(a’+b’)c using CMOS -- 4 Marks

5. Find V0 in the circuit of Fig. using Thevenin’s theorem.

-- 4 Marks