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329 views6 pages

Maven

Uploaded by

hemadri.vadhiraja19
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Design Test

www.maven-silicon.com
VLSI Training Services
Setting standards in VLSI Design

Maven Silicon Confidential


All the presentations, books, documents [hard copies and soft copies] labs
and projects [source code] that you are using and developing as part of the training
course are the proprietary work of Maven Silicon and it is fully protected under
copyright and trade secret laws. You may not view, use, disclose, copy, or
distribute the materials or any information except pursuant to a valid written
license from Maven Silicon

Copyright © 2024 Maven Silicon 2


www.maven-silicon.com
VLSI Training Services
Setting standards in VLSI Design

Part- 1: Digital (25 Marks)


1. Design a circuit to perform the following operation using only four 2x1 Multiplexers.
(5M)

Control Input Operation


0 Half Adder
1 Half Subtractor

Inputs : 2-Data inputs 1-control input


Outputs : 2 - outputs

2. Design a sequential circuit that cuts the every second pulse from the input (clk) and
produce the output as shown below. (4M)

Clk (in)

Clk (out)

3. A binary ripple counter is required to count up to 16,383. If the clock frequency is


8.192MHz, determine the number of flip-flops needed and the output frequency.
(3M)

4. (135)12= (X)8+(78)9. Solve X (3M)

Copyright © 2024 Maven Silicon 3


www.maven-silicon.com
VLSI Training Services
Setting standards in VLSI Design

5. The below given digital circuit has 3 D-flipflop. Initially Y2Y1Y0 = 111. What is the
sequence for Y0Y1Y2 at the 237th clock cycle? (3M)

4. Design a sequence detector to detect a sequence “11011”. Use D flip flop to design
(7M)

Copyright © 2024 Maven Silicon 4


www.maven-silicon.com
VLSI Training Services
Setting standards in VLSI Design

Part- 2: Verilog (25 Marks)

1. Write down the batch mode output of the below given verilog snippet. (5M)

module monitor_check();

reg [2:0]a,b,c;
initial
begin
a = 3'b000;
#5 a = 3'b010;
#10;
$monitoroff;
a = 3'b011;
#10;
#5 a = 3'b101;
$monitoron;
#5 a = #7 3'b111;
b <= #3 3’b110;
#1 c <= #2 3’b001;
end

initial
$monitor ($time," a= %b,b= %b,c=%b",a,b,c);

endmodule

2. Draw waveform for the below given snippet. (5M)

module delays();

reg clk;
reg a;
reg b;

initial
begin
clk = 1'b0;
forever #6 clk = ~clk;
end

initial
begin
a = 0;
Copyright © 2024 Maven Silicon 5
www.maven-silicon.com
VLSI Training Services
Setting standards in VLSI Design

b = 0;
end

always @(posedge clk)


begin
#4 a = 1;
#6 b = a;
end
endmodule
3. Write an RTL for a counter that generates an arbitrary sequence 0,4,5,2, 1 and repeats the
sequence. (5M)

4. Design a sequence detector that will detect a sequence “1001” (10M)

[A] Draw the Moore overlapping sequence. (2M)


[B] Write the RTL code for the design. (4M)
[C] Write the TB to verify the design. (4M)

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