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module rand_methods;
initial
begin
randvar pkt;
pkt = new();
pkt.randomize();
b.
class randvar;
rand bit [7:0] var1, var2, var3, var4;
endclass
module rand_methods;
initial
begin
randvar pkt;
pkt = new();
pkt.var1.rand_mode(0);
pkt.var3.rand_mode(0);
pkt.var4.rand_mode(0);
pkt.randomize();
c.
class randvar;
rand bit [7:0] var1, var2, var3, var4;
endclass
module rand_methods;
initial
begin
randvar pkt;
pkt = new();
pkt.var2.rand_mode(0);
pkt.var3.rand_mode(0);
pkt.randomize();
d.
class randvar;
rand bit [7:0] var1, var2, var3, var4;
endclass
module rand_methods;
initial
begin
randvar pkt;
pkt = new();
pkt.var2.rand_mode(0);
pkt.randomize();
2. There are two constraints applied to same variable ‘A’. One will generate
the value within the range of [25:50] and another expression say variable
value should be greater than 40. What should be the value generated, and
what is the reason?
class packet;
rand bit [8:0] val;
module constr_inside;
initial
begin
packet pkt;
pkt = new();
repeat(3)
begin
pkt.randomize();
$display("\t VALUE = %0d",pkt.val);
end
end
endmodule
3. Write a single constraint to generate random values for bit [8:0] variable
in the below range, 1-34, 127, 129-156, 192-202,257-260.
class packet;
rand bit [8:0] val;
constraint c1_range { val inside {[1:34], 127, [129:156],
[192:202],[257:260]}; }
endclass
module constr_inside;
initial
begin
packet pkt;
pkt = new();
repeat(10)
begin
pkt.randomize();
$display("\t VALUE = %0d",pkt.val);
end
end
endmodule
class packet;
rand bit [8:0] val;
constraint c1_range { val > 34; }
constraint c2_range { val < 43; }
endclass
module constr_inside;
initial
begin
packet pkt;
pkt = new();
repeat (10)
begin
pkt.randomize();
$display("\t VALUE = %0d", pkt.val);
end
end
endmodule
class packet;
rand bit [8:0] val;
constraint c1_range { val > 34; }
constraint c2_range { val < 43; }
module constr_inside;
initial
begin
packet pkt;
pkt = new();
repeat (10)
begin
pkt.randomize();
$display("\t VALUE = %0d", pkt.val);
end
end
endmodule
class packet;
rand bit [7:0] var1;
rand bit [7:0] var2;
constraint c1_range { var1 inside {[0:50]}; }
constraint c2_range { unique {var2}; }
endclass
module constr_inside;
initial
begin
packet pkt;
pkt = new();
repeat(10)
begin
pkt.randomize();
$display("\t VAR1 = %0d \t VAR2 = %0d",pkt.var1,pkt.var2);
end
end
endmodule
module test;
int unsigned a[10];
initial
begin
foreach (a[i])
begin
a[i] = i*i;
end
a.shuffle();
$display("a = %p",a);
end
endmodule
module foreach_constraint;
packet pkt = new(); initial
begin
repeat (15)
begin
assert(pkt.randomize());
$display("\nThe size of the array is %0d",pkt.array.size());
$display("Elements of the array = %0p",pkt.array);
end
end
endmodule
class packet;
rand logic a;
rand logic b;
function void post_randomize();
b = $urandom_range(0,1);
if (b)
a = a ? 'x : 'z;
endfunction
endclass
module test;
initial
begin
packet pkt = new;
repeat (10)
begin
pkt.randomize();
$display(pkt.a);
end
end
endmodule
class addr2power;
rand bit[7:0] addr;
randc bit[2:0] add2;
constraint ADDR { addr == 2**add2; }
endclass
module test;
initial
begin
addr2power addr_pow;
addr_pow = new();
repeat(10)
begin
addr_pow.randomize();
$display("%0d", addr_pow.addr);
end
end
endmodule
11.Having 32-bit of variable, only single bit high values need to be accessed.
Write a constraint for that.
class abc;
rand bit [31:0] var1;
rand bit [31:0] c1;
module bb();
abc ab_h;
initial
begin
ab_h = new();
repeat(10)
begin
ab_h.randomize();
$display("values are %0d %b",ab_h.c1,ab_h.c1);
end
end
endmodule
12.Write a constraint with array size 5 to 10 values & the array values should
be in ascending order/descending order.
class packet;
rand bit [7:0] b[];
constraint abc1 {b.size() inside {[5:10]};}
constraint odd_even_2 {
foreach(b[i])
if (i % 2 == 0)
b[i] % 2 != 0;
else
b[i] % 2 == 0;
}
endclass
module test;
packet v;
initial
begin
v = new;
repeat (10)
begin
v.randomize();
$display("%p",v.b);
end
end
endmodule
class packet;
rand bit[7:0] b[];
constraint abc1 { b.size() inside {[2:10]}; }
constraint odd { foreach (b[i]) {
b[i] inside {[10:30]};
b[i] % 2 != 0; }
}
endclass
module test;
packet v;
initial
begin
v = new();
repeat(2)
begin
v.randomize();
$display("%p", v.b);
end
end
endmodule
module test;
class prime_number;
rand bit [8:0] a[$];
constraint abc {a.size==100; }
constraint cba { foreach(a[i])
if(i>1 )
a[i] == prime(i);
else a[i] == 2;}
prime_number pri;
initial
begin
pri=new;
void'(pri.randomize);
foreach(pri.a[i])
$display("%d",pri.a[i]);
end
endmodule
15.How can we generate the factorial of the first 5 even numbers using
constraints in SystemVerilog?
class factt;
rand int num[];
constraint size {num.size == 5;}
constraint fact_num {
foreach (num[i])
num[i] == fact((i + 1) * 2);
}
function int fact(int j);
if (j == 0)
fact = 1;
else
fact = j * fact(j - 1);
endfunction
endclass
module factorial;
factt f = new();
initial
begin
assert(f.randomize); // Randomize the values of the class
constraints
$display("%p", f.num); // Display the generated factorials of even
numbers
end
endmodule
16.Write a code that generates a random number between 1.35 to 2.57 using
SystemVerilog
module tb;
class real_num;
rand int r_num[];
real num[10];
foreach (r_num[i])
r_num[i] inside {[1350:2570]};
}
function void post_randomize();
foreach (num[i])
begin
num[i] = r_num[i] / 1000.0;
$display("Number = %f", num[i]);
end
endfunction
endclass
real_num rn = new();
initial
begin
rn.randomize();
end
endmodule
class packet;
rand int a[];
constraint size { a.size() == 10; }
constraint pattern {
foreach (a[i]) {
if (i < 5)
a[i] == 10 - ((i * 2) + 1); // 9, 7, 5, 3, 1
else
a[i] == 18 - (i * 2); // 8, 6, 4, 2, 0
}
}
endclass
module tb;
initial
begin
packet pkt = new(); // create an instance of packet class
assert(pkt.randomize()); // randomize the packet
$display("OUTPUT = %p", pkt.a); // print the generated pattern
end
endmodule
18. Can you provide a code example of how to use constraints to access a
single bit of a 16-bit variable? For instance, how can you generate 16- bit
numbers with only a single bit set, such as 4, 8, or 16, using constraints?
class abc;
rand bit [31:0] var1;
rand bit [31:0] c1;
constraint c2{ $onehot(c1)==1;}
endclass
module bb();
abc ab_h;
initial
begin
repeat(10)
begin
ab_h = new();
ab_h.randomize();
$display("values are %0d %b", ab_h.c1, ab_h.c1);
end
end
endmodule
class packet;
rand bit [61:0] num;
constraint abc {
foreach(num[i])
if(i>=0&&i<32)
num[i]==1'b1;
else if(i>31&&i<62)
num[i]==1'b0;
}
function void post_randomize();
$display("num= %d %b",num, num);
endfunction
endclass
module test;
packet v;
initial
begin
v=new;
v.randomize();
end
endmodule
class packet;
rand bit a;
static bit b = 0;
constraint abc { a != b; }
module test;
packet v;
initial
begin
v = new;
repeat (10)
begin
v.randomize();
end
end
endmodule
class packet;
randc bit[31:0] a;
constraint abc {foreach (a[i])
{if (i != 12)
a[i] inside {0, 1};
else
a[i] == 0;
}
}
function void post_randomize();
$display("a= %b", a);
endfunction
endclass
module test;
packet v;
initial
begin
v = new();
repeat (10)
begin
v.randomize();
$display("a= %d a=%b", v.a, v.a);
end
end
endmodule
22.How can you define a constraint in System Verilog to ensure that even
locations in a random array contain odd numbers, and odd locations
contain even numbers?
class a;
rand bit[3:0] k[];
module test;
initial
begin
a a1 = new();
repeat (5)
begin
assert(a1.randomize());
foreach (a1.k[i])
$display(" The location = %0d\t value = %0d", i, a1.k[i]);
end
end
endmodule
class cons;
rand int a[];
constraint x{a.size==10;}
constraint y{foreach(a[i])
if(i<5)
a[i]==i+1;
else
a[i]==10-i;}
cons c;
module top;
initial
begin
c=new();
assert(c.randomize());
end
endmodule
class cons;
rand int a[];
constraint x{a.size==7;}
constraint y{foreach(a[i])
a[i]==(i*10)+9;}
function void post_randomize();
$display("Required pattern is %0p",a);
endfunction
endclass
cons c;
module top;
initial
begin
c=new();
assert(c.randomize());
end
endmodule
class cons;
rand int even[];
constraint range{even.size==51;}
constraint x{foreach(even[i])
even[i] inside {[50:100]};}
constraint y{foreach(even[i])
even[i]%2==0;}
cons c;
module top;
initial
begin
c=new();
assert(c.randomize());
end
endmodule
26.Write a constraint for a 32 bit rand variable such that it should have 12
number of 1's non consecutively
class cons;
rand bit [31:0]a;
constraint no_of_ones{$countones(a)==12;}
//We can use constraint no_of_ones{$countbits(a,1)==12;}
constraint x{foreach(a[i])
if(i>0&&a[i]==1)
a[i]!=a[i-1];}
cons c;
module test;
initial
begin
c=new;
c.randomize;
end
endmodule
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