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Constraints

The document provides a comprehensive guide on VLSI training services offered by Maven Silicon, focusing on randomization and constraints in SystemVerilog. It includes various code examples demonstrating how to implement randomization techniques, define constraints, and generate specific patterns and values. Additionally, it emphasizes the proprietary nature of the training materials and the legal protections in place.

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0% found this document useful (0 votes)
37 views33 pages

Constraints

The document provides a comprehensive guide on VLSI training services offered by Maven Silicon, focusing on randomization and constraints in SystemVerilog. It includes various code examples demonstrating how to implement randomization techniques, define constraints, and generate specific patterns and values. Additionally, it emphasizes the proprietary nature of the training materials and the legal protections in place.

Uploaded by

20501a0404
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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www.maven-silicon.

com
VLSI Training Services
Setting standards in VLSI Design

Maven Silicon Confidential


All the presentations, books, documents [hard copies and soft copies] labs
and projects [source code] that you are using and developing as part of the training
course are the proprietary work of Maven Silicon and it is fully protected under
copyright and trade secret laws. You may not view, use, disclose, copy, or
distribute the materials or any information except pursuant to a valid written
license from Maven Silicon

Copyright © 2023 Maven Silicon 2


www.maven-silicon.com
VLSI Training Services
Setting standards in VLSI Design

Randomisation and Constraints


1. Randomize the below variable such as
class randvar;
rand bit [7:0] var1, var2, var3, var4;
endclass
a. Randomize all variable.
b. Randomize only var2
c. Randomize var1, var4.
d. Randomize var1, var3, var4.
a.
class randvar;
rand bit [7:0] var1, var2, var3, var4;
endclass

module rand_methods;
initial
begin
randvar pkt;
pkt = new();
pkt.randomize();

$display("\t VAR1 = %0d \t VAR2 = %0d \t VAR3 = %0d \t VAR4 = %0d


",pkt.var1, pkt.var2, pkt.var3, pkt.var4);
end
endmodule

b.
class randvar;
rand bit [7:0] var1, var2, var3, var4;
endclass

module rand_methods;
initial
begin
randvar pkt;
pkt = new();
pkt.var1.rand_mode(0);
pkt.var3.rand_mode(0);
pkt.var4.rand_mode(0);

pkt.randomize();

$display("\t VAR1 = %0d \t VAR2 = %0d \t VAR3 = %0d \t VAR4 = %0d


",pkt.var1, pkt.var2, pkt.var3, pkt.var4);
end
endmodule

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Setting standards in VLSI Design

c.
class randvar;
rand bit [7:0] var1, var2, var3, var4;
endclass

module rand_methods;
initial
begin
randvar pkt;
pkt = new();
pkt.var2.rand_mode(0);
pkt.var3.rand_mode(0);

pkt.randomize();

$display("\t VAR1 = %0d \t VAR2 = %0d \t VAR3 = %0d \t VAR4 = %0d


",pkt.var1, pkt.var2, pkt.var3, pkt.var4);
end
endmodule

d.
class randvar;
rand bit [7:0] var1, var2, var3, var4;
endclass

module rand_methods;
initial
begin
randvar pkt;
pkt = new();
pkt.var2.rand_mode(0);

pkt.randomize();

$display("\t VAR1 = %0d \t VAR2 = %0d \t VAR3 = %0d \t VAR4 = %0d


",pkt.var1, pkt.var2, pkt.var3, pkt.var4);
end
endmodule

Copyright © 2023 Maven Silicon 4


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VLSI Training Services
Setting standards in VLSI Design

2. There are two constraints applied to same variable ‘A’. One will generate
the value within the range of [25:50] and another expression say variable
value should be greater than 40. What should be the value generated, and
what is the reason?

class packet;
rand bit [8:0] val;

constraint c1_range { val inside {[25:50]}; }


constraint c2 { val > 40;}
endclass

module constr_inside;
initial
begin
packet pkt;
pkt = new();

repeat(3)
begin
pkt.randomize();
$display("\t VALUE = %0d",pkt.val);
end
end
endmodule

Copyright © 2023 Maven Silicon 5


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VLSI Training Services
Setting standards in VLSI Design

3. Write a single constraint to generate random values for bit [8:0] variable
in the below range, 1-34, 127, 129-156, 192-202,257-260.

class packet;
rand bit [8:0] val;
constraint c1_range { val inside {[1:34], 127, [129:156],
[192:202],[257:260]}; }
endclass

module constr_inside;
initial
begin
packet pkt;
pkt = new();
repeat(10)
begin
pkt.randomize();
$display("\t VALUE = %0d",pkt.val);
end
end
endmodule

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Setting standards in VLSI Design

4. Write a constraint without an inside function to generate random values


within the range of 34 to 43?

class packet;
rand bit [8:0] val;
constraint c1_range { val > 34; }
constraint c2_range { val < 43; }
endclass

module constr_inside;
initial
begin
packet pkt;
pkt = new();

repeat (10)
begin
pkt.randomize();
$display("\t VALUE = %0d", pkt.val);
end
end
endmodule

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Setting standards in VLSI Design

5. Write a constraint without an inside function to generate random values


within the range of 34 to 43?

class packet;
rand bit [8:0] val;
constraint c1_range { val > 34; }
constraint c2_range { val < 43; }

module constr_inside;
initial
begin
packet pkt;
pkt = new();
repeat (10)
begin
pkt.randomize();
$display("\t VALUE = %0d", pkt.val);
end
end
endmodule

Copyright © 2023 Maven Silicon 8


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VLSI Training Services
Setting standards in VLSI Design

6. Write a constraint to generate a random value for a var1 [7:0] within50


and var2 [7:0] with the non-repeated value in every randomization?

class packet;
rand bit [7:0] var1;
rand bit [7:0] var2;
constraint c1_range { var1 inside {[0:50]}; }
constraint c2_range { unique {var2}; }
endclass

module constr_inside;
initial
begin
packet pkt;
pkt = new();
repeat(10)
begin
pkt.randomize();
$display("\t VAR1 = %0d \t VAR2 = %0d",pkt.var1,pkt.var2);
end
end
endmodule

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Setting standards in VLSI Design

7. Without using randomization method or rand


keyword(modifiers),generate an array of unique values.

module test;
int unsigned a[10];
initial
begin
foreach (a[i])
begin
a[i] = i*i;
end
a.shuffle();

$display("a = %p",a);
end
endmodule

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Setting standards in VLSI Design

8. Generate unique elements in an array without using the keyword unique.


class packet;
rand bit [5:0] array[];
randc int c;
constraint size_array {c inside {[4:20]}; array.size == c;}
constraint elements {foreach (array[i]) array[i] inside {[0:64]};}
constraint abc {foreach(array[i])
foreach(array[j])
if (i!=j)
array[i]!=array[j];}
endclass: packet

module foreach_constraint;
packet pkt = new(); initial
begin
repeat (15)
begin
assert(pkt.randomize());
$display("\nThe size of the array is %0d",pkt.array.size());
$display("Elements of the array = %0p",pkt.array);
end
end
endmodule

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Setting standards in VLSI Design

9. Write a constraint to generate 0, 1, x and z randomly.

class packet;
rand logic a;
rand logic b;
function void post_randomize();
b = $urandom_range(0,1);
if (b)
a = a ? 'x : 'z;
endfunction
endclass

module test;
initial
begin
packet pkt = new;
repeat (10)
begin
pkt.randomize();
$display(pkt.a);
end
end
endmodule

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Setting standards in VLSI Design

10.Write a constraint to generate multiples of power 2.

class addr2power;
rand bit[7:0] addr;
randc bit[2:0] add2;
constraint ADDR { addr == 2**add2; }
endclass

module test;

initial
begin
addr2power addr_pow;
addr_pow = new();
repeat(10)
begin
addr_pow.randomize();
$display("%0d", addr_pow.addr);
end
end
endmodule

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Setting standards in VLSI Design

11.Having 32-bit of variable, only single bit high values need to be accessed.
Write a constraint for that.

class abc;
rand bit [31:0] var1;
rand bit [31:0] c1;

constraint c2{ $countones(c1)==1;}


endclass

module bb();
abc ab_h;
initial
begin
ab_h = new();
repeat(10)
begin
ab_h.randomize();
$display("values are %0d %b",ab_h.c1,ab_h.c1);
end
end
endmodule

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Setting standards in VLSI Design

12.Write a constraint with array size 5 to 10 values & the array values should
be in ascending order/descending order.
class packet;
rand bit [7:0] b[];
constraint abc1 {b.size() inside {[5:10]};}
constraint odd_even_2 {
foreach(b[i])
if (i % 2 == 0)
b[i] % 2 != 0;
else
b[i] % 2 == 0;
}
endclass

module test;
packet v;
initial
begin
v = new;
repeat (10)
begin
v.randomize();
$display("%p",v.b);
end
end
endmodule

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Setting standards in VLSI Design

13.Declare dynamic array size to be between 2 to 10. Generate odd numbers


in it within the range of 10 to 30 using SV constraint.

class packet;
rand bit[7:0] b[];
constraint abc1 { b.size() inside {[2:10]}; }
constraint odd { foreach (b[i]) {
b[i] inside {[10:30]};
b[i] % 2 != 0; }
}
endclass
module test;
packet v;
initial
begin
v = new();
repeat(2)
begin
v.randomize();
$display("%p", v.b);
end
end
endmodule

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Setting standards in VLSI Design

14.Write a constraint to generate prime numbers between the range of 1 to


100.

module test;
class prime_number;
rand bit [8:0] a[$];
constraint abc {a.size==100; }
constraint cba { foreach(a[i])
if(i>1 )
a[i] == prime(i);
else a[i] == 2;}

function int prime( int g);


for(int i=2;i<g;i++)
if(g%i==0)
return 2; //if it is not a prime number ,returning 2 which
is one of prime
return g;
endfunction
function void post_randomize();
a=a.unique;
endfunction
endclass

prime_number pri;

initial
begin
pri=new;
void'(pri.randomize);
foreach(pri.a[i])
$display("%d",pri.a[i]);
end
endmodule

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Setting standards in VLSI Design

15.How can we generate the factorial of the first 5 even numbers using
constraints in SystemVerilog?

class factt;
rand int num[];
constraint size {num.size == 5;}
constraint fact_num {
foreach (num[i])
num[i] == fact((i + 1) * 2);
}
function int fact(int j);
if (j == 0)
fact = 1;
else
fact = j * fact(j - 1);
endfunction
endclass

module factorial;
factt f = new();
initial
begin
assert(f.randomize); // Randomize the values of the class
constraints
$display("%p", f.num); // Display the generated factorials of even
numbers
end
endmodule

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Setting standards in VLSI Design

16.Write a code that generates a random number between 1.35 to 2.57 using
SystemVerilog

module tb;
class real_num;
rand int r_num[];
real num[10];

constraint size1 { r_num.size == 10; }


constraint real_num {

foreach (r_num[i])
r_num[i] inside {[1350:2570]};
}
function void post_randomize();
foreach (num[i])
begin
num[i] = r_num[i] / 1000.0;
$display("Number = %f", num[i]);
end
endfunction
endclass

real_num rn = new();

initial
begin
rn.randomize();
end
endmodule

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Setting standards in VLSI Design

17.What is the constraint to generate the pattern 9 7 5 3 1 8 6 4 2 0 ?

class packet;
rand int a[];
constraint size { a.size() == 10; }
constraint pattern {
foreach (a[i]) {
if (i < 5)
a[i] == 10 - ((i * 2) + 1); // 9, 7, 5, 3, 1
else
a[i] == 18 - (i * 2); // 8, 6, 4, 2, 0
}
}
endclass
module tb;
initial
begin
packet pkt = new(); // create an instance of packet class
assert(pkt.randomize()); // randomize the packet
$display("OUTPUT = %p", pkt.a); // print the generated pattern
end
endmodule

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Setting standards in VLSI Design

18. Can you provide a code example of how to use constraints to access a
single bit of a 16-bit variable? For instance, how can you generate 16- bit
numbers with only a single bit set, such as 4, 8, or 16, using constraints?

class abc;
rand bit [31:0] var1;
rand bit [31:0] c1;
constraint c2{ $onehot(c1)==1;}
endclass

module bb();
abc ab_h;
initial
begin
repeat(10)
begin
ab_h = new();
ab_h.randomize();
$display("values are %0d %b", ab_h.c1, ab_h.c1);
end
end
endmodule

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Setting standards in VLSI Design

19.Write a constraint to generate a variable with 0-31 bits should be 1, 32-61


bits should be 0

class packet;
rand bit [61:0] num;
constraint abc {
foreach(num[i])
if(i>=0&&i<32)
num[i]==1'b1;
else if(i>31&&i<62)
num[i]==1'b0;
}
function void post_randomize();
$display("num= %d %b",num, num);
endfunction
endclass
module test;
packet v;
initial
begin
v=new;
v.randomize();
end
endmodule

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20.How to generate a sequence of 10 random single-bit values that alternate


between 0 and 1 like 101010101010?

class packet;
rand bit a;
static bit b = 0;
constraint abc { a != b; }

function void post_randomize();


$display("a=%d, b=%d", a, b);
b = a;
endfunction
endclass

module test;
packet v;
initial
begin
v = new;
repeat (10)
begin
v.randomize();
end
end
endmodule

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21.Write a SystemVerilog program to randomize a 32-bit variable, but only


randomize the 12th bit.

class packet;
randc bit[31:0] a;
constraint abc {foreach (a[i])
{if (i != 12)
a[i] inside {0, 1};
else
a[i] == 0;
}
}
function void post_randomize();
$display("a= %b", a);
endfunction
endclass
module test;
packet v;
initial
begin
v = new();
repeat (10)
begin
v.randomize();
$display("a= %d a=%b", v.a, v.a);
end
end
endmodule

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Setting standards in VLSI Design

22.How can you define a constraint in System Verilog to ensure that even
locations in a random array contain odd numbers, and odd locations
contain even numbers?

class a;
rand bit[3:0] k[];

constraint b {k.size() inside {[4:20]};}

constraint c { foreach (k[i])


{ if (i % 2 == 0) // even location
k[i] % 2 == 1; // odd number
else if (i % 2 == 1) // odd location
k[i] % 2 == 0; // even number
}
}
endclass

module test;
initial
begin
a a1 = new();
repeat (5)
begin
assert(a1.randomize());
foreach (a1.k[i])
$display(" The location = %0d\t value = %0d", i, a1.k[i]);
end
end
endmodule

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23.Write a constraint to generate below pattern 1234554321

class cons;
rand int a[];
constraint x{a.size==10;}
constraint y{foreach(a[i])
if(i<5)
a[i]==i+1;
else
a[i]==10-i;}

function void post_randomize();


$display("Randomized data is %0p",a);
endfunction
endclass

cons c;
module top;
initial
begin
c=new();
assert(c.randomize());
end
endmodule

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24.Write a constraint to generate below pattern 9 19 29 39 49 59 69 79

class cons;
rand int a[];
constraint x{a.size==7;}
constraint y{foreach(a[i])
a[i]==(i*10)+9;}
function void post_randomize();
$display("Required pattern is %0p",a);
endfunction
endclass

cons c;
module top;
initial
begin
c=new();
assert(c.randomize());
end
endmodule

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Setting standards in VLSI Design

25.Write a constraint to generate a random even number between 50 and


100

class cons;
rand int even[];
constraint range{even.size==51;}
constraint x{foreach(even[i])
even[i] inside {[50:100]};}
constraint y{foreach(even[i])
even[i]%2==0;}

function void post_randomize();


$display("Random even numbers between 50 and 100 are:\n %0p",even);
endfunction
endclass

cons c;
module top;
initial
begin
c=new();
assert(c.randomize());
end
endmodule

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Setting standards in VLSI Design

26.Write a constraint for a 32 bit rand variable such that it should have 12
number of 1's non consecutively

class cons;
rand bit [31:0]a;
constraint no_of_ones{$countones(a)==12;}
//We can use constraint no_of_ones{$countbits(a,1)==12;}
constraint x{foreach(a[i])
if(i>0&&a[i]==1)
a[i]!=a[i-1];}

function void post_randomize();


$display("Randomized 32 bit variable having 12 ones is:%0b",a);
$display("Displaying no of ones in the variable that we randomized
is %0d",$countones(a));
endfunction
endclass

cons c;
module test;
initial
begin
c=new;
c.randomize;
end
endmodule

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VLSI Training Services
Setting standards in VLSI Design

Copyright © 2023 Maven Silicon 30


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VLSI Training Services
Setting standards in VLSI Design

www.maven-silicon.com

Maven Silicon Confidential


All the presentations, books, documents [hard copies and soft copies] labs
and projects [source code] that you are using and developing as part of the training
course are the proprietary work of Maven Silicon and it is fully protected under
copyright and trade secret laws. You may not view, use, disclose, copy, or
distribute the materials or any information except pursuant to a valid written
license from Maven Silicon

Copyright © 2023 Maven Silicon 31


www.maven-silicon.com
VLSI Training Services
Setting standards in VLSI Design

Randomization and Constraints


1. Randomize the below variable such as
class randvar;
rand bit [7:0] var1, var2, var3, var4;
endclass
a. Randomize all variable.
b. Randomize only var2
c. Randomize var1, var4.
d. Randomize var1, var3, var4.
2. There are two constraints applied to same variable ‘A’. One will generate
the value within the range of [25:50] and another expression say variable
value should be greater than 40. What should be the value generated, and
what is the reason?
3. Write a single constraint to generate random values for bit [8:0] variable
in the below range, 1-34, 127, 129-156, 192-202,257-260.
4. Write a constraint without an inside function to generate random values
within the range of 34 to 43?
5. Write a constraint without an inside function to generate random values
within the range of 34 to 43?
6. Write a constraint to generate a random value for a var1 [7:0] within50
and var2 [7:0] with the non-repeated value in every randomization?
7. Without using randomization method or rand
keyword(modifiers),generate an array of unique values.
8. Generate unique elements in an array without using the keyword unique.
9. Write a constraint to generate 0, 1, x and z randomly.
10.Write a constraint to generate multiples of power 2.
11.Having 32-bit of variable, only single bit high values need to be accessed.
Write a constraint for that.
12.Write a constraint with array size 5 to 10 values & the array values should
be in ascending order/descending order.
13.Declare dynamic array size to be between 2 to 10. Generate odd numbers
in it within the range of 10 to 30 using SV constraint.

Copyright © 2023 Maven Silicon 32


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Setting standards in VLSI Design

14.Write a constraint to generate prime numbers between the range of 1 to


100.
15.How can we generate the factorial of the first 5 even numbers using
constraints in SystemVerilog?
16.Write a code that generates a random number between 1.35 to 2.57 using
SystemVerilog
17.What is the constraint to generate the pattern 9 7 5 3 1 8 6 4 2 0 ?
18.Can you provide a code example of how to use constraints to access a
single bit of a 16-bit variable? For instance, how can you generate 16- bit
numbers with only a single bit set, such as 4, 8, or 16, using constraints?
19.Write a constraint to generate a variable with 0-31 bits should be 1, 32-61
bits should be 0
20.How to generate a sequence of 10 random single-bit values that alternate
between 0 and 1 like 101010101010?
21.Write a SystemVerilog program to randomize a 32-bit variable, but only
randomize the 12th bit.
22.How can you define a constraint in System Verilog to ensure that even
locations in a random array contain odd numbers, and odd locations
contain even numbers?
23.Write a constraint to generate below pattern 1234554321
24.Write a constraint to generate below pattern 9 19 29 39 49 59 69 79
25.Write a constraint to generate a random even number between 50 and
100
26.Write a constraint for a 32 bit rand variable such that it should have 12
number of 1's non consecutively

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