Electrical Engineering - I

EEE 1183

Field Effect Transistor

(FET)

Md. Ariful Islam

Lecturer, Department of Electrical & Electronic Engineering
Rajshahi University of Engineering & Technology, Rajshahi-6204, Bangladesh
E-mail: arif.ruet.eee17@gmail.com ; ariful.islam@eee.ruet.ac.bd
1
 What is a FET ?

Definition:
FET is a transistor which utilizes electric field to control the flow of current.

Application:
▪ Amplifier
▪ Switch

2
 BJT vs FET

BJT FET
BJTs are Current Controlled Device as the FETs are Voltage Controlled Device as the
output is controlled by input current output is controlled by input voltage
Bipolar i.e. conduction depends on both Unipolar i.e. conduction depends on either
electron and hole electron or hole
Lower input impedance Higher input impedance
Higher power consumption Lower power consumption
BJTs are less temperature stable FETs are more temperature stable
Larger in size Smaller in size
Higher voltage gain Lower voltage gain

3
 Types of FET

FET

JFET MOSFET

n - channel p - channel D - MOS E - MOS

n - channel p - channel n - channel p - channel

4
Junction Field Effect Transistor
(JFET)

5
 Construction

▪ The n-type material forms the channel

between the layers of p-type material.
▪ The top of the n-type channel is connected
through an ohmic contact to a terminal
referred to as the drain (D), whereas the
lower end of the same material is
connected through an ohmic contact to a
terminal referred to as the source (S).
▪ The two p-type materials are connected
together and to the gate (G) terminal.

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 Function of the Terminals

▪ Source supplies the charge carriers

▪ Gate controls the flow of current
▪ Drain collects the charge carriers

Water analogy for realizing JFET control mechanism:

The source of water pressure can be likened to the applied
voltage from drain to source, which establishes a flow of
water (electrons) from the spigot (source). The “gate,”
through an applied signal (potential), controls the flow of
water (charge) to the “drain.”

7
 Working Principle

1. VGS = 0 and VDS > 0

▪ Since VGS = 0 (i.e. VG = VS = 0), gate and
source are shorted.
▪ The instant the voltage VDD = VDS is applied,
the electrons are drawn to the drain terminal,
establishing the conventional current ID.
▪ The depletion region is wider near the top of
both p-type materials. It occurs due to voltage
distribution among different levels of n-
channel.
▪ As the p–n junction is reverse-biased for the
length of the channel results in a gate current
of zero amperes i.e. IG = 0.

8
 Working Principle (contd.)

▪ As the voltage VDS is increased from zero to

a few volts, the current will increase as
determined by Ohm’s law.
▪ If VDS is increased to a level where it appears
that the two depletion regions would “touch”,
the resistance will tend to be infinite,
resulting into zero drain current.
▪ But, in reality a very small channel still exists
which allows to pass a constant (saturated)
current.
▪ The level of VDS that establishes this
condition is referred to as the pinch-off
Fig. Output Characteristics
voltage (VP).

9
 Working Principle (contd.)

2. VGS < 0 and VDS > 0

The result of applying a negative bias to VGS is that the
saturation level of ID is achieved at a lower level of VDS.

VDD
IDSS

Pinch-Off Region

VP 10
 Working Principle (contd.)

Application Operating Region

Saturation Region
Amplifier
(Active Region)
Switch (ON) Ohmic Region
Pinch-Off Region
Switch (OFF)
(Cut-off Region)

11
 Transfer Characteristics

Transfer characteristics describe the relationship between input and output quantities.

BJT

IC

Constant VCE
IB

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 Transfer Characteristics (contd.)

JFET

Shockley’s Equation:

Vp

13
 JFET Biasing

1. Fixed-bias Configuration
2. Self-bias configuration
3. Voltage divider configuration
4. Collector feedback configuration

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Fixed-bias Configuration

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 Fixed-bias Configuration (contd.)

2
𝑉𝐺𝐺
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1+
𝑉𝑃

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 Fixed-bias Configuration (contd.)

Example 7.1:
Determine the following for the network.
a) VGSQ
b) IDQ
c) VDS
d) VD
e) VG
f) VS

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Voltage Divider Biasing

18
 Voltage Divider Biasing (contd.)

2
𝑉𝐺 − 𝐼𝐷 𝑅𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1−
𝑉𝑃

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Voltage Divider Biasing (contd.)

20
 Voltage Divider Biasing (contd.)

Example 7.4:
Determine the following for the network.
a) IDQ and VGSQ
b) VD
c) VS
d) VDS
e) VDG

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Metal - Oxide Semiconductor Field Effect Transistor
(MOSFET)

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 MOSFET

▪ It is an electronic device which is most commonly fabricated by the controlled

oxidation of silicon.
▪ It provides higher input impedance than JFETs because of its insulated gate.

Types:
1. Depletion Type MOSFET (D - MOS)
2. Enhancement Type MOSFET (E - MOS)

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Depletion Type MOSFET
(D - MOS)

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 Construction

▪ A slab of p-type material is formed from a

silicon base and is referred to as the
substrate
▪ The source and drain terminals are
connected through metallic contacts to n-
doped regions linked by an n-channel.
▪ The gate is also connected to a metal
contact surface but remains insulated from
the n-channel by a very thin silicon
dioxide (SiO2) layer. So, There is no direct
electrical connection between the gate
terminal and the channel of a MOSFET. It
is the insulating layer that accounts for the
very desirable high input impedance of the
device.
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 Working Principle

1. VGS = 0 and VDS > 0

▪ Since VGS = 0 (i.e. VG = VS = 0), gate and
source are shorted.
▪ The instant the voltage VDD = VDS is
applied, the electrons are drawn to the drain
terminal, establishing the conventional
current ID.
▪ The insulated gate results in a gate current
of zero amperes i.e. IG = 0.

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 Working Principle (contd.)

▪ As the voltage VDS is increased from zero to

a few volts, the current will increase as
determined by Ohm’s law.
▪ If VDS is increased to a point where the
depletion region expands significantly,
causing the effective width of the channel
become extremely narrow, a constant current
will continue to flow.
▪ The level of VDS that establishes this
condition is referred to as the pinch-off
voltage (VP).
Fig. Output Characteristics

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 Working Principle (contd.)

2. VGS < 0 and VDS > 0 (Depletion Mode)

▪ IF VGS is set at a negative voltage, the
negative potential at the gate will tend to
D n
pressure electrons toward the p-type
substrate (like charges repel) and attract G SS
holes from the p-type substrate (opposite P
+ +
charges attract). VGG VDD
▪ Depending on the magnitude of the - -
negative bias, a level of recombination S n
between electrons and holes will occur
that will reduce the number of free
electrons in the n-channel resulting into
less drain current.

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 Working Principle (contd.)

3. VGS > 0 and VDS > 0 (Enhancement Mode)

▪ For positive values of VGS, the positive gate
D n
will draw additional electrons (free carriers)
from the p-type substrate due to the reverse G SS
leakage current and establish new carriers + P
through the collisions resulting between +
VGG VDD
accelerating particles. As a result, the drain - -
current will increase. S n

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Output Characteristics

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 Transfer Characteristics

2
𝑉𝐺𝑠 IDSS
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1−
𝑉𝑃

VP

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Enhancement Type MOSFET
(E - MOS)

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 Construction

▪ A slab of p-type material is formed from a

silicon base and is referred to as the
substrate
▪ The source and drain terminals are
connected through metallic contacts to n-
doped regions linked by an n-channel.
▪ There is an absence of a channel between
the two n-doped regions. This is the
primary difference between the
construction of D-MOS and E-MOS.

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 Working Principle

1. VGS = 0 and VDS > 0

▪ As there is no complete channel for electron
flow, the drain current becomes zero.

2. VGS > 0 and VDS > 0

▪ The positive VGS will pressure the holes in the
p-substrate along the edge of the SiO2 layer to
leave the area.
▪ The result is a depletion region near the SiO2
insulating layer void of holes. However, the
electrons in the p-substrate (the minority
carriers of the material) will be attracted to the
positive gate and accumulate in the region near
the surface of the SiO2 layer.
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 Working Principle

▪ As VGS increases in magnitude, the

concentration of electrons near the SiO2
surface increases until eventually the induced
n-type region can support a measurable flow
between drain and source.
▪ The level of VGS that results in the significant
increase in drain current is called the
threshold voltage and is given the symbol VT.

35
 Working Principle

▪ As the voltage VDS is increased, the current

will increase as determined by Ohm’s law.
▪ If VDS is increased to a point where the
depletion region expands significantly,
causing the effective width of the channel
become extremely narrow, a constant current
will continue to flow.
▪ The level of VDS that establishes this
condition is referred to as the saturated VDS
voltage (VDS(sat)).

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Output Characteristics

37
Transfer Characteristics

VT

38
 Home Work

1. Voltage Divider Bias Configuration for D-MOS and E-MOS.

2. Example 7.6

3. Example 7.11

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