Electronics III

Chapter 2: Basic MOS Device Physics and

Modeling
Reading: Razavi, Chs. 2, 17, & 19; Johns, Chs. 1 & 2

Mohammad Yavari
Amirkabir University of Technology
E-mail: myavari@aut.ac.ir

Copyright  2025 by M. Yavari

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 1
 General Considerations
 Two approaches to study and design of ICs:
 Start from quantum mechanics, understand solid-state physics,

semiconductor device modeling, and finally design of circuits.

 Treat each semiconductor device as a black box described by its I/V

characteristics.
 Neither approach is optimum.
 First case: the relevance of all the physics to IC design cannot be seen.

 Second case: designer cannot have a depth view of the circuit operation.

 In today’s IC design, a solid understanding of semiconductor devices is

essential most importantly in analog and RF circuits.
 In digital circuits, transistors are considered as simple switches.

 But, second order effects directly affect the circuit operation in analog/RF

ICs especially in more scaled nano-meter CMOS technologies.

 So, we need to understand the physical operation of MOS transistors and
model them as simple as yet accurate.
 The simplest level 1 is usually used in paper and pencil analysis.
 Today BSIM4 with level 54 in 90 nm or lower feature size processes utilized.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 2
 MOSFET as a Switch

 Simple view as three terminals: drain, source, gate

 It is symmetric with respect to drain and source.
 VG is “high”, transistor “connects” the source and drain together.
 VG is “low”, it isolates source and drain.
 Questions: for what values of VG does the device turn on? What is
the threshold voltage? What is the resistance between drain and
source when the device is on or off? What limits the device speed?
 To answer these questions, we need to analyze the MOS structure
and operation.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 3
 MOSFET Structure (NMOS)

 n-type MOS: NMOS, fabricated on a p-type substrate (bulk, body).

 Source and drain areas are heavily-doped n regions.
 A heavily-doped (conductive) polysilicon (called ploy) acts as the
gate.
 Polysilicon is silicon in amorphous (non-crystal) form. Poly instead
of metal (Al) is used to build small accurate transistors.
 A thin layer of silicon dioxide (SiO2) insulates the gate from the
substrate.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 4
 MOSFET Structure
 A piece of polysilicon with a width of W and length of L on top of a thin
layer of oxide defines the gate area.
 MOS devices have a very high input impedance.
 Leff = Ldrawn – 2LD, Leff: effective channel length, Ldrawn: drawn channel
length in layout, in this course we consider L = Leff.
 Leff and tox play an important role in MOS operation.
 They are reduced in scaled CMOS technologies.
 0.25 um: tox = 5 nm, Leff = 0.13 um, Ldrawn = 0.25 um
 0.13 um: tox = 3 nm, Leff = 0.08 um, Ldrawn = 0.13 um
 Today 3 nm used as commercial.
 Symmetric with respect to D and S.
 Why we call drain and source?
 Source: provides the charge carries.
 Drain: collects the charge carries.
 Source and drain terminals can be changed based on the device
terminals voltage.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 5
 Substrate Connection
 The substrate potential greatly affects the device
characteristics. => MOS is a four terminal device.
 The body connection is provided through an ohmic p+ region.
 S/D junction diodes must be reverse biased.
 The substrate of NMOS transistors is connected to the most
negative supply voltage.

NMOS cross-section

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 6
 PMOS Transistor
 In complementary MOS (CMOS) technology, both NMOS and
PMOS transistors are available.
 The PMOS device is obtained by negating all of the doping types.
 NMOS and PMOS devices must be fabricated on the same wafer => one
device type can be placed in a local substrate, usually called a “well”.
 In most of today’s CMOS processes, the PMOS device is
fabricated in an n-well.
 The well of PMOS is connected to the most positive supply
voltage.
 For the sake of brevity, we sometimes call NMOS and PMOS
devices “NFET” and “PFET,” respectively.

PMOS cross-section

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 7
 n-Well CMOS Process
 While all NFETs share the same substrate, each PFET can have an
independent n-well.
 This flexibility of PFETs is exploited in some analog circuits to
reduce the body effect.
 Twin-well CMOS with p-well inside the n-well mostly used in RFIC.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 8
 MOS Symbols

 The source of PMOS device is positioned on top because

it has a higher potential than the gate.
 In digital circuits the switch symbol is used.
 But, in analog, the distinction between D and S is needed.
 No gate dc current.
 MOS oxide capacitor between gate and body.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 9
 MOS Characteristics: Threshold Voltage
 Gate and bulk form a cap => for VGS < VTH, holes in substrate are
repelled from gate area, leaving negative ions behind to mirror
charge on the gate.
 No current flows because no carriers are available.
 A depletion region forms under the gate.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 10
 Threshold Voltage
 As VGS increases, so do the width of the depletion region and the
potential at the oxide-silicon interface => the structure resembles two
capacitors in series: the gate oxide capacitor and the depletion region
capacitor.
 When the interface potential reaches a sufficiently positive value,
electrons flow from the source to the interface and eventually to the
drain. Thus, a “channel” of charge carriers is formed under the gate
oxide between S and D, and the transistor is turned on.
 Say the interface is “inverted”
 The value of VG for which this occurs is called the “ threshold voltage,”
VTH .

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 11
 Threshold Voltage
 For VGS ≈ VTH, electrons are attracted to the interface under gate,
establishing a “channel” for conduction. The channel is also called
the “inversion layer.”
 If VGS rises further, the charge in depletion region remains
relatively constant while channel charge density continues to
increase, providing a greater current from S to D.
 Turn-on process not really abrupt, i.e., for VGS < VTH, ID > 0 =>
Sub-threshold conduction (considered later) => making it difficult to
define VTH unambiguously.
 In semiconductor physics, the VTH of an NFET is usually defined as
the gate voltage for which the interface is “as much n-type as the
substrate is p-type.” It can be proved that (VBS = 0) :

Qdep kT N sub
VTH   MS  2 F  F  ln
Cox q ni Qdep  4q si |  F | N sub

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 12
 Threshold Voltage
 Q: electron charge, Nsub: substrate doping, Qdep: depletion region
charge, Cox: gate oxide capacitor per unit area, εsi: silicon dielectric
constant.
 Cox for tox = 5 nm is about 6.9 fF/um2 and increased by scaling.
 In practice, the “native” threshold value obtained from the above
equation may not be suited to circuit design, e.g., VTH = 0 and device
does not turn off for VGS > 0.
 Threshold voltage adjusted by implantation of dopants into the channel
area during device fabrication => altering the doping level of the
substrate near the oxide interface.
 E.g. a thin sheet of p+ is created, the voltage required to deplete this
region increases.
 The above definition is not directly applicable to the measurement of
VTH.
 VGS > VTH => device assumed on abruptly.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 13
 PMOS
 The turn on phenomenon in a PMOS device is similar to that of
NMOS, but, with all of the polarities reversed.
 If the gate-source voltage become sufficiently negative, an
inversion layer consisting of holes is formed at the oxide-silicon
interface, providing a conduction path between the S and D.

NMOS: VGS  VTHN

PMOS: VGS  VTHP PMOS: VSG  | VTHP |

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 14
 MOS I/V Characteristics
 A useful Lemma: if a conductor carries a constant current I
and it has a charge density (charge per unit length) of Qd
and the charge moves with a velocity v, then we have I =
Qd  v

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 15
 MOS I/V Characteristics
 Consider an NMOS transistor with source and drain
connected to ground.
 What is the charge density in inversion layer?
 For VGS ≥ VTH, any charge placed on the gate must be

mirrored by the charge in the channel, yielding a uniform

channel charge density proportional to VGS- VTH.
 Total charge per unit length if VGS  VTH:

Qd = WCox(VGS – VTH)

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 16
 MOS I/V Characteristics
 Now suppose the drain voltage is grater than zero!
 Channel potential varies from zero at source to VD at drain =>
the local voltage difference between the gate and the channel
varies from VG to VG –VD. Thus, the charge density at a point
x along the channel can be written as:
 Note that as we approach the end of the channel, the charge
density falls.
Qd ( x)  WCox VGS  V ( x)  VTH 

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 17
 MOS I/V Characteristics
 To find the current, multiply charge density by charge
velocity. The drain current is therefore given by:
I D   WCox VGS  V ( x)  VTH  

 The negative sign is inserted because the charge carries

are negative and v denotes the velocity of the electrons in
channel.
 For semiconductors: dV
  n E , E ( x)  
dx
 Where µn is the mobility of electrons and E is the electric
field. So, dV ( x)
I D  WCox VGS  V ( x)  VTH  n
dx
V (0)  0, V ( x  L)  VDS

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 18
 MOS I/V Characteristics
 Thus,
WCox  n VGS  V ( x)  VTH  dV
L VDS
x 0
I D dx  
V 0

W 1 2 
I D  n Cox VGS VTH  VDS  VDS 
L 2 

 L: effective channel length

 Assumptions made:
 One-dimensional structure
 Constant mobility
 Constant depletion layer
charge
 VTH & n independent on x
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 19
 MOS I/V Characteristics
 Peak current occurs at VDS = VGS - VTH

I D W
 n Cox VGS VTH  VDS   0 VDS  VGS VTH
VDS L
1 W
I D ,max  nCox (VGS  VTH ) 2
2 L
 VDS = VGS – VTH = Veff is called overdrive or effective voltage.
 W/L: “aspect ratio”
 If VDS  VGS - VTH , the device operates in the “triode or linear
region”.
 nCox is technology parameter
 W & L are the main design parameters
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 20
 MOS I/V Characteristics
 If VDS << 2(VGS – VTH): W
I D   nCox VGS VTH  VDS
L
 For small VDS, each parabola can be approximated by a straight line.
Linear relationship implies that the path from the source to the drain can
be represented by a linear resistor equal to Ron.
 Thus, a MOS device can operate as a resistor whose value is controlled
by VGS (so long as VDS << 2 (VGS - VTH).
 This region is called “deep triode”.
 Note that the device can be “on” but have zero current, which occurs only
if VDS = 0.
W
R  n Cox VGS  VTH 
1
on
L

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 21
 An Example
 Plot the on-resistance of M1 as a function of VG
 Assume µnCox=50µA/V2 , W/L=10, and VTH= 0.7 V
 Drain is open!

 Solution:
 Since the drain terminal is open, ID = 0 and VDS= 0, thus, if the
device is “on” it operates in the deep triode. For VG < 1 V + VTH,
M1 is off and Ron=. For VG  1 V + VTH:
1
Ron 
50  A / V 2  10  VG  1.7 

 Triode region: R 1   C W V  V  V 
on n ox GS TH DS
L
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 22
 Pinch-Off
 What happens if VDS > VGS - VTH?
 The drain current doesn’t follow the parabolic behavior for VDS > VGS –
VTH.
 ID becomes constant => the device operates in the “saturation” region.
 The local density of inversion layer charge is proportional to (VGS –
V(x) – VTH), thus if V(x) approaches VGS – VTH, then Qd(x) drops to
zero.
 If VDS > VGS – VTH, the inversion layer drops at x < L, and the
channel is “pinched off”.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 23
 Pinch-Off

dV ( x )
I D  WCox [VGS VTH  V ( x)] n
dx

L VGS VTH
 I D dx   WCox  n VGS  V ( x)  VTH  dV
x 0 V ( x )0

1 W 1 W
I D  nCox (VGS  VTH )  n Cox (VGS  VTH ) 2
2

2 L 2 L
 L’ is the point at which Qd drops to zero and V(x) from 0 to VGS-VTH.
 ID is independent of VDS if L’ remains close to L.
 Electrons reach a high velocity near the end of inversion layer and
shoot into depletion region around the drain.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 24
 PMOS I/V Characteristics
 For PMOS device we have these equations:
W 1 2 
I DS    p Cox (VGS VTH ) VDS  VDS  , VDS  VGS  VTH
L 2 
1 W
   p Cox VGS  VTH  ,
2
I DS VDS  VGS  VTH
2 L'
W 1 2
I SD   p Cox VSG  | VTH | VSD  VSD  , VSD  VSG  | VTH |
L 2 
1 W
  p Cox VSG  | VTH | ,
2
I SD VSD  VSG  | VTH |
2 L
 The negative sign appears here because we assume ID flows from
drain to the source whereas holes flows in reverse direction.
 Since the mobility of holes is about ½ to ¼ of mobility of electrons,
PMOS suffers from lower “current drive” capability.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 25
 Saturation Region
 In saturation region, ID is independent of VDS => device acts
as a current source connected between the drain and source.
 This is only a first order modeling
 Channel length modulation makes the current source with finite
output impedance (more later).
 Only one terminal of each current source is “floating”. Why?
 Current source or sink

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 26
 Concept of Transconductance
 Drain current controlled by VGS in saturation, so, we define gm =
ID/ VGS.
 gm represents the device sensitivity to gate-source variation.
 A higher gm achieves both higher dc gain and speed.

 gm in saturation is equal to the inverse of Ron in deep triode region.

I D W W 2I D
gm  VDS const   nCox (VGS  VTH )  2 n Cox I D 
VGS L L VGS  VTH

Saturation

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 27
 Example
 Plot the transconductance as a function
of VDS:

 Solution:
 As long as VDS  Vb – VTH , M1 is in saturation => ID and gm
are constant. For VDS< Vb – VTH, M1 is in the triode region
and:
 1 W  W
gm    n Cox  2(VGS  VTH ) VDS  VDS    nCox VDS
2

VGS  2 L  L

 gm drops when device enters the triode

region => employ MOSFETs only in
saturation region as an amplifier.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 28
 Conceptual Visualization
 NMOS
 Turn-on condition: VGS  VTHN
 Saturation condition: VDS  VGS – VTHN => VGD VTHN
 PMOS
 Turn-on condition: VSG  |VTHP|
 VSD  VSG – |VTHP| => VDG |VTHP|

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 29
 Second-Order Effects: Body Effect

 Appears when VSB  0, i.e. bulk and source are not dc connected.
 As VB becomes more negative, more holes can break loose from
atoms under the gate area, leaving negative ions behind =>
depletion region can contribute more charge => inversion layer
forms for larger VG => threshold voltage ↑
 Gate and body have to “fight” for forming inversion layer at channel.
Therefore, VTH , VGS  to turn the MOS into inversion region.
 As VB drops and Qdep increases, VTH also increases, this is called
the “body effect” or the “backgate effect”.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 30
 Body Effect

 It can be proved that with body effect:

VTHN  VTHN 0    2 |  F |  VSB  2  F 
VTHP  VTHP 0   2 |  F |  VBS  2  F 
  2q si N sub / Cox  F   kT / q  ln  N sub / ni 
 Where  denotes the body effect coefficient, and VSB is the source-bulk
potential difference.
 The value of  typically lies in the range of 0.3 to 0.5 V1/2.
 VSB > 0 for NMOS and VBS > 0 for PMOS.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 31
 Body Effect: Example
 Plot the drain current if VX varies from - to 0. Assume VTH0 = 0.6
V,  =0.4 V1/2 ,and 2ΦF = 0.7 V.

 Solution: If VX is sufficiently negative, the threshold voltage of M1

exceeds 1.2 V and the device is off. So:
VGS  VTH  1.2 V  0.6V  0.4  0.7  VX 1  0.7 
 Hence, VX1 = - 4.76 V. For VX1 < VX< 0, ID increases according to:
1
I D  nCox
2
W
L 
VGS  VTH 0    2 |  F | Vx  2 F  2
 
 For VX1 < VX< 0, M1 is in saturation. Why?
 Note: body effect appears both in saturation and triode regions.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 32
 Body Effect in Circuit Design
 M1 biased in saturation. 1 W
I1   nCox Vin  Vout  VTH 
2

2 L
 When VSB = 0, as Vin , ID = cte => Vout  and Vin – Vout is constant.
 But, when Vout  => VSB  => VTH  => Vout  and hence Vin – Vout is
not constant.
 Body effect is usually undesirable. VTH variation complicates the
design of analog and even digital circuits. It is controlled by adjusting
the value of  during fabrication.
 But, it can also be used in low voltage analog design => body driven
amplifiers.

VSB = 0 VSB  0

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 33
 Channel Length Modulation
 In saturation, as VDS , the width
of depletion region between
inversion layer and drain  =>
effective channel length  => ID .
1 W
I D   nCox VGS  VTH 
2

2 L
1 1 1  L / L
L  L  L    when L  L
L  L  L L
 L/L = VDS where  is the channel length modulation coefficient.
1 W
I D  nCox VGS  VTH  1   VDS  Veff  
2

2 L
 This results in a nonzero slope in ID/VDS characteristic, and hence, a
non-ideal current source between D and S in the saturation region.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 34
 Channel Length Modulation (cont’d)

 The parameter  represents the relative variation in length for a given

increment in VDS, thus, for longer channels,  is smaller. =>   1/L.
 rds =1/(ID/VDS)  1/(ID) is the resulting small-signal resistance
between D and S.
 rds  L2 => a longer channel device results in an accurate current
source between D and S => higher dc gain in amplifiers => a key
design issue.
 In dc analysis, the effect of channel length modulation is neglected for
simplicity.
 In short channel devices, the linear approximation of L/L = VDS
becomes less accurate. => resulting in a nonlinear rds.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 35
 Subthreshold Conduction
 In reality, for VGS ≈ VTH, a “weak” inversion layer still exists and
some current flows from D to S. Even for VGS < VTH , ID is finite, but
exhibits an exponential dependence on VGS, called “subthreshold
conduction”. If 0 < VGS < VTH & VDS  200 mV:
 This conduction is important in very large circuits, e.g., memories,
because it results in finite stand-by current.
VGS W VGS Cox  Cdep
I D  I 0 exp I D  I D 0 exp    1.5 I D 0  20 nA
 VT L  VT Cox
VBE
BJT I C  I S exp
VT  C dep 
S  2.3V T  1  
ID  C ox 
MOS g m 
 VT Subthreshold slope
IC
BJT g m 
VT Very low speed, poor matching, low power
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 36
 Subthreshold Conduction (cont’d)
W  VGS  VTH    VDS 
I D  I D 0 ( )exp    1  exp   
L   VT    VT 
W V GS V TH    V DS  
I D  nC dep ( )V T exp 
2
  1  exp   
L   VT    V T 

q si N sub Cdep
Cdep   1  1.5
4B Cox
W  VGS  VTH 
I D  I D 0 ( )exp   , VDS  VT NMOS
L   VT 

W  VSG  | VTH | 
I D  I D 0 ( )exp   , VSD  VT PMOS
L   VT 
 VTH determined by device performance: upper bound is VDD/4 to
realize fast switches in digital circuits.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 37
 Voltage Limitations
 At high gate-source voltages, the gate oxide breaks down
irreversibly, damaging the transistor.
 In short-channel devices, an excessively large VDS widens
the depletion region around the drain so much that it touches
that around the source, creating a very large drain current,
this effect is called “Punch Through”.
 Hot electron effects

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 38
 Integrated Circuit Layout
 Circuits are defined by
identifying the
dimensions of the
various material layers
 layout
 The layout of a
MOSFET is determined
by both the electrical
properties and the
“design rules” imposed
by the technology.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 39
 Layout of MOS Transistors

PMOS Transistor

NMOS Transistor

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 40
 Layout Basics

 Layout database is stored in GDS format.

 Transfer to foundry was done on magnetic
tape (Tapeout).
 Tape is not used today.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 41
 Chip Micrograph

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 42
 Design Rules
 IC manufacturer imposes many constraints on the layout to ensure the
circuit is manufacturable.
 Minimum dimensions
 Minimum spacing between structures
 Design rules limit several aspects of analog circuit performance in a
given manufacturing process.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 43
 Design Rules
 Design rules define geometry in x-y dimension.
 Width, spacing, overlap.
 Z dimension is pre-determined by the foundry/
process.
 Understand design rules
 Design rules: must
 Recommended rules: want
 Guidelines: nice to have
 Following design rules ensures functionality and yield.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 44
  Design Rules
 Define  = Lmin/2
 Assume that any mask may be misaligned by 0.75 
 Relative misalignment between any two masks may be 1.5 
 Design rules must guarantee no faults.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 45
 Floor Planning
 Do floor planning before layout of cells.
 Estimate area and package pins.
 Organize block placement.
 Package choice
 Size of package versus die
 Length of bond wire and package trace (esp. for power
and ground)
 Coupling between adjacent bond wire and package
pins.
 Avoid a large output signal coupling back to weak input
signal.
 Iterative process
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 46
 Block Level Layout
 For each block
 Determine pin location of each block including power/gnd.
 Where are the signals coming and going.
 Place the transistors.
 Plan power routing (current path)
 A “ground” or “Vdd” label on a metal line does not change
parasitic resistance or inductance.
 “Vdd” needs decoupling capacitors to “ground”.
 Routing of sensitive nodes
 Separate noisy (digital, clock, …) and quiet (input, bias, …)
signals.
 Shield signal signals using ground, vdd, digital control signals
that are not toggling.
 Decouple (add capacitors) sensitive dc signals (bias, supply).
 Iterative process.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 47
 Metal Routing
 Width of metal:
 Electromigration: ~1 mA/um.
 IR drop: ~50-100 mohms/square/layer
 Wide metal rule < 10 um (process dependent) but ~10um
(process dependent) but use multiple layers or parallel
lines.

 Establish metal routing ground rules to ease layout.

 Example: M1, M3 horizontal; M2, M4 vertical

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 48
 Signal Routing
 Use low impedance node
 Example: route current instead of high impedance voltage
nodes.
 Watch for IR drop in current
 Voltage headroom
 Shield sensitive signals
 Use return path shields.
 Choose vdd or gnd.
 Shielding adds capacitance
 Consider spacing to reduce coupling.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 49
 CMP Effect
 Chemical Mechanical Polishing (CMP) process
planarizes wafer surface after each metal layer;
otherwise, unevenness of one layer that may affect
the next layer.
 Relative hardness of metal and oxide affects the
polishing.
 Solution
 Metal coverage rule: keep relatively uniform density of
metal/oxide over ~100 um diameter.
 Metal density rule to avoid large area without metal =>
dummy metal fill.
 Limit the width of metal to avoid large area with only metal =>
metal slot rules.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 50
 Dummy Metal Fill & Metal Width
 Automatic generation of small rectangles in “empty”
space to provide more uniform density.
 Dummy metal can impact parasitic capacitance.
 Can block the automatic generation of dummy metal
(with a dummy block layer) for critical circuits
 Metal width cannot be too wide.
 Copper is softer than oxide.
 CMP can over polish the copper, reducing its thickness
(increasing resistance) and making the overall surface less
planar (more difficult for higher layer metal)
 Add slots to metal width to increase the density of
oxide
 or avoid using very wide metal, use several narrower metal
lines in parallel.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 51
 Matching
 A major advantage of VLSI design is device matching:
 Fully differential circuits => CMRR, offset
 Current mirrors
 Ratioed devices: capacitors, resistors, transistors
 Random mismatch:
 Process: geometry, implant dose, …
 Systematic:
 Mask gradient
 Thermal gradient
 Systematic mismatch changes the average.
 Random mismatch leads to fluctuation/spread.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 52
 Resistors
 For passive RF components, high Q, low parasitics, and good linearity are
desired. Reduction of off chip components reduces the total system cost.
 Resistors are rarely laid out as one straight skinny rectangle.
 Use of striped structures.
 Corner squares have less resistance. => 0.56X
 A resistive strip is contacted at the two terminals by ohmic contacts (metal – p+ or
n+).
 Insulation from the surrounding is made by oxide layers or by reversely biased
junctions.
A

Striped
resistor
B

 L L
R   2 RC  R   2 RC
t W W
R: resistor sheet resistance in /
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 53
 Capacitors
A WL
C  
H
H H
W Standard formula:
L underestimates C! it does not
take fringing into account.
Substrate Accurate when W, L >> H

C 
W  2 H  L  2 H    WL  2W  2 L  A first-order model to
H  H  consider the fringing effect.

 All interconnect layers may be used to make traditional parallel plate

capacitors.
 Ordinary dielectric thickness tends to be rather high (0.5-1 m) => small
density, typical value is 0.05 fF/m2.
 Large bottom-plate parasitic capacitance: 10-30% or more of the main
capacitance. This often limits the circuit performance.
 TC of metal-metal capacitors is quite low: 30-50 ppm/C. It is dominated by TC
of oxide’s dielectric constant itself.
 High Q for MIM capacitor. Poly-poly has small Q!
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 54
 Inductors
Ltotal  L1  L2  L3
 M 12  M 13  M 23
Square
spiral

Ltotal  N ( N  1) / 2

 Active circuits synthesize an inductor, always have higher noise, distortion, and
power consumption than passive real wire inductors.
 Planar spiral inductors: has mutual coupling between every two turns.
 Larger inductance than a straight line
 Widely used on chip
 Many shapes: square, hexagonal, octagonal, circular
 Octagonal or circular spirals are moderately better than squares (typically 10%).
 Nonetheless, choice of shape is more often made on convenience or habit than
anything else.
 Use top level metals to reduce the series resistance and coupling to the substrate =>
increase Q.
 Key parameters: Q < 10, 1 nH < L < 10 nH, self resonant frequency.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 55
 Inverter Layout
VDD

Vout

N+ active Vin
P+ active
N-well active
Poly
Metal 1
VSS

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 56
 Inverter Layout (cont’d)

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 57
 Another Layout Example
VDD
Vb2 N+ active
P+ active
N-well
2 m
Poly
Metal 1

0.5 m
0.2 m Vout
VDD

M4

Vb2
4 m M3
Vout
M2
Vb1
(W/L)1,2 = ( 2 4 m)/0.2 m
Vb1 (W/L)3,4 = ( 1 2 m)/0.5 m
Vin Vin
M1
VSS VSS

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 58
 MOS Device Capacitances
 A capacitance exists between every two of four terminals of a
MOSFET. Cap between D & S can be neglected. They depend
on biasing.
 Oxide capacitance between G and channel: C1 = WLCox
 C2: depletion capacitance between channel and bulk
 C3, C4: overlap capacitance between gate ploy and D and S.
 Junction capacitance (S/B, D/B): C5, C6 = Area*Cj +
Perimeter*Cjsw, where Cj is bottom-plate and Cjsw is sidewall caps

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 59
 Example
 Calculate the source and drain junction capacitance of these
two structures.

Cdb  Csb  WEC j

2(W  E )C jsw

W W
Cdb  EC j  2(  E )C jsw
2 2
W W 
Csb  2  EC j  2(  E )C jsw   WEC j  2(W  2 E )C jsw
2 2 
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 60
 MOS Device Capacitances (cont’d)
 Cut-off: Cdb & Csb exist Cgd  C gs  CovW
always and depend on reverse WLCox Cdep
Cgb  WLCox || Cdep 
biasing voltage. WLCox  Cdep
q si N sub
 Deep-triode: D and S have Cdep  WL
4 F
approximately equal voltages.
1
 Cgb is neglected in strong Cgd  C gs  CovW  WLCox
inversion region. 2
2
 Saturation: varying channel Cgd  CovW , Cgs  WLCox  CovW
3
capacitance.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 61
 Small-Signal Model
W 1 2  1 W
I D  n Cox   GS TH  DS
V V V  VDS  I D   nCox VGS  VTH  1  VDS 
2

L 2  2 L
 If the perturbation in bias conditions is small, a small-signal model,
i.e., an approximation of the large-signal model around the operating
point, can be employed to simplify the calculations.
 Since the drain current is a function of the gate-source voltage, we
incorporate a voltage-dependent current-source equal to gmVgs.
 Channel length modulation => a linear resistor between D & S.
 VTH => Veff = VGS – VTH => ID => body effect represented by a VCCS.

W W
g m   nCox (VGS  VTH )  2 nCox I D
L L
2I D

VGS  VTH
Ideal MOS model
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 62
 Small-Signal Model (cont’d)
G D G D
Vgs gmVgs Vds Vgs gmVgs rds

S S

VDS 1
rds  |VGS cte 
MOS low-freq. model
I D I D / VDS
1 1
I D W VTH  
g mb   nCox (VGS  VTH )( ) 1 W
nCox (VGS  VTH ) 2 .  ID
VBS L VBS 2 L
VTH VTH  1 
  gm

   (2 F  VSB ) 2 g mb  g m
VBS VSB 2 2 2 F  VSB
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 63
 MOS Terminals Resistance
 Each terminal exhibits a finite ohmic resistance resulting from
the resistivity of the materials and contacts => a proper layout
can minimize such resistances.
 For example, the gate ploy resistance can be reduced by
folding or fingering => M folding results in M2 reduction.

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 64
 Complete MOS Small-Signal Model (Saturation)
Cgd
G D
Vgs Cgs gmVgs rds gmbVbs
S Cdb
Vbs Csb
B
 Current unity-gain frequency:

id 1 gm
t   @ | |vd 0  1, id  g m vgs , vgs  ig t 
ig j (C gs  C gd ) C gs  C gd
W
n Cox (VGS  VTH ) n (VGS  VTH )
t  L t 
2WLCox / 3  CovW  CovW L2
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 65
 Small-Signal T-Model (Saturation)

Ideal -model
Ideal T-model

Low freq. T-model

High freq. T-model
 It is simpler to analyze CS with -model and CD with T-model.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 66
Small-Signal Models in Triode & Cut-Off Regions
G G

Cgs Cgd Cgs Cgd

S D S Cgb D
Ron
Csb Cdb Csb Cdb

B B
Triode Deep triode Cut-off

 In triode region, the small-signal model is highly non-linear RC

distributed => the channel resistance at drain side is greater
than the source side.
 But, in deep triode region, it becomes linear.
 In cut-off region, the drain-source resistance is almost infinite.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 67
 SPICE MOS Model
 SPICE requires an accurate model for each device to simulate.
 Level 1: the following parameters are the bare minimum SPICE
needs to simulate circuits.
 Modern MOS models have several hundred parameters.

0.5 m CMOS

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 68
 NMOS versus PMOS Devices
 In most CMOS technologies, PMOS devices are quite
inferior to NMOS transistors.
 Lower mobility of holes yielding low current drive and
transconductance in PMOS devices.
 NMOS devices exhibit a higher output resistance =>
higher gain and ideal current sources.
 In overall, it is preferred to use NFETs rather than
PFETs where it is possible!

M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 69
 MOS as a Capacitor
 VGS  VTH => strong inversion (triode, saturation)
 0 < VGS < VTH => weak inversion (subthreshold)
 VGS < 0 => accumulation

CGS  WLCox CGS  WLCox || Cdep CGS  WLCox

 Cox = 12 fF/m2 in 0.13m CMOS => high density, but it is quite
nonlinear.
 CMIM = 1 fF/m2 has low density, but with high linearity.
M. Yavari Electronics III Chapter 2: Basic MOS Device Physics and Modeling 70