Lecture 5:
CMOS Transistor Theory
Mark McDermott
Electrical and Computer Engineering
The University of Texas at Austin
9/13/18 VLSI-1 Class Notes
Outline
§ Introduction
§ MOS Capacitor
§ nMOS I-V Characteristics
§ pMOS I-V Characteristics
§ Gate and Diffusion Capacitance
§ MOS Channel resistance
§ Resistors & RC approximation
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Introduction
§ So far, we have treated transistors as ideal switches
§ An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
§ Transistor gate, source, drain all have capacitance
– I = C (DV/Dt) -> Dt = (C/I) DV
– Capacitance and current determine speed
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Electrical Properties of MOS Devices
§ Necessary to understand the basic electrical properties of the
MOS transistor (geometry => electrical), e.g., delay/power
– Ensure that the circuits are robust
– Create working layouts
– Predict delays and power consumption
§ As technology advances and circuit dimensions scale down,
electrical effects become more important
– Secondary/non-ideal effects (next lecture)
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MOS Capacitor
§ Gate and body form MOS Vg < 0
polysilicon gate
silicon dioxide insulator
capacitor +
p-type body
-
§ Operating modes
– Accumulation (a)
– Depletion
0 < Vg < Vt
– Inversion depletion region
+
-
(b)
Vg > Vt
inversion region
+
- depletion region
(c)
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The nMOS Transistor
Moderately doped p- type
substrate (or well) in which
two heavily doped n+ regions,
the Source and Drain are
diffused
§ Gate is insulated from substrate by thin oxide
– Resistance of oxide is > 1012 W, so current ~ 0
§ Two types of nMOS transistor
– Enhancement mode: non conducting when gate voltage Vgs = Vsb
(source voltage) (normally used)
– Depletion mode: conducting when Vgs = Vsb
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Terminal Voltages
§ Mode of operation depends on Vg, Vd, Vs Vg
+ +
Vgs = Vg – Vs Vgs Vgd
- -
Vgd = Vg – Vd
Vs Vd
Vds = Vd – Vs = Vgs - Vgd -
Vds +
§ Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds ³ 0
§ nMOS body is grounded; for simple designs, assume
source is grounded too
§ Three regions of operation
– Cutoff
– Linear
– Saturation
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nMOS Cutoff
§ No channel
Ids ≈ 0
Vgs = 0 Vgd
+ g +
- -
s d
n+ n+
p-type body
b
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nMOS Linear
§ Channel forms
Vgs > Vt
§ Current flows from d to s + g +
Vgd = Vgs
– e- from s to d - -
s d
§ Ids increases with Vds n+ n+ Vds = 0
– Similar to linear resistor p-type body
§ Since there is a b
threshold voltage (Vt)
Vgs > Vt
Vgs > Vgd > Vt
required to invert the + g +
- -
charge under the gate, s d
Ids
this means that the n+ n+
0 < Vds < Vgs-Vt
effective gate voltage is: p-type body
b
Vg = Vgs - Vt
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nMOS Saturation
§ Channel pinches off
§ Ids independent of Vds
§ Current saturates
§ Similar to current source
Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids
n+ n+
Vds > Vgs-Vt
p-type body
b
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The pMOS Transistor
Moderately doped n- type
substrate (or well) in which
two heavily doped p+ regions,
the Source and Drain are
diffused
§ Application of a negative gate voltage (w.r.t. source) draws
holes into the region below the gate; channel changes from n
to p-type (source-drain conduction path)
§ Conduction due to holes; negative Vd sweeps holes from
source (through channel) to drain
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I-V Characteristics
§ In Linear region, Ids 60 Linear Region Saturation Region
depends on VGS = +5V
– How much charge is in the
50
channel?
VGS = +4V
Drain Current, IDS (µa)
– How fast is the charge
moving? 40
30 VGS = +3V
20
VGS = +2V
10 VGS = +1V
0
0 1 2 3 4 5 6
Drain-Source Voltage, VDS (volts)
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Channel Charge
§ MOS structure looks like parallel plate capacitor while operating
in inversion
Gate – oxide – channel
Qchannel = CV
C = Cg = eoxWL/tox = CoxWL where Cox = eox / tox
V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon + +
gate
source Vgs Cg Vgd drain
W
Vs - - Vd
tox channel
n+ - + n+
n+
L
n+
SiO2 gate oxide Vds
(good insulator, eox = 3.9)
p-type body p-type body
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Carrier Velocity
§ Charge is carried by e-
§ Carrier velocity v proportional to lateral E-field between source
and drain:
v = µ Eds where μ is the electron/hole mobility
Vds
where Eds =
L
§ Time for carrier to cross channel:
Length of the channel ( L)
t sd =
Velocity (v)
L2
or t sd =
µ Vds
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nMOS Linear I-V
§ Now we know
60 Linear Region Saturation Region
VGS = +5V
– How much charge Qchannel is in the 50
channel
Drain Current, IDS (µa)
VGS = +4V
– How much time τ each carrier 40
takes to cross 30 VGS = +3V
20
Qchannel
VGS = +2V
I ds = 10 VGS = +1V
t 0
W
0 1 2 3 4 5 6
= µCox æV - V - Vds öV Drain-Source Voltage, VDS (volts)
ç gs t 2 ÷ ds
L è ø
æ Vds ö W
= b çVgs - Vt - ÷Vds where b = µCox
è 2 ø L
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nMOS Saturation I-V
§ If Vgd < Vt, channel pinches off near
60 Linear Region Saturation Region
VGS = +5V
drain 50
– When Vds > Vdsat = Vgs – Vt
Drain Current, IDS (µa)
VGS = +4V
40
30 VGS = +3V
§ Now drain voltage no longer
increases current
20
VGS = +2V
10 VGS = +1V
æ Vdsat öV
I ds = b çVgs - Vt - ÷ dsat
0
2
0 1 2 3 4 5 6
è ø Drain-Source Voltage, VDS (volts)
b
( - Vt )
2
= Vgs
2
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nMOS I-V Summary
§ Shockley 1st order transistor models
ì
ï 0 Vgs < Vt cutoff
ï
ï æ Vds öV V < V
I ds = í b çVgs - Vt - ÷ ds linear
è 2 ø
ds dsat
ï
ï b
(Vgs - Vt )
2
ïî Vds > Vdsat saturation
2
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Example
§ Example: a 0.6 µm process from AMI semiconductor
– tox = 100 Å
– µ = 350 cm2/V*s 2.5
Vgs = 5
– Vt = 0.7 V
2
1.5 Vgs = 4
§ Plot Ids vs. Vds
Ids (mA)
– Vgs = 0, 1, 2, 3, 4, 5 1
Vgs = 3
– Use W/L = 4/2 l
0.5
Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
Vds
W æ 3.9 • 8.85 × 10-14 ö æ W ö W
b = µCox = ( 350 ) ç -8 ÷ç L ÷ = 120 µ A / V 2
L è 100 × 10 øè ø L
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pMOS I-V
§ All dopings and voltages are inverted for pMOS
§ Mobility µp is determined by holes
– Typically 2-3x lower than that of electrons µn for older technologies.
– Approaching 1 for gate lengths < 20nm.
§ Thus pMOS must be wider to provide the same current
– Simple assumption, µn / µp = 2 for technologies > 20nm
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Capacitance
§ Any two conductors separated by an insulator have capacitance
§ Gate to channel capacitor is very important
– Creates channel charge necessary for operation
§ Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is associated with source/drain
diffusion
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Gate Capacitance
§ Approximate channel as connected to source
§ Cgs = eoxWL/tox = CoxWL = Cper/micronW
§ Cpermicron is typically about 2 fF/µm for minimum channel length
device
polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, eox = 3.9e0)
p-type body
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Capacitance Estimation
§ The dynamic response (switching speed) of a CMOS circuit is very
dependent on parasitic capacitances associated with the circuit
GATE
Parasitic Capacitances:
Cgs, Cgd = gate-to-channel
C gs C gb C gd t ox
capacitances lumped at
CHANNEL
SOURCE DRAIN source and drain regions
C sb
DEPLETION LAYER
C db
Csb, Cdb = source and drain
diffusion capacitances to
P-SUBSTRATE bulk (substrate)
Add routing capacitances to get total capacitance.
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Gate Capacitance of MOS Transistor
W = 49.2 µ,
L = 0.75µ
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Gate Capacitance of MOS Transistor (cont.)
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Gate Capacitance: Operation Region Dependence
G G G
CGC CGC CGC
S D S D S D
Cut-off Linear (Triode) Saturation
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Diffusion Capacitance
§ Csb, Cdb from Source/Drain
§ Undesirable, called parasitic capacitance
§ Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process
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Area and Periphery Capacitance
Cjp = Periphery capacitance (pf/µ)
DIFFUSION
C
jp
Xd
DIFFUSION a
Cja C C
jp jp
C
GND OR V ss jp
Cja = Area capacitance (pf/µ2)
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Pass Transistors
§ We have assumed source is grounded
§ What if source > 0?
– e.g. pass transistor passing VDD VDD
VDD
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Pass Transistors
§ We have assumed source is grounded
§ What if source > 0?
– e.g. pass transistor passing VDD VDD
§ Vg = VDD VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
§ nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded 1
– Approach degraded value slowly (low Ids)
§ pMOS pass transistors pull no lower than Vtp
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Pass Transistor Circuits
VDD VDD VDD
VDD VDD
VDD
Vs = VDD-Vtn VDD-Vtn
VDD-Vtn VDD-Vtn
VDD
Vs = |Vtp| VDD-Vtn
VDD VDD-2Vtn
VSS
NOTE: These values are for steady state conditions only.
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Effective Resistance
§ Shockley models have limited value
– Not accurate enough for modern
transistors
– Too complicated for hand analysis
§ Simplification: treat transistor as
resistor
– Replace Ids(Vds, Vgs) with effective
resistance R
• Ids = Vds/R
– R averaged across switching of digital
gate
§ Too inaccurate to predict current at
any given time
– But good enough to predict RC delay
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The MOS Resistor
I
AO O B
§ Resistance of a bar of uniform material
§ The channel resistance of a MOS transistor in the linear region
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Resistance of Turned-On Transistor
W/L ratio defines size of N and P channel transistors
Channel resistance of turned-on transistor is:
k is in the range of 1000 -- 30,000 Ω /
Resistance increases by about 0.25%/℃ above 25℃
I R = 3 s I
R = L/W * R = 1/3 s
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Resistors Connected in Series
R1 R2 R1 R2
R = R1 + R2 = 2s
I
Sheet Resistance, Rs: Any
W
material on the chip can be W
divided into squares W on L
a side with (Rs W/ ) R = Rs(L/W)W
Typical sheet resistances (W/) for 0.25µ TSMC process:
4.7 for N+, 3.5 for P+, 4.2 for Poly, 0.06 for Metal1,
0.08 for Metal2 - Metal4, 0.03 for Metal5, and 1190 for the N-well
Increase of about 0.3%/C (metal, poly), 1%/C (diffusion)
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Resistors Connected in Parallel
R1
R2
For two squares in parallel, the equivalent resistance is ½
Expressing sheet resistance in s simplifies the calculations
Contact resistance becomes more important as processes
scale down
About 6 Ω for N+, P+, Poly, Metal 4
2 Ω for Metal2
4 Ω for Metal3 Use multiple contacts/vias for
8 Ω for Metal5 low resistance connections
in a 0.25m TSMC process
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RC Delay Model
§ Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
§ Capacitance proportional to width
§ Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d
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Inverter Delay Estimate
§ Estimate the delay of a fanout-of-1 inverter
2C
2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C
C delay ~ 6RC
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Backup
9/13/18 VLSI-1 Class Notes • Page 38
Example of SPICE Deck
*file [Link] test of 10 stage lumped mos model
* comments
.option scale=1e-6 post=2 nomod
vin in 0 pl 0v 0n 5v 100ps
.param rpoly=40 wt=100 lt=1.2
m1 single in 0 0 n w=wt l=lt
xm1 lumped in 0 0 lrgtp xw=wt xl=lt
vsingle single 0 5v
vlumped lumped 0 5v
.tran 25ps 4ns
.graph tran model=time1 single=par('-i(vsingle)) lumped=par('-i(vlumped)')
.model time1 plot xmin=0ps xmax=800ps
* subckt and model on next page
*.subckt lrgtp drain gate source bulk
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Example of SPICE Deck, Contd
.subckt lrgtp drain gate source bulk
m1 drain gate source bulk n w='xw/18' l=xl
m2 drain g1 source bulk n w='xw/9' l=xl
m3 drain g2 source bulk n w='xw/9' l=xl
m4 drain g3 source bulk n w='xw/9' l=xl
m5 drain g4 source bulk n w='xw/9' l=xl
m6 drain g5 source bulk n w='xw/9' l=xl
m7 drain g6 source bulk n w='xw/9' l=xl
m8 drain g7 source bulk n w='xw/9' l=xl
m9 drain g8 source bulk n w='xw/9' l=xl
m10 drain g9 source bulk n w='xw/18' l=xl
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Example of SPICE Deck, Contd
r1 gate g1 'xw/xl*rpoly/9'
r2 g1 g2 'xw/xl*rpoly/9'
r3 g2 g3 'xw/xl*rpoly/9'
r4 g3 g4 'xw/xl*rpoly/9'
r5 g4 g5 'xw/xl*rpoly/9'
r6 g5 g6 'xw/xl*rpoly/9'
r7 g6 g7 'xw/xl*rpoly/9'
r8 g7 g8 'xw/xl*rpoly/9'
r9 g8 g9 'xw/xl*rpoly/9'
.ends lrgtp
* * model section *
.model n nmos level=3 vto=0.7 uo=500 kappa=.25 kp=30u
eta=.03 theta=.04 +vmax=2e5 nsub=9e16 tox=250e-10
gamma=1.5 pb=0.6 js=.1m xj=0.5u ld=0.0
+nfs=1e11 nss=2e10 cgso=200p cgdo=200p cgbo=300p
.end
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Spice Simulation: NAND Gate
SPICE "deck" has "measure", print statements; parameters, netlist
Model: 0.18 micron
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Modes in MOS Structures
ACCUMULATION Vgs <<Vt DEPLETION Vgs = Vt
+ + + polysilicon gate + + +
silicon dioxide
insulator
+ + + depletion region
+ +
+ + + p-substrate - + + + -
+ + + + + +
INVERSION Vgs > Vt
+ + +
- - -
inversion region
(n type)
depletion +
region -
+ + +
+ + +
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Greek alphabet
9/13/18 VLSI-1 Class Notes Page 44
