UNIT I MOS TRANSISTOR PRINCIPLES

MOS logic families (NMOS and CMOS), Ideal and Non Ideal IV Characteristics, CMOS devices.
MOS(FET) Transistor Characteristic under Static and Dynamic Conditions, Technology Scaling, power
consumption

Very-large-scale integration (VLSI) is a process of combining thousands of transistors into a single chip. It started
in the 1970s with the development of complex semiconductor and communication technologies.
The first integrated circuits contained only a few transistors. Early digital circuits contain transistors in tens,
provided a few logic gates and early ICs had as few as two transistors. MOS transistor is widely used in integrated
circuits.

1.1: INTRODUCTION: (VLSI)

 In 1958, Jack Kilby built the first integrated circuit flip-flop at Texas Instruments.
 Bell Labs developed the bipolar junction transistor. Bipolar transistors were more reliable, less noisy and
more power-efficient.
 In 1960s, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) began to enter in the
production.
 MOSFETs offer the compelling advantage that; they draw almost zero control current while idle.
 They come in two flavors: nMOS and pMOS, using n-type and p-type silicon respectively.
 In 1963, Frank Wanlass at Fairchild described the first logic gates using MOSFETs. Fairchild’s gates used
both nMOS and pMOS transistors, naming as Complementary Metal Oxide Semiconductor (CMOS).
 Power consumption became a major issue in the 1980s as hundreds of thousands of transistors were
integrated onto a single die.
 CMOS processes were widely adopted and replaced nMOS and bipolar processes for all digital logic
applications.

 In 1965, Gordon Moore observed that plotting the number of transistors that can be most economically
manufactured on a chip gives a straight line on a semi logarithmic scale.

 Moore’s Law is defined as transistor count doubling every 18 months.

The level of integration of chips is classified as

 Small Scale Integration (SSI)
 Medium Scale Integration (MSI)
 Large Scale Integration (LSI)
 Very Large Scale Integration (VLSI)
 Ultra Large Scale Integration (ULSI)
Small scale Integration:
 Small-Scale Integration (SSI) circuits have less than 10 gates. Example: 7404 inverter.
Medium scale Integration:
 Medium-Scale Integration (MSI) circuits have up to 1000 gates. Example: 74161 counter.
Large scale Integration:
 Large-Scale Integration (LSI) circuits have up to 10,000 gates. Example: 8-bit microprocessor (8085).
Very large scale Integration:
 Very large scale Integration (VLSI) with gates counting up to lakhs. Example: 16-bit microprocessor
(8086).
 The feature size of a CMOS manufacturing process refers to the minimum dimension of a transistor that
can be reliably built.
Ultra large scale Integration:
 Ultra Large-Scale Integration (ULSI) is the process of integrating millions of transistors on a single silicon
semiconductor microchip.
*****************************************************************************

1)MOS Logic Families

MOS Transistor
MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a type of Field Effect Transistor (FET) used as
a switch and amplifier of signals in electronic circuits. MOSFETs are either NMOS (n-channel) or PMOS (p-
channel) transistors, which are fabricated as individually packaged discrete components for high power
applications as well as by the hundreds of millions inside a single chip (IC).

Definition
A MOS transistor is called a majority carrier device in which the current in a conducting channel between the
source and the drain is modulated by a voltage applied to the gate.

Basic forms of MOSFET

MOSFETs are available in two basic forms:
 Depletion Type – the transistor requires the Gate-Source voltage, (V GS ) to switch the device “OFF”. The
depletion mode MOSFET is equivalent to a “Normally Closed” switch.
 Enhancement Type – the transistor requires a Gate-Source voltage, (V GS ) to switch the device “ON”. The
enhancement mode MOSFET is equivalent to a “Normally Open” switch.
Structure of MOSFET
A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several layers of conducting and
insulating materials to form a sandwich-like structure. Each transistor consists of a stack of the conducting gate,
an insulating layer of silicon dioxide (SiO 2), and the silicon wafer, also called the substrate, body or bulk.
MOSFET is a four-terminal device with source(S), gate(G), drain(D) and body(B) terminals. The body is
frequently connected to the source terminal. There are two main types of MOSFET: n-channel and p-channel.

n-channel MOSFET p-channel MOSFET

 1.1 : Modes of MOS TRANSISTOR
Accumulation (Enhancement) mode:
 In Figure 2(a), when a negative voltage is applied to the gate, negative charges are formed on
the gate.
 The positively charged holes are attracted to the region under the gate. This is called the
accumulation mode.

Depletion mode:
 In Figure 2(b), when a small positive voltage is applied to the gate, positive charges are
formed on the gate.
 The holes in the body are repelled from the region directly under the gate, resulting in a
depletion region forming below the gate.

Inversion layer:
 In Figure 2(c), when a higher positive potential greater than threshold voltage (Vt) is applied,
more positive charges are attracted to the gate.
 The holes are repelled and some free electrons in the body are attracted to the region under the
gate. This conductive layer of electrons in the p-type body is called the inversion layer.
 The threshold voltage depends on the number of dopants in the body and the thickness tox of
the oxide.

Figure 2: MOS structure demonstrating (a) accumulation, (b) depletion, and (c) inversion layer

NMOS Structure (n-channel MOSFET)

A basic n-channel MOSFET is made up of p-type lightly doped silicon substrate. It consists of two heavily doped
n-type regions, source and drain which constitute the main terminals of the device. A thin layer of silicon dioxide
(SiO2) is grown over the region between source and drain and is called thin or gate oxide. Gate oxide is covered
by a conductive material often polycrystalline silicon (polysilicon) and form the gate of the transistor. The body is
typically grounded. The region between source and drain is called the channel. The channel conductivity is
controlled by the gate voltage.
Operation
In NMOS transistor, the body is generally grounded so the p-n junctions of the source and drain to body are
reverse biased.
1. If the gate is grounded (Vgs=0), no current flows from source to drain i.e reverse biased p-n junctions.
Hence the transistor is OFF.
2. If the gate voltage is raised (Vgs>0), it creates an electric field that starts to attract free electrons to the
underside of the Si-SiO2 interface.
3. If the voltage is raised enough, the electrons form a thin region which acts as a conducting channel
between source and drain called the inversion layer. Hence the transistor is ON.

Characteristics of n-channel MOSFET

MOS transistors have three regions of operation:
i) Cutoff or subthreshold region
ii) Linear or nonsaturation region
iii) Saturation region
i) Cutoff or subthreshold region (Vgs< Vt)
In cutoff region, the gate-to-source voltage (V gs) is less than the threshold voltage (V t or VTHn).The source and
drain have free electrons. The body has free holes but no free electrons. The junctions between the body and the
source or drain are reverse-biased, so almost zero current flows. This mode of operation is called cut-off.
ii) Linear or nonsaturation region (Vgs > Vt and Vds<Vgs-Vt)
When the gate-to-source voltage (Vgs) is greater than threshold voltage (Vt) and drain-to-source voltage (Vds) is
small enough, the inversion layer is available for whole distance from source to drain. This mode of operation is
termed linear, resistive, nonsaturated or unsaturated. The current increases with both drain voltage and gate
voltage.
iii) Saturation region (Vgs>Vt and Vds>Vgs-Vt)
If the gate-to-source voltage (Vgs) is greater than threshold voltage (V t) and Vds becomes sufficiently large, the
channel is no longer inverted near the drain and becomes pinched off.
 V-I Characteristics of n-channel transistor
1.3.2) PMOS Structure (p-channel Transistor)
PMOS transistor is just the opposite. It consists of p-type source and drain regions with n-type body. The body is
held at a high potential.
Operation
1 . When the Gate is at a high potential, the source and drain junctions are reverse biased and no current flows. So
the transistor is OFF.
2.When the gate voltage is lowered enough, a conducting path of positive carriers is formed from source to drain ,
so the transistor is ON.

MOS Transistor Symbols

Symbols
NMOS Transistor
 pMOS transistor

MOS transistors can be viewed as simple on/off switches because the gate of an MOS transistor controls the flow
of current between the source and drain.

nMOS transistor
When the gate of an nMOS transistor is 1, the transistor is ON and there is a conducting path from source to drain.
When the gate is low or 0, the nMOS transistor is OFF and almost zero current flows from source to drain.

pMOS Transistor
When the gate is low or 0, the transistor is ON. When the gate is high or VDD, the transistor is OFF.

Long Channel I-V Characteristics

MOS transistors have three regions of operation:
 Cutoff or subthreshold region
 Linear region
 Saturation region

Let us derive a model relating the current and voltage (I-V) for an nMOS transistor in each of these regions.
The model assumes that the channel length is long enough that the lateral electric field (the field between source
and drain) is relatively low. This model is variously known as the long-channel, ideal, first-order, or Shockley
model.

Cutoff or subthreshold region

When the gate to source voltage is less than the threshold voltage (V gs < Vt), the transistor is OFF. There is no
current to flow.
I ds=0

Linear Region
The long-channel MOSFET model assumes that the current through an OFF transistor is 0. When a transistor turns
ON (Vgs>Vt), the gate attracts carriers (electrons) to form a channel. The electrons drift from source to drain at a
rate proportional to the electric field between these regions. Thus, currents can be computed if the amount of
charge in the channel and the rate at which it moves is known.
The charge on each plate of a capacitor is Q = CV. Thus, the charge in the channel Qchannel is

Qchannel =C g (V gc −V t ) (1)

where Cg is the capacitance of the gate to the channel

V gc -Vt is the amount of voltage attracting charge to the channel beyond the minimum required to invert
from p to n.
The gate voltage is referenced to the channel, which is not grounded.
If the source is at Vs and the drain is at Vd , the average is
V c =( V s +V d ) /2 (2)
We know that V ds=V d−V s
V d =V ds +V s (3)
Sub equation (3) into equation (2)
V c =V s+ V ds /2 (4)
Therefore, the mean difference between the gate and channel potentials Vgc is
V gc=V g−V c (5)
Substituting Vc in Equation (4) into equation (5),
V gc=V g−V s−V ds /2
V gc=V gs−V ds /2 (6)

nMOS Transistor
To model the gate as a parallel plate capacitor with capacitance proportional to area over thickness. If the gate has
length L and width W and the oxide thickness is tox, the capacitance is

WL WL
C g=k OX ε O =ε OX =COX WL (7)
t OX t OX
 Transistor Dimensions
where ε0 is the permittivity of free space, 8.85 × 10–14 F/cm,
the permittivity of SiO2 is kox = 3.9 times as great.
The εox/tox term is called Cox, the capacitance per unit area of the gate oxide.
tOX is the thickness of a layer of SiO2.

Each carrier in the channel is accelerated to an average velocity, v, proportional to the lateral electric field, i.e., the
field between source and drain. The constant of proportionality R is called the mobility.
v=µE (8)

A typical value of µ for electrons in an nMOS transistor with low electric fields is 500–700 cm2/V·s.
The electric field E is the voltage difference between drain and source V ds divided by the channel length
V ds
E= (9)
L

Therefore, the velocity is

V ds
v=µ
(10)
L

The time required for carriers to cross the channel is the channel length divided by the carrier velocity: L/v.
Therefore, the current between source and drain is the total amount of charge in the channel divided by the time
required to cross
Q channel
I ds = (11)
L/ v

Substitute Qchannel,
C g (V gc −V t )
¿
L/ v

Substitute the values of C g, V gc and v

¿
(
COX WL ( V gs−
V ds
2 )−V t )

L
V ds
µ
L
 W
I ds =µC OX ( V −V t −V ds /2 ) V ds
L gs
(12)

V ds
¿ β (V ¿ − )V ds (13)
2

W
where, β=µ COX and V ¿ =V gs−V t
L
Equation (12) describes the linear region of operation, for V gs > Vt, but Vds relatively small. It is called linear or
resistive because when Vds << VGT, Ids increases almost linearly with V ds, just like an ideal resistor. The geometry
and technology-dependent parameters are sometimes merged into a single factor β.

The constant term k includes technology dependent parameters alone.

k =µ C OX (14)

Saturation Region
If Vds > Vdsat ≡ VGT ≡ Vgs-Vt, the channel is no longer inverted in the vicinity of the drain. It is said to be pinched
off. Beyond this point, called the drain saturation voltage, increasing the drain voltage has no further effect on
current.

Substituting Vds = Vdsat into Equation (12), to find an expression for the saturation current that is independent of
Vds.
2
W (V gs−V t ) (15)
I ds=µC OX
L 2

β 2
I ds = V ¿ (16)
2
This expression is valid for V gs > Vt and Vds > Vdsat. Thus, long-channel MOS transistors are said to exhibit square-
law behavior in saturation.
Current in the three regions are

{
0 V gs <V t Cutoff
I ds= β ( V ¿ −V ds /2 ) V ds V ds <V dssat Linear
β 2
V V >V Saturation
2 ¿ ds dsat

Non ideal I-V Effects

The long-channel I-V model neglects many effects that are important to devices with channel lengths below 1
micron. The simulated I-V characteristic of a 1-micron wide nMOS transistor in a 65 nm process is compared with
the ideal characteristics as shown in Figure.
 I-V Characteristics of nMOS Transistor

The non ideal effects are

1. Mobility degradation and velocity saturation
2. Channel Length Modulation
3. Threshold Voltage Effects
4. Leakage
5. Temperature Dependence
6. Geometry Dependence

Mobility degradation and velocity saturation

The saturation current increases less than quadratically with increasing Vgs. This is caused by two effects: velocity
saturation and mobility degradation.

Velocity saturation : At high lateral field strengths (V ds/L), carrier velocity ceases to increase linearly with field
strength. This is called velocity saturation and results in lower Ids than expected at high Vds.

According to the equation, carrier drift velocity is proportional to electric field,

v=µE
where, the electric field E is the voltage difference between drain and source V ds divided by the channel length L
V ds
E=
L
In saturation region, current is proportional to the lateral electric field E lat = Vds /L between source and drain. The
constant of proportionality is called the carrier mobility, µ. The long-channel model assumed that carrier mobility
is independent of the applied fields. This is a good approximation for low fields, but breaks down when strong
lateral or vertical fields are applied. Carriers approach a maximum velocity vsat when high fields are applied. This
phenomenon is called velocity saturation.

Mobility degradation: At high vertical field strengths (V gs/tox), the carriers scatter off the oxide interface more
often, slowing their progess. This mobility degradation effect also leads to less current than expected at high V gs.
A high voltage at the gate of the transistor attracts the carriers to the edge of the channel, causing collisions with
the oxide interface that slow the carriers. This is called mobility degradation.

Figure shows the measured data for carrier velocity as a function of the electric field, E, between the drain and
source.
At low fields, the velocity increases linearly with the field. The slope is the mobility, R eff. At fields above a critical
level, Ec, the velocity levels out at vsat, which is approximately 107 cm/s for electrons and 8 × 106 cm/s for holes.
The velocity can be approximated as,

{
µeff E
E< Ec
v= 1+ E
Ec
v sat E ≥ E c

where, the critical electric field is

2 v sat
Ec =
µ eff
The critical voltage Vc is the drain-source voltage at which the critical effective field is reached: V c = EcL.
By applying the new carrier velocity expression into current equations, gives modified equations for linear and
saturation currents,

{
µeff W
C OX ( V ¿−V ds /2 ) V ds V ds <V dsat Linear
V L
I ds= 1+ ds
Vc
C OX W ( V ¿ −V dsat ) v sat V ds ≥V dsat Saturation

The mobility term is reduced by a factor related to V ds. At sufficiently high lateral fields, the current saturates at
some value dependent on the maximum carrier velocity.

Channel Length Modulation

The saturation current of the non ideal transistor increases somewhat with Vds. This is caused by channel length
modulation, in which higher Vds increases the size of the depletion region around the drain and thus effectively
shortens the channel.
Ideally, Ids is independent of Vds for a transistor in saturation, making the transistor a perfect current source. the p–
n junction between the drain and body forms a depletion region with a width L d that increases with Vdb as shown in
Figure.
The depletion region effectively shortens the channel length to
Leff =L−Ld
Hence, increasing Vds decreases the effective channel length. Shorter channel length results in higher current; thus,
Ids increases with Vds in saturation. This can be crudely modeled by multiplying I ds by a factor of (1 + V ds/VA),
where VA is called the Early voltage. In the saturation region, the current equation becomes,
β 2
I ds= V ¿ 1+
2 [ ]
V ds
VA
As channel length gets shorter, the effect of the channel length modulation becomes relatively more important.
Hence, VA is proportional to channel length. Channel length modulation is very important to analog designers
because it reduces the gain of amplifiers.

Threshold Voltage Effects

The threshold voltage indicates the gate voltage necessary to invert the channel and is primarily determined by the
oxide thickness and channel doping levels. However, other fields in the transistor have some effect on the channel,
effectively modifying the threshold voltage. Increasing the potential between the source and body raises the
threshold through the body effect. Increasing the drain voltage lowers the threshold through drain-induced barrier
lowering. Increasing the channel length raises the threshold through the short channel effect.

Body Effect
A transistor is usually considered to be a three-terminal device with gate, source, and drain. However, the body is
an implicit fourth terminal. When a voltage V sb is applied between the source and body, it increases the amount of
charge required to invert the channel, hence, it increases the threshold voltage. The threshold voltage can be
modeled as

V t =V t 0 + γ ( √ ϕ s +V sb−√ ϕ s )

where Vt0 is the threshold voltage when the source is at the body potential, ϕ s is the surface potential at threshold,
and γ is the body effect coefficient, typically in the range 0.4 to 1 V1/2.

NA
ϕ s =2 v T ln
ni

t OX √2 q ε si N A
γ=
ε OX
√ 2 q ε si N A =
C OX

where NA is the doping level.

Drain-Induced Barrier Lowering
The drain voltage Vds creates an electric field that affects the threshold voltage. This drain-induced barrier
lowering (DIBL) effect is especially pronounced in short-channel transistors. It can be modeled as
V t =V t 0 −η V ds
where η is the DIBL coefficient, typically on the order of 0.1. Drain-induced barrier lowering causes I ds to increase
with Vds in saturation.

Short Channel Effect

The threshold voltage typically increases with channel length. This phenomenon is especially pronounced for
small L where the source and drain depletion regions extend into a significant portion of the channel, and hence is
called the short channel effect or Vt rollof. In some processes, a reverse short channel effect causes V t to decrease
with length. There is also a narrow channel effect in which V t varies with channel width; this effect tends to be
less significant because the minimum width is greater than the minimum length.

Leakage
Even when transistors are nominally OFF, they leak small amounts of current. Leakage mechanisms include
subthreshold conduction between source and drain, gate leakage from the gate to body, and junction leakage from
source to body and drain to body, as illustrated in Figure.

Leakage current paths

Subthreshold conduction is caused by thermal emission of carriers over the potential barrier set by the threshold.
Gate leakage is a quantum-mechanical effect caused by tunneling through the extremely thin gate dielectric.
Junction leakage is caused by current through the p-n junction between the source/drain diffusions and the body.

Subthreshold Leakage
The long-channel transistor I-V model assumes current only flows from source to drain when V gs > Vt. In real
transistors, current does not abruptly cut off below threshold, but rather drops off exponentially, as seen in Figure.
 I-V characteristics of a 65 nm nMOS transistor

When the gate voltage is high, the transistor is strongly ON. When the gate falls below V t, the exponential decline
in current appears as a straight line on the logarithmic scale. This regime of V gs < Vt is called weak inversion. The
subthreshold leakage current increases significantly with V ds because of drain-induced barrier lowering. There is a
lower limit on Ids set by drain junction leakage that is exacerbated by the negative gate voltage.
Subthreshold leakage increases exponentially as Vt decreases or as temperature rises, so it is a major problem for
chips using low supply and threshold voltages and for chips operating at high temperature.

Gate Leakage
For gate oxides thinner than 15-20 Aº, there is a nonzero probability that an electron in the gate will find itself on
the wrong side of the oxide, where it will get whisked away through the channel. This effect of carriers crossing a
thin barrier is called tunneling, and results in leakage current through the gate.
Two physical mechanisms for gate tunneling are called Fowler-Nordheim (FN) tunneling and direct tunneling. FN
tunneling is most important at high voltage and moderate oxide thickness and is used to program EEPROM
memories. Direct tunneling is most important at lower voltage with thin oxides and is the dominant leakage
component.

Junction Leakage
The p–n junctions between diffusion and the substrate or well form diodes, as shown in Figure.

Substrate to Diffusion Diodes in CMOS circuits

The well-to-substrate junction is another diode. The substrate and well are tied to GND or VDD to ensure these
diodes do not become forward biased in normal operation. However, reverse-biased diodes still conduct a small
amount of current ID.

I =I [ e ]
VD
vT
D S −1
where IS depends on doping levels and on the area and perimeter of the diffusion region and V D is the diode
voltage (e.g., –Vsb or –Vdb). When a junction is reverse biased by significantly more than the thermal voltage, the
leakage is just –IS, generally in the 0.1–0.01 fA/µm2 range, which is negligible compared to other leakage
mechanisms.
Temperature Dependence
Temperature Dependence Transistor characteristics are influenced by temperature. Carrier mobility decreases with
temperature. An approximate relation is

[ ]
−k
T µ

µ (T )=µ(T r )
Tr
where T is the absolute temperature, T r is room temperature, and kµ is a fitting parameter with a typical value of
about 1.5. vsat also decreases with temperature, dropping by about 20% from 300 to 400 K.
Ion at high VDD decreases with temperature. Subthreshold leakage increases exponentially with temperature.
At high Vgs, the current has a negative temperature coefficient; i.e., it decreases with temperature. At low V gs, the
current has a positive temperature coefficient. Thus, OFF current increases with temperature. ON current I dsat
normally decreases with temperature, so circuit performance is worst at high temperature.

Idsat vs Temperature

Geometry Dependence
The layout designer draws transistors with width and length W drawn and Ldrawn. The actual gate dimensions may
differ by some factors XW and XL. The source and drain tend to diffuse laterally under the gate by L D, producing a
shorter effective channel length that the carriers must traverse between source and drain. Similarly, W D accounts
for other effects that shrink the transistor width. The effective transistor length and width are
Leff =Ldrawn + X L −2 LD
W eff =W drawn + X W −2 W D

C-V Characteristics
Each terminal of an MOS transistor has capacitance to the other terminals. In general, these capacitances are
nonlinear and voltage dependent (C-V); however, they can be approximated as simple capacitors when their
behavior is averaged across the switching voltages of a logic gate.

Simple MOS Capacitance Models

Gate Capacitance
The gate of an MOS transistor is a good capacitor. Indeed, its capacitance is necessary to attract charge to invert
the channel, so high gate capacitance is required to obtain high Ids. The gate capacitor can be viewed as a parallel
plate capacitor with the gate on top and channel on bottom with the thin oxide dielectric between. Therefore, the
capacitance is
C g=C OX WL
The bottom plate of the capacitor is the channel, which is not one of the transistor’s terminals. When the transistor
is on, the channel extends from the source (and reaches the drain if the transistor is unsaturated, or stops short in
saturation). Thus, we often approximate the gate capacitance as terminating at the source and call the capacitance
Cgs.

Most transistors used in logic are of minimum manufacturable length because this results in greatest speed and
lowest dynamic power consumption. Thus, taking this minimum L as a constant for a particular process, we can
define
C g=C permicron × W
E OX
where, C permicron =COX L= L
t Ox
Source and Drain Capacitance
In addition to the gate, the source and drain also have capacitances. These capacitances are not fundamental to
operation of the devices, but do impact circuit performance and hence are called parasitic capacitors. The source
and drain capacitances arise from the p–n junctions between the source or drain diffusion and the body and hence
are also called diffusion capacitance Csb and Cdb . A depletion region with no free carriers forms along the
junction. The depletion region acts as an insulator between the conducting p- and n-type regions, creating
capacitance across the junction. The capacitance of these junctions depends on the area and perimeter of the
source and drain diffusion, the depth of the diffusion, the doping levels, and the voltage. As diffusion has both
high capacitance and high resistance, it is generally made as small as possible in the layout. Three types of
diffusion regions are frequently seen, illustrated by the two series transistors in Figure.

Diffusion region geometries

Detailed MOS Gate Capacitance Model

The MOS gate sits above the channel and may partially overlap the source and drain diffusion areas.
Therefore, the gate capacitance has two components:
i. the intrinsic capacitance Cgc (over the channel)
ii. the overlap capacitances Cgol (to the source and drain).
The intrinsic capacitance was approximated as a simple parallel plate with capacitance
C0 = WLCox.
However, the bottom plate of the capacitor depends on the mode of operation of the transistor. The intrinsic
capacitance has three components representing the different terminals connected to the bottom plate: Cgb (gate-
to-body), Cgs (gate-to-source), and Cgd (gate-to-drain).

Cutoff : When the transistor is OFF (Vgs< Vt), the channel is not inverted and charge on the gate is matched
with opposite charge from the body. This is called Cgb, the gate-to-body capacitance. For negative Vgs, the
transistor is in accumulation and Cgb = C0. As Vgs increases but remains below a threshold, a depletion region
forms at the surface. This effectively moves the bottom plate downward from the oxide, reducing the
capacitance, as shown in Figure.
Linear: When Vgs > Vt, the channel inverts and again serves as a good conductive bottom plate. However, the
channel is connected to the source and drain, rather than the body, so Cgb drops to 0. At low values of Vds, the
channel charge is roughly shared between source and drain, so Cgs = Cgd = C0/2. As Vds increases, the region near
the drain becomes less inverted, so a greater fraction of the capacitance is attributed to the source and a smaller
fraction to the drain, as shown in Figure.

Saturation. At Vds > Vdsat, the transistor saturates and the channel pinches off. At this point, all the intrinsic
capacitance is to the source. Because of pinchoff, the capacitance in saturation reduces to Cgs = 2/3 C0 for an ideal
transistor.

Overlap Capacitances
The gate overlaps the source and drain in a real device and also has fringing fields terminating on the source and
drain. This leads to additional overlap capacitances. These capacitances are proportional to the width of the
transistor.
 Overlap Capacitance
C gsol (overlap)=C gsol W
C gdol(overlap)=C gdol W

The typical values are Cgsol = Cgdol = 0.2 – 0.4 fF/µm.

Because the source and drain actually form second terminals, the effective gate capacitance varies with the
switching activity of the source and drain.

Detailed MOS Diffusion Capacitance Model

The p–n junction between the source diffusion and the body contributes parasitic capacitance across the depletion
region. The capacitance depends on both the area AS and sidewall perimeter PS of the source diffusion region.

Diffusion Region Geometry

The area is AS = WD. The perimeter is PS = 2W +2D. Of this perimeter, W abuts the channel and the
remaining W + 2D does not.
The total source parasitic capacitance is
C sb= AS ×C jbs + PS × C jbssw
where Cjbs (the capacitance of the junction between the body and the bottom of the source) has units of
capacitance/area and Cjbssw (the capacitance of the junction between the body and the side walls of the source)
has units of capacitance/length. Because the depletion region thickness depends on the bias conditions, these
parasitics are nonlinear. The area junction capacitance term is

[ ]
−MJ
V sb
C jbs =C J 1+
ψ0

CJ is the junction capacitance at zero bias and is highly process-dependent.

MJ is the junction grading coefficient, typically in the range of 0.5 to 0.33 depending on the abruptness of the
diffusion junction.
Ψ0 is the built-in potential that depends on doping levels.

N A ND
ψ 0=v T ln 2
ni
vT is the thermal voltage
 KT
v T=
q
where k = 1.380 ×10–23 J/K is Boltzmann’s constant, T is absolute temperature (300 K at room temperature),
and q = 1.602 × 10–19 C is the charge of an electron. NA and ND are the doping levels of the body and source
diffusion region. ni is the intrinsic carrier concentration in undoped silicon and has a value of 1.45 × 10 10 cm–3
at 300 K.
The sidewall capacitance term is of a similar form but uses different coefficients.

[ ]
−M
V sbJSW

C jbssw =C JSW 1+
ψ SW

DC Transfer Characteristics
DC transfer characteristics of a circuit relate the output voltage to the input voltage, assuming the input changes
slowly enough that capacitances have plenty of time to charge or discharge. Specific ranges of input and output
voltages are defined as valid 0 and 1 logic levels.

Static CMOS Inverter DC Characteristics

A complementary CMOS inverter is implemented as the series connection of a p-device and n-device as shown in
Figure. The source and the substrate (body) of the p-device is tied to the VDD rail, while the source and the
substrate of the n-device are connected to the ground. Thus, the devices do not suffer from any body effect. To
derive the DC transfer characteristics for the CMOS inverter, which depicts the variation of the output voltage
(Vout) as a function of the input voltage (Vin), one can identify five following regions of operation for the n -
transistor and p -transistor.

Fig.1 Static CMOS Inverter

Let Vtn and Vtp denote the threshold voltages of the n and p-devices respectively. The following voltages at the
gate and the drain of the two devices (relative to their respective sources) are all referred with respect to the
ground (or VSS), which is the substrate voltage of the n -device, namely

Vgsn =Vin , Vdsn =Vout, Vgsp =Vin -VDD , and Vdsp=Vout -VDD

The voltage transfer characteristic of the CMOS inverter is now derived with reference to the following five
regions of operation:

Region 1 : the input voltage is in the range 0 ≤ V ¿ <V tn. In this condition, the n -transistor is off, while the p -
transistor is in linear region (as −V DD <V gsp ←V DD +V tn)
 Fig.2 Variation of current in CMOS inverter with Vin

No actual current flows until Vin crosses Vtn . The operating point of the p -transistor moves from higher to lower
values of currents in linear zone. The output voltage is given by V out ≈ V DD , as may be seen from Fig.3.

Fig.3 Transfer characteristics of the CMOS inverter

Region 2 : The input voltage is in the range V tn ≤ V ¿ <V inv. The upper limit of Vin is Vinv , the logic threshold
voltage of the inverter. The logic threshold voltage or the switching point voltage of an inverter denotes the
boundary of "logic 1" and "logic 0". It is the output voltage at which Vin = Vout. In this region, the n-transistor
moves into saturation, while the p-transistor remains in linear region. The total current through the inverter
increases, and the output voltage tends to drop fast
Region 3 : In this region, V ¿ ≈ V inv . Both the transistors are in saturation, the drain current attains a maximum
value, and the output voltage falls rapidly. The inverter exhibits gain. But this region is inherently unstable. As
both the transistors are in saturation, equating their currents, one gets (as V gsn=V inv , V gsp=V inv−V DD).
1 2 1 2
β n ( V inv−V tn ) = β p ( V inv−V DD−V tp )
2 2
 W E E µ
Where β=K and K= ins 0 . Solving for the logic threshold voltage Vinv , one gets
L D

Note that if and , then Vinv =0.5 VDD .

Region 4 : In this region, . As the input voltage Vin is increased beyond Vinv , the n -transistor
leaves saturation region and enters linear region, while the p -transistor continues in saturation. The magnitude of
both the drain current and the output voltage drops.
Region 5 : In this region, . At this point, the p -transistor is turned off, and the n -transistor
is in linear region, drawing a small current, which falls to zero as Vin increases beyond VDD -| Vtp|, since the p -
transistor turns off the current path. The output in this region is .

As may be seen from the transfer curve in Fig.3, the transition from "logic 1" state (represented by regions 1 and
2) to “logic 0” state (represented by regions 4 and 5) is quite steep. This characteristic guarantees maximum noise
immunity.

Beta Ratio Effects (βn / βp)

One can explore the variation of the transfer characteristic as a function of the ratio . As noted from the
above equation, the logic threshold voltage Vinv depends on the ratio . The CMOS inverter with the
ratio =1 allows a capacitive load to charge and discharge in equal times by providing equal current-source
and current-sink capabilities. Consider the case of >1. Keeping fixed, if one increases , then the
impedance of the pull-down n -transistor decreases. It conducts faster, leading to faster discharge of the capacitive
load. This ensures quicker fall of the output voltage Vout , as Vin increases from 0 volt onwards. That is, the transfer
characteristic shifts leftwards. Similarly, for a CMOS inverter with <1, the transfer curve shifts rightwards.
This is portrayed in Fig.4.
 Fig.4 Variation of shape of transfer characteristic of the CMOS inverter with the ratio β n/βp

Noise margin
Noise margin is a parameter intimately related to the transfer characteristics. It allows one to estimate the
allowable noise voltage on the input of a gate so that the output will not be affected. Noise margin (also called
noise immunity) is specified in terms of two parameters - the low noise margin NML , and the high noise
margin NMH . Referring to Fig.5, NMl is defined as the difference in magnitude between the maximum LOW
input voltage recognized by the driven gate and the maximum LOW output voltage of the driving gate. That is,

NML =| VILmax - VOLmax |

Similarly, the value of NMH is the difference in magnitude between the minimum HIGH output voltage of the
driving gate and the minimum HIGH input voltage recognizable by the driven gate. That is,

NMH =| VOHmin - VIHmin |

Where VIHmin : minimum HIGH input voltage

VILmax : maximum LOW input voltage

VOHmin : minimum HIGH output voltage

VOLmax : maximum LOW output voltage

 Fig.5 Definition of noise margin

Ideally, if one desires to have V IH =VIL , and VOL =VOH in the middle of the logic swing, then the switching of
states should be abtrupt, which in turn requires very high gain in the transition region. To calculate V IL , the
inverter is supposed to be in region 2 (referring to Fig.3) of operation, where the p -transistor is in linear zone
while the n -transistor is in saturation. The parameter V IL is found out by considering the unity gain point on the
inverter transfer characteristic where the output makes a transition from V OH . Similarly, the parameter VIH is
found by considering the unity gain point at the VOL end of the characteristic.

If the noise margins NMH or NML are reduced to a low value, then the gate may be susceptible to switching noise
that may be present at the inputs. The net effect of noise sources and noise margins on cascaded gates must be
considered in estimating the overall noise immunity of a particular system. Not infrequently, noise margins are
compromised to improve speed.

Scaling
The reduction of the size, i.e., the dimensions of MOSFETs, is commonly referred to as scaling.
1.1) Transistor Scaling
Dennard’s Scaling Law predicts that the basic operational characteristics of a MOS transistor can be preserved and
the performance improved if the critical parameters of a device are scaled by a dimensionless factor S. These
parameters include the following:
 All dimensions (in the x, y, and z directions)
 Device voltages
 Doping concentration densities

Constant field scaling (Full Scaling):

 In constant field scaling, electric fields remain the same as both voltage and distance shrink.
 1/S scaling is applied to all dimensions, device voltages and concentration densities.
 Ids per transistor are scaled by 1/S.
 No. of transistors per unit area is scaled by S2.
 Current density is scaled by S and power density remains constant.
 o e.g., ( 1
)  S2
1
S
Lateral scaling (gate-shrink):
S
  Another approach is lateral scaling, in which only the gate length is scaled.
 This is commonly called as gate shrink, because it can be done easily to
an existing mask database for a design.
 Ids per transistor are scaled by S.
 No. of transistors per unit area is scaled by S.
 Current density is scaled by S2 and power density is scaled by S2.
 The industry generally scales process generations with 30% shrink.
 It reduces the cost (area) of a transistor by a factor of two.
 A 5% gate shrink (S = 1.05) is commonly applied as a process, becomes
mature to boost the speed of components in that process.
Constant voltage scaling: V DD is held constant, while process is scaled.
 Constant voltage scaling (Fixed scaling) offers quadratic delay
improvement as well as cost reduction.
 It is also maintaining continuity in I/O voltage standards. Constant voltage
scaling increases the electric fields in devices.
 Ids per transistor are scaled by S.
 No. of transistors per unit area is scaled by S2.
 Current density is scaled by S3 and power density is scaled by S3.
 A 30% shrink with Dennard scaling improves clock frequency by 40%
and cuts power consumption per gate by a factor of 2.
Maintaining a constant field has the further benefit, that many nonlinear factors and wear out
mechanisms are unaffected.
Influence of scaling on MOS device characteristics
Voltage scaling with feature size

Feature sizes were shrunk from 6 µm to 1 µm while maintaining a 5 V supply voltage. This
constant voltage scaling offered quadratic delay improvement as well as cost reduction. It also
maintained continuity in I/O voltage standards. Constant voltage scaling increased the electric
fields in devices. By the 1 µm generation, velocity saturation was severe enough that decreasing
feature size no longer improved device current. Device breakdown from the high field was
another risk. And power consumption became unacceptable.
Therefore, Dennard scaling has been the rule since the half-micron node. A 30% shrink with
Dennard scaling improves clock frequency by 40% and cuts power consumption per gate by a
factor of 2. Maintaining a constant field has the further benefit that many nonlinear factors and
wearout mechanisms are essentially unaffected. Unfortunately, voltage scaling has dramatically
slowed since the 90 nm generation because of leakage, and this may ultimately limit CMOS
scaling.

Interconnect Scaling
Wires also tend to be scaled equally in width and thickness to maintain an aspect ratio close to 2.
Table shows the resistance, capacitance, and delay per unit length.

Wires can be classified as

 local
 semiglobal
 global

Local wires run within functional units and use the bottom layers of metal.
Semiglobal (or scaled) wires run across larger blocks or cores, typically using middle layers of
metal. Both local and semiglobal wires scale with feature size.
Global wires run across the entire chip using upper levels of metal.

Most local wires are short enough that their resistance does not matter. Like gates, their
capacitance per unit length is remaining constant, so their delay is improving just like gates.
Semiglobal wires long enough to require repeaters are speeding up, but not as fast as gates. This
is a relatively minor problem. Global wires, even with optimal repeaters, are getting slower as
technology scales.

Influence of scaling on interconnect characteristics

Power
Definitions
The instantaneous power P (t) consumed or supplied by a circuit element is the product of the
current through the element and the voltage across the element

The energy consumed or supplied over some time interval T is the integral of the instantaneous
power
The average power over this interval is

Suppose that the gate switches at some average frequency fsw. Over some interval T, the load will
be charged and discharged Tfsw times. The average power dissipation is

This is called the dynamic power because it arises from the switching of the load. Because most
gates do not switch every clock cycle, it is often more convenient to express switching frequency
fsw as an activity factor α times the clock frequency f. Now, the dynamic power dissipation may
be rewritten as

The activity factor is the probability that the circuit node transitions from 0 to 1, because that is
the only time the circuit consumes power.

Sources of Power Dissipation

Power dissipation in CMOS circuits comes from two components:
Dynamic dissipation due to
○ charging and discharging load capacitances as gates switch
○ “short-circuit” current while both pMOS and nMOS stacks are partially ON

Static dissipation due to

○ subthreshold leakage through OFF transistors
○ gate leakage through gate dielectric
○ junction leakage from source/drain diffusions
○ contention current in ratioed circuits
Putting this together gives the total power of a circuit

Power can also be considered in active, standby, and sleep modes. Active power is the power
consumed while the chip is doing useful work. It is usually dominated by Pswitching. Standby power
is the power consumed while the chip is idle. If clocks are stopped and ratioed circuits are
disabled, the standby power is set by leakage. In sleep mode, the supplies to unneeded circuits
are turned off to eliminate leakage. This drastically reduces the sleep power required, but the
chip requires time and energy to wake up so sleeping is only viable if the chip will idle for long
enough.

Dynamic Power
Dynamic power is

It consists mostly of the switching power, given in Equation,

The supply voltage VDD and frequency f are readily known by the designer. Activity factors can
be heavily dependent on the particular task being executed. As VDD is a quadratic term, it is good
to select the minimum VDD that can support the required frequency of operation. Likewise, we
choose the lowest frequency of operation that achieves the desired end performance. The activity
factor is mainly reduced by putting unused blocks to sleep. Finally, the circuit may be optimized
to reduce the overall load capacitance of each section.

Dynamic power also includes a short-circuit power component caused by power rushing from
VDD to GND when both the pullup and pulldown networks are partially ON while a transistor
switches.

Switching power is consumed by delivering energy to charge a load capacitance, then dumping
this energy to GND.

Static Power
Static power is consumed even when a chip is not switching.

1.1) Static Power Sources

Static power arises from subthreshold, gate, and junction leakage currents and contention
current.

1.1.1) Subthreshold Leakage

Subthreshold leakage current flows when a transistor is supposed to be OFF. For Vds exceeding a
few multiples of the thermal voltage (e.g., Vds > 50 mV), it can be simplified to

where Ioff is the subthreshold current at Vgs = 0 and Vds = VDD, and S is the subthreshold slope If
Vds is small, Isub may decrease by roughly an order of magnitude from Ioff. kγ is the body effect
coefficient, which describes how the body effect modulates the threshold voltage. Raising the
source voltage or applying a negative body voltage can further decrease leakage. The leakage
through two or more series transistors is dramatically reduced on account of the stack effect.

1.1.2) Gate Leakage

Gate leakage occurs when carriers tunnel through a thin gate dielectric when a voltage is applied
across the gate (e.g., when the gate is ON). Gate leakage is an extremely strong function of the
dielectric thickness. It is normally limited to acceptable levels in the process by selection of the
dielectric thickness. Gate leakage also depends on the voltage across the gate.

(a) (b)
Gate leakage in series stack

Figure shows two series transistors. If N1 is ON and N2 is OFF, N1 has Vgs=VDD and experiences
full gate leakage. On the other hand, if N1 is OFF and N2 is on, N2 has Vgs = Vt and experiences
negligible gate leakage. In both cases, the OFF transistor has no gate leakage. Thus, gate leakage
can be alleviated by stacking transistors such that the OFF transistor is closer to the rail.

1.1.3) Junction Leakage

Junction leakage occurs when a source or drain diffusion region is at a different potential from
the substrate. Junction leakage is often minor in comparison to the other leakages, but can be
expressed in nA/µm of transistor width when it needs to be considered.

1.1.4) Contention Current

Static CMOS circuits have no contention current. However, certain alternative circuits inherently
draw current even while quiescent. Current-mode logic and many analog circuits also draw static
current. Such circuits should be turned OFF in sleep mode by disabling the pull ups or current
source.