BC68F2123v140

Sub-1GHz OOK RF Transmitter Flash MCU
BC68F2123
Revision: V1.40 Date: October 29, 2020

BC68F2123
Table of Contents
Features.................................................................................................................. 5
CPU Features................................................................................................................................5
Peripheral Features........................................................................................................................5
RF Transmitter Features................................................................................................................5
General Description............................................................................................... 6
Block Diagram........................................................................................................ 6
Device Connection Diagram..........................................................................................................6
Functional Block Diagram..............................................................................................................7
Pin Assignment...................................................................................................... 7
Pin Description...................................................................................................... 7
Interconnection Signal Description.................................................................................................9
Absolute Maximum Ratings.................................................................................. 9

D.C. Characteristics............................................................................................... 9
A.C. Characteristics............................................................................................. 10
LVD/LVR Electrical Characteristics.................................................................... 11
Power-on Reset Characteristics......................................................................... 11
RF Characteristics............................................................................................... 12
D.C. Characteristics.....................................................................................................................12
A.C. Characteristics.....................................................................................................................12
I2C Characteristics........................................................................................................................13
System Architecture............................................................................................ 14
Clocking and Pipelining................................................................................................................14
Program Counter..........................................................................................................................15
Stack............................................................................................................................................15
Arithmetic and Logic Unit – ALU..................................................................................................16
Flash Program Memory....................................................................................... 16

Structure.......................................................................................................................................16
Special Vectors............................................................................................................................17
Look-up Table...............................................................................................................................17
Table Program Example...............................................................................................................17
In Circuit Programming – ICP......................................................................................................18
On-Chip Debug Support – OCDS................................................................................................19
Data Memory........................................................................................................ 20
Structure.......................................................................................................................................20
General Purpose Data Memory...................................................................................................20
Special Purpose Data Memory....................................................................................................21
Special Function Register Description.............................................................. 22

Indirect Addressing Registers – IAR0, IAR1................................................................................22
Bank Pointer – BP........................................................................................................................23
Accumulator – ACC......................................................................................................................23
Rev. 1.40 2 October 29, 2020

BC68F2123
Program Counter Low Register – PCL.........................................................................................23

Look-up Table Registers – TBLP, TBLH.......................................................................................23
Status Register – STATUS...........................................................................................................24
EEPROM Data Memory........................................................................................ 26

EEPROM Data Memory Structure...............................................................................................26
EEPROM Registers.....................................................................................................................26
Reading Data from the EEPROM................................................................................................28
Writing Data to the EEPROM.......................................................................................................28
Write Protection............................................................................................................................28
EEPROM Interrupt.......................................................................................................................28
Programming Considerations.......................................................................................................29
Oscillators............................................................................................................ 30
Oscillator Overview......................................................................................................................30
System Clock Configurations.......................................................................................................30
Internal RC Oscillator – HIRC......................................................................................................31
Internal 32kHz Oscillator – LIRC..................................................................................................31
Supplementary Oscillator.............................................................................................................31
Operating Modes and System Clocks............................................................... 31

System Clocks.............................................................................................................................31
System Operation Modes.............................................................................................................32
Control Register...........................................................................................................................33
Operating Mode Switching ..........................................................................................................35
Standby Current Considerations..................................................................................................38
Wake-up.......................................................................................................................................38
Watchdog Timer................................................................................................... 39
Watchdog Timer Clock Source.....................................................................................................39
Watchdog Timer Control Register................................................................................................39
Watchdog Timer Operation..........................................................................................................40
Reset and Initialisation........................................................................................ 41

Reset Functions...........................................................................................................................41
Reset Initial Conditions................................................................................................................44
Input/Output Ports............................................................................................... 46
Pull-high Resistors.......................................................................................................................47
Port A Wake-up............................................................................................................................47
I/O Port Input/Output Control ......................................................................................................48
Pin-shared Functions...................................................................................................................48
I/O Pin Structures.........................................................................................................................50
Timer Modules – TM............................................................................................ 51

Introduction..................................................................................................................................51
TM Operation...............................................................................................................................52
TM Clock Sources........................................................................................................................52
TM Interrupts................................................................................................................................52
TM External Pins..........................................................................................................................52
Rev. 1.40 3 October 29, 2020

BC68F2123
Standard Type TM – STM.................................................................................... 54

Standard TM Operation................................................................................................................54
Standard Type TM Register Description......................................................................................55
Standard Type TM Operating Modes...........................................................................................59
Periodic Type TM – PTM...................................................................................... 69

Periodic TM Operation.................................................................................................................69
Periodic Type TM Register Description........................................................................................70
Periodic Type TM Operating Modes.............................................................................................74
Interrupts.............................................................................................................. 83
Interrupt Registers........................................................................................................................83
Interrupt Operation.......................................................................................................................86
External Interrupt..........................................................................................................................87
Time Base Interrupts....................................................................................................................87
Multi-function Interrupts................................................................................................................88
EEPROM Write Interrupt..............................................................................................................88
TM Interrupts................................................................................................................................89
Interrupt Wake-up Function..........................................................................................................89
Low Voltage Detector – LVD............................................................................... 90

LVD Register................................................................................................................................90
LVD Operation..............................................................................................................................91
RF Transmitter..................................................................................................... 91
State Control................................................................................................................................92
RF Transmitter Module Registers................................................................................................94
Application Circuits............................................................................................. 98
Instruction Set...................................................................................................... 99
Introduction..................................................................................................................................99
Instruction Timing.........................................................................................................................99
Moving and Transferring Data......................................................................................................99
Arithmetic Operations...................................................................................................................99
Logical and Rotate Operation....................................................................................................100
Branches and Control Transfer..................................................................................................100
Bit Operations............................................................................................................................100
Table Read Operations..............................................................................................................100
Other Operations........................................................................................................................100
Instruction Set Summary.................................................................................. 101

Table Conventions......................................................................................................................101
Instruction Definition......................................................................................... 103

Package Information......................................................................................... 112
16-pin NSOP (150mil) Outline Dimensions (Exposed Pad)....................................................... 113
Rev. 1.40 4 October 29, 2020

BC68F2123
Features
CPU Features
• Operating Voltage
♦ fSYS=8MHz: 2.2V~3.6V
• Up to 0.5μs instruction cycle with 8MHz system clock
• Power down and wake-up functions to reduce power consumption
• Oscillator types
♦ Internal High Speed 8MHz RC – HIRC
♦ Internal Low Speed 32kHz RC – LIRC
• Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP
• Fully integrated internal oscillators require no external components
• All instructions executed in one or two instruction cycles
• Table read instructions
• 61 powerful instructions
• 2-level subroutine nesting
• Bit manipulation instruction
Peripheral Features
• Flash Program Memory: 1K×14
• RAM Data Memory: 64×8
• True EEPROM Memory: 32×8
• Watchdog Timer function
• 9 bidirectional I/O lines
• One pin-shared external interrupt
• Multiple Timer Modules for time measurement, input capture, compare match output or PWM
output or single pulse output function
• Dual Time-Base functions for generation of fixed time interrupt signals
• Low voltage reset function
• Low voltage detect function
• Flash program memory can be re-programmed up to 10,000 times
• Flash program memory data retention > 10 years
• True EEPROM data memory can be re-programmed up to 100,000 times
• True EEPROM data memory data retention > 10 years
• Package type: 16-pin NSOP-EP
RF Transmitter Features
• Operating voltage range: 2.2V~3.6V @Ta=-40˚C~+85˚C
• Frequency bands: 315MHz, 433MHz, 868MHz, 915MHz
• Output Power up to 13dBm
• TX Current consumption @433MHz: 11mA typical (OOK, 10dBm, 50% duty cycle)
• OOK symbol rate from 0.5Ksps to 25Ksps
• 4-step programmable TX Power: 0 / 5 / 10 / 13dBm
Rev. 1.40 5 October 29, 2020

BC68F2123
• I2C interface for RF transmitter configuration

• Fully integrated VCO, on chip loop filter and Fractional-N PLL synthesizer
• FCC / ETSI Compliant
General Description
The BC68F2123 is an OOK transmitter MCU for remote wireless applications in the 315MHz,
433MHz, 868MHz and 915MHz frequency bands.
The MCU is a Flash memory type 8-bit high performance RISC architecture microcontroller and
offers users the convenience of Flash memory multi-programming features. It includes an area of
RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile data
such as serial numbers, calibration data etc. The device includes multiple and extremely flexible
Timer Modules, internal oscillators, Time Base functions, low voltage reset, low voltage detection
and Watchdog Timer functions.
The OOK transmitter can be used for remote wireless applications in the 315MHz, 433MHz,
868MHz and 915MHz frequency bands. It is a highly integrated and low cost solution for one-way
transmitters.
The inclusion of flexible I/O programming features along with many other features of the MCU,
ensure that the device only requires a simple peripheral for use in consumer, industrial automation
and high-performance unidirectional wireless link applications.
Block Diagram
The following block diagram illustrates the structure of the device.
Device Connection Diagram

VDD DVDDRF VDDRF
PA0
PA1
PB2 SCL/PCLK
PA2
RFOUT
PA5
HOLTEK RF
PA6
MCU Part
XOIN
PA7
PB3 SDA/DIN
PB0
PB1
PB5
EP
VSS VSSRF_PA
Rev. 1.40 6 October 29, 2020

BC68F2123
Functional Block Diagram
Reset ROM RAM

RES 1K × 14 64 × 8 PA0~PA2,
Circuit Timers Port A Driver
PA5~PA7
Pin-Shared
EEPROM Stack Function
Interrupt 32 × 8 2-level PB0, PB1,
INT I/O Port B Driver
Controller PB5
Watchdog
Pin-Shared LVD/LVR Digital Peripherals
Timer
With Port A DVDDRF
BUS
HT8 MCU Core
VDDRF
SYSCLK
Digital Loop RFOUT
CP/PFD PA
Control Logic Filter
LIRC VSSRF_PA
Time 32kHz MMD
MUX
Bases Digital
VSS VSS
HIRC Demodulator XOIN
RF Synthesizer
VDD VDD 8MHz
Clock System RF Peripherals EP
: Pin-Shared Node EP : Exposed pad, must be connected to ground
Pin Assignment
VDD 1 16 VSS
PA7/PTCK1/STP0B/RES 2 15 PA0/STP0I/OCDSDA/ICPDA
PA6/PTCK1/STP0I/STP0 3 14 PA1
PA5/INT/PTP1I 4 13 PA2/INT/STCK0/OCDSCK/ICPCK
EP
PB5/PTP1 5 12 PB0/PTP1I
DVDDRF 6 11 PB1/PTCK1/STP0B
RFOUT 7 10 XOIN
VSSRF_PA 8 9 VDDRF
BC68F2123/BC68V2123
16 NSOP-EP-A
Note: 1. If the pin-shared pin functions have multiple outputs, the desired pin-shared function is determined by the
corresponding software control bits.
2. The OCDSDA and OCDSCK pins are used as the OCDS dedicated pins and only available for the
BC68V2123 device which is the OCDS EV chip of the BC68F2123.
3. For the unbonded pins, PA3, PA4 and PB4, the pin status should be properly configured to avoid
unwanted power consumption resulting from floating input conditions. Refer to the “Standby Current
Considerations” and “Input/Output Ports” sections.
Pin Description
The function of each pin is listed in the following table, however the details behind how each pin is
configured is contained in other sections of the datasheet.
Pin Name Function OPT I/T O/T Description
PAWU General purpose I/O. Register enabled pull-up and
PA0 ST CMOS
PAPU wake-up
PA0/STP0I/ STP0I IFS0 ST — TM0 (STM) input
OCDSDA/ICPDA
OCDSDA — ST CMOS On Chip Debug System Data Line (OCDS EV only)
ICPDA — ST CMOS ICP Data Line
PA1 PA1 ST CMOS
PAPU wake-up
Rev. 1.40 7 October 29, 2020

BC68F2123
Pin Name Function OPT I/T O/T Description

PA2 ST CMOS
PAPU wake-up
PA2/INT/STCK0/ INT IFS0 ST — External interrupt input
OCDSCK/ICPCK STCK0 IFS0 ST — TM0 (STM) clock input
OCDSCK — ST — On Chip Debug System Clock Line (OCDS EV only)
ICPCK — ST — ICP Clock Line
PA5 ST CMOS
PAPU wake-up
PA5/INT/PTP1I
INT IFS0 ST — External interrupt input
PTP1I IFS0 ST — TM1 (PTM) input
PAWU
General purpose I/O. Register enabled pull-up and
PA6 PAPU ST CMOS
wake-up
PASR
PA6/PTCK1/STP0I/ PASR
PTCK1 ST — TM1 (PTM) clock input
STP0 IFS0
PASR
STP0I ST — TM0 (STM) input
IFS0
STP0 PASR — CMOS TM0 (STM) output
PAWU
General purpose I/O. Register enabled pull-up and
PA7 PAPU ST CMOS
wake-up
PASR
PA7/PTCK1/STP0B/ PASR
RES PTCK1 ST — TM1 (PTM) clock input
IFS0
STP0B PASR — CMOS TM0 (STM) inverted output
RES RSTC ST — External reset pin
PB0 PBPU ST CMOS General purpose I/O. Register enabled pull-up
PB0/PTP1I
PTP1I IFS0 ST — TM1 (PTM) input
PBPU
PB1 ST CMOS General purpose I/O. Register enabled pull-up
PBSR
PB1/PTCK1/STP0B PBSR
PTCK1 ST — TM1 (PTM) clock input
IFS0
STP0B PBSR — CMOS TM0 (STM) inverted output
PBPU
PB5 ST CMOS General purpose I/O. Register enabled pull-up
PB5/PTP1 PBSR
PTP1 PBSR — CMOS TM1 (PTM) output
RF Power Amplifier output, connect to matching
RFOUT PA_OUT — — AN
circuit
XOIN Crystal — AN — External crystal input
VSSRF_PA PA GND — PWR — RF GND
VDDRF PA VDD — PWR — RF Analog positive power supply
DVDDRF DVDD — PWR — RF Digital Positive power supply
VDD VDD — PWR — Digital positive power supply
VSS VSS — PWR — Digital negative power supply
EP EP — PWR — Exposed pad, must be connected to ground
Legend: I/T: Input type O/T: Output type
OPT: Optional by register option PWR: Power
ST: Schmitt Trigger input CMOS: CMOS output
AN: Analog signal
Rev. 1.40 8 October 29, 2020

BC68F2123
Interconnection Signal Description

Two lines are not connected to external package pins. These signal lines are interconnected between
the MCU and the RF transmitter and are listed in the following table.
MCU RF Transmitter Part Function Description
PB2 General purpose I/O
PB2 SCL/PCLK
SCL/PCLK Clock input line in RF transmitter I2C mode/normal mode
PB3 General purpose I/O
PB3 SDA/DIN
SDA/DIN Data input line in RF transmitter I2C mode/normal mode
Note: The PB2~PB3 lines, which are internally connected to the RF transmitter clock and data inputs,
SCL/PCLK and SDA/DIN, respectively should be properly configured to control the RF
transmitter operations. Refer to the “Input/Output Ports” and “RF Transmitter” chapters for
more details.
Absolute Maximum Ratings

Supply Voltage..................................................................................................VSS-0.3V to VSS+3.6V
Input Voltage (Digital)......................................................................................VSS-0.3V to VDD+0.3V
Input Voltage (Analog)............................................................................................. VSS-0.3V to 2.1V
Storage Temperature.....................................................................................................-50˚C to 125˚C
Operating Temperature...................................................................................................-40˚C to 85˚C
*ESD HBM...............................................................................................................................˃±2kV
* This RF transmitter is ESD sensitive. HBM (Human Body Mode) is based on the MIL-STD-883.
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute
Maximum Ratings" may cause substantial damage to the devices. Functional operation of
the devices at other conditions beyond those listed in the specification is not implied and
prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage — HIRC — fSYS =8MHz 2.2 — 3.6 V
No load, fSYS=fH, WDT enable,
— 1.0 2.0 mA
LVR enable
No load, fSYS=fH/2, WDT enable,
— 1.0 1.5 mA
LVR enable
No load, fSYS=fH/4, WDT enable,
— 0.9 1.3 mA
LVR enable
Operating Current, No load, fSYS=fH/8, WDT enable,
3V — 0.8 1.1 mA
Normal Mode, fH=8MHz (HIRC) LVR enable
IDD
No load, fSYS=fH/16,
— 0.7 1.0 mA
WDT enable, LVR enable
— 0.6 0.9 mA
— 0.5 0.8 mA
Operating Current, Slow Mode, No load, fSYS=LIRC,
3V — 20 30 μA
fSYS=fL=LIRC WDT enable , LVR enable
Rev. 1.40 9 October 29, 2020

BC68F2123
Test Conditions
VDD Conditions
SLEEP0 Mode Standby Current No load, WDT disable,
3V — 0.1 1.0 μA
(LIRC off) LVR disable
SLEEP1 Mode Standby Current No load, WDT enable,
3V — 1.3 3.0 μA
(LIRC on) LVR disable
ISTB
IDLE0 Mode Standby Current No load, WDT enable,
3V — 1.3 3.0 μA
(LIRC on) LVR disable
IDLE1 Mode Standby Current No load, WDT enable,
3V — 0.8 1.6 mA
(HIRC on) fSYS=8MHz on
Input Low Voltage for I/O Ports
— — 0 — 0.2VDD
VIL or Input Pins except RES pin V
Input Low Voltage (RES) — — 0 — 0.4VDD
Input High Voltage for I/O Ports
— — 0.8VDD — VDD
VIH or Input Pins except RES pin V
Input High Voltage (RES) — — 0.9VDD — VDD
IOL I/O Port Sink Current 3V VOL=0.1VDD 18 36 — mA
IOH I/O Port Source Current 3V VOL=0.9VDD -3 -6 — mA
Pull-high Resistance for I/O Ports 3V — 20 60 100
RPH Pull-high Resistance for kΩ
3V — 20 60 100
OCDSCK, OCDSDA Pins
Operating Current, Normal
IOCDS Mode, fSYS=fH(HIRC)(for OCDS 3V No load, fH=8MHz, WDT enable — 1.4 2.0 mA
EV testing, connect to an e-Link)
A.C. Characteristics
Ta=25°C, unless otherwise specified
Test Conditions
VDD Conditions
fCPU Operating Clock 2.2V~3.6V — DC — 8 MHz
3V Ta=25°C -2% 8 +2% MHz
3V Ta=0°C to 70°C -5% 8 +5% MHz
fHIRC System Clock (HIRC)
2.2V~3.6V Ta=0°C to 70°C -8% 8 +8% MHz
2.2V~3.6V Ta=-40°C to 85°C -12% 8 +12% MHz
fLIRC System Clock (LIRC) 2.2V~3.6V Ta=-40°C to 85°C 8 32 50 kHz
tTIMER xTCKn, xTPnI Input Pulse Width — — 0.3 — — μs
tRES External Reset Low Pulse Width — — 10 — — μs
tINT Interrupt Pulse Width — — 0.3 — — μs
tEERD EEPROM Read Time — — — 2 4 tSYS
tEEWR EEPROM Write Time — — — 4 10 ms
System Start-up Timer Period fSYS=HIRC 16 — —
tSST — tSYS
(Wake-up from HALT state where fSYS is off) fSYS=LIRC 2 — —
System Reset Delay Time
(Power On Reset, LVR Reset, WDT S/W — — 25 50 100 ms
tRSTD Reset(WDTC))
System Reset Delay Time
— — 8.3 16.7 33.3 ms
(RES Reset, WDT Normal Reset)
Note: 1. tSYS=1/fSYS
2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
Rev. 1.40 10 October 29, 2020

BC68F2123
LVD/LVR Electrical Characteristics

Ta=25°C
Test Conditions
VDD Conditions
VLVR Low Voltage Reset Voltage — LVR Enable, 2.1V option -5% 2.1 +5% V
ENLVD=1, VLVD=2.0V 2.0
VLVD Low Voltage Detector Voltage — -5% +5% V
tLVR Low Voltage Width to Reset — — 160 320 640 μs
— For LVR enable, LVD off→on — — 15 μs
tLVDS LVDO Stable Time
— For LVR disable, LVD off→on — — 150 μs
Power-on Reset Characteristics

Ta=25°C
Test Conditions
VDD Conditions
VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV
RRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms

Minimum Time for VDD Stays at VPOR to Ensure
tPOR — — 1 — — ms
Power-on Reset
VDD
tPOR RRPOR
VPOR
Time
Rev. 1.40 11 October 29, 2020

BC68F2123
RF Characteristics
D.C. Characteristics
Ta=25°C, VDDRF=3.3V, fXTAL=16MHz, OOK modulation with Matching circuit,
PAOUT is powered by VDDRF=3.3V, unless otherwise noted.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
TOP Operating Temperature — -40 — 85 °C
VDD Supply Voltage — 2.2 3.3 3.6 V
Digital I/Os
VIH High Level Input Voltage — 0.7×VDD — VDD V
VIL Low Level Input Voltage — 0 — 0.3×VDD V
VOH High Level Output Voltage IOH=-5mA 0.8×VDD — VDD V
VOL Low Level Output Voltage IOL=5mA 0 — 0.2×VDD V
Current Consumption
ISleep Deep Sleep Mode Current Consumption — — — 0.4 μA
IStandby Idle Mode Current Consumption XTAL on, PA off, Synthesizer on — 6.5 — mA
PRF=0dBm — 11 —
High Data Current Consumption
PRF=10dBm — 19 — mA
@ 315MHz (Data=1)
PRF=13dBm — 24 —
PRF=0dBm — 11 —
@ 433MHz (Data=1)
PRF=13dBm — 24 —
ITX
PRF=0dBm — 11 —
@ 868MHz (Data=1)
PRF=13dBm — 24 —
PRF=0dBm — 12 —
@ 915MHz (Data=1)
PRF=13dBm — 25 —
A.C. Characteristics
Ta=25°C, VDDRF=3.3V, fXTAL=16MHz, OOK modulation with Matching circuit,
PAOUT is powered by VDDRF=3.3V, unless otherwise noted.
Transmitter Characteristics
315MHz band — 315 —
433MHz band — 433.92 —
fRF RF Frequency Band MHz
868MHz band — 868.35 —
915MHz band — 915 —
SR Symbol Rate OOK modulation 0.5 — 25 ksps
433MHz band 0 — 13
PRF RF Transmit Output Power dBm
868MHz band 0 — 13
tST RF Transmit Settling Time Standby mode to Transmit mode — 370 — μs
EROOK OOK Extinction Ratio OOK modulation depth — 70 — dB
Output Blanking From Deep Sleep to Transmit mode — — 1 ms
One Shot Delay Time OOK 4 — 32 ms
Rev. 1.40 12 October 29, 2020

BC68F2123

f < 1GHz — — -36
47MHz < f < 74MHz
87.5MHz < f < 118MHz
S.E.TX TX Spurious Emission (PRF =10dBm) — — -54 dBm
174MHz < f < 230MHz
470MHz < f < 862MHz
2nd, 3rd Harmonic — — -30
LO Characteristics
315MHz band 290 — 335
fLO RF Frequency Coverage Range 433MHz band 415 — 490 MHz
868MHz band 830 — 960
fSTEP LO Frequency Resolution — — — 1 kHz
@ 100kHz offset — -76 —
433MHz Phase Noise
@ 1MHz offset — -104 — dBc/
PNLO
@ 100kHz offset — -70 — Hz
868MHz Phase Noise
@ 1MHz offset — -100 —
Crystal Oscillator
fXTAL XTAL Frequency — — 16 — MHz
ESR XTAL Equivalent Series Resistance — — — 100 Ω
CLOAD XTAL Capacitor Load — — 16 — pF
TOL (Note) XTAL Tolerance — -20 — +20 ppm
tSU XTAL Startup Time 49US XO — — 1 ms
Note: 1. This is the total tolerance including (1) Initial tolerance (2) Crystal loading (3) Aging and (4) Temperature
dependence.
2. The acceptable crystal tolerance depends on RF frequency and channel spacing/band width.
I2C Characteristics
Ta=-40°C~85°C
I2C Characteristics
fSCL Serial Clock Frequency — — — 1 MHz
tBUF Bus Free Time between Stop and Start Condition SCL=1MHz 250 — — ns
tLOW SCL Low Time SCL=1MHz 500 — — ns
tHIGH SCL High Time SCL=1MHz 500 — — ns
tsu(DAT) Data Setup Time SCL=1MHz 100 — — ns
tsu(STA) Start Condition Setup Time SCL=1MHz 250 — — ns
tsu(STO) Stop Condition Setup Time SCL=1MHz 250 — — ns
th(DAT) Data Hold Time SCL=1MHz 100 — — ns
th(STA) Start Condition Hold Time SCL=1MHz 250 — — ns
tr(SCL) Rise Time of SCL Signal SCL=1MHz — — 100 ns
tf(SCL) Fall Time of SCL Signal SCL=1MHz — — 100 ns
tr(SDA) Rise Time of SDA Signal SCL=1MHz — — 100 ns
tf(SDA) Fall Time of SDA Signal SCL=1MHz — — 100 ns
Rev. 1.40 13 October 29, 2020

BC68F2123
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to their internal system architecture. The device takes advantage of the usual features found within
RISC microcontrollers providing increased speed of operation and Periodic performance. The
pipelining scheme is implemented in such a way that instruction fetching and instruction execution
are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch
or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which
carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions,
etc. The internal data path is simplified by moving data through the Accumulator and the ALU.
Certain internal registers are implemented in the Data Memory and can be directly or indirectly
addressed. The simple addressing methods of these registers along with additional architectural
features ensure that a minimum of external components is required to provide a functional I/O
control system with maximum reliability and flexibility. This makes the device suitable for low-cost,
high-volume production for controller applications
Clocking and Pipelining

The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into four
internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the
beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecutive
instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the
contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the
instruction will take one more instruction cycle to execute.
Oscillator Clock
(System Clock)
Phase Clock T1
Phase Clock T2
Phase Clock T3
Phase Clock T4
Program Counter PC PC+1 PC+2
Pipelining
Fetch Inst. (PC)
Execute Inst. (PC-1) Fetch Inst. (PC+1)
Execute Inst. (PC) Fetch Inst. (PC+2)
Execute Inst. (PC+1)
System Clock and Pipelining
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
Rev. 1.40 14 October 29, 2020

BC68F2123
1 MOV A, [12H] Fetch Inst. 1 Execute Inst. 1

2 CALL DELAY Fetch Inst. 2 Execute Inst. 2
3 CPL [12H]
Fetch Inst. 3 Flush Pipeline
4 :
5 : Fetch Inst. 6 Execute Inst. 6
6 DELAY: NOP Fetch Inst. 7
Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the
next instruction to be executed. It is automatically incremented by one each time an instruction
is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a non-
consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low
Register, are directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is
obtained.
Program Counter
Program Counter High Byte PCL Register
PC9~PC8 PCL7~PCL0
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly, however, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory, that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is
needed to pre-fetch.
Stack
This is a special part of the memory which is used to save the contents of the Program Counter only.
The stack has two levels is neither part of the data nor part of the program space, and is neither
readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable
nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program
Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by
a return instruction, RET or RETI, the Program Counter is restored to its previous value from the
stack. After a device reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded
but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or
RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer
to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can
still be executed which will result in a stack overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program branching. If the stack is overflow, the first Program
Counter save in the stack will be lost.
Rev. 1.40 15 October 29, 2020

BC68F2123
Program Counter
Top of Stack
Stack Level 1
Stack Program Memory
Pointer Stack Level 2
Bottom of Stack
Arithmetic and Logic Unit – ALU

The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
• Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
• Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
• Increment and Decrement: INCA, INC, DECA, DEC
• Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
Flash Program Memory

The Program Memory is the location where the user code or program is stored. For the device the
Program Memory is Flash type, which means it can be programmed and re-programmed a large
number of times, allowing the user the convenience of code modification on the same device. By
using the appropriate programming tools, the Flash device offers users the flexibility to conveniently
debug and develop their applications while also offering a means of field programming and
updating.
Structure
The Program Memory has a capacity of 1K×14 bits. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt entries. Table data, which
can be setup in any location within the Program Memory, is addressed by a separate table pointer
register.
000H Reset
004H
Interrupt Vector
01CH
3FFH 14 bits
Program Memory Structure
Rev. 1.40 16 October 29, 2020

BC68F2123
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location
000H is reserved for use by the devices reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the address
of the look up data to be retrieved in the table pointer register, TBLP. This register defines the total
address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory using
the "TABRDC[m]" or "TABRDL[m]" instructions, respectively. When the instruction is executed,
the lower order table byte from the Program Memory will be transferred to the user defined
Data Memory register [m] as specified in the instruction. The higher order table data byte from
the Program Memory will be transferred to the TBLH special register. Any unused bits in this
transferred higher order byte will be read as "0".
The accompanying diagram illustrates the addressing data flow of the look-up table.
Last page or
present page
PC9~PC8 Program Memory
PC High Byte
Address
Data
14 bits
TBLP Register
Register TBLH User Selected

Register
Data High Byte Data Low Byte
Table Program Example

The following example shows how the table pointer and table data is defined and retrieved from the
microcontroller. This example uses raw table data located in the Program Memory which is stored
there using the ORG statement. The value at this ORG statement is "300H" which refers to the start
address of the last page within the 1K words Program Memory of the device. The table pointer is
setup here to have an initial value of "06H". This will ensure that the first data read from the data table
will be at the Program Memory address "306H" or 6 locations after the start of the last page. Note that
the value for the table pointer is referenced to the first address of the last page if the "TABRDL [m]"
instruction is being used. The high byte of the table data which in this case is equal to zero will be
transferred to the TBLH register automatically when the "TABRDL [m]" instruction is executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Rev. 1.40 17 October 29, 2020

BC68F2123
Table Read Program Example

tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
:
mov a,06h ; initialise low table pointer - note that this address is referenced
mov tblp,a ; to the last page or present page
:
:
tabrdl tempreg1 ; transfers value in table referenced by table pointer data at program
; memory address "306H" transferred to tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
tabrdl tempreg2 ; transfers value in table referenced by table pointer data at program
; memory address "305H" transferred to tempreg2 and TBLH in this
; example the data "1AH" is transferred to tempreg1 and data "0FH" to
; register tempreg2
:
:
org 300h ; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
In Circuit Programming – ICP

The provision of Flash type Program Memory provides the user with a means of convenient and easy
upgrades and modifications to their programs on the same device. As an additional convenience,
Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface.
This provides manufacturers with the possibility of manufacturing their circuit boards complete with
a programmed or un-programmed microcontroller, and then programming or upgrading the program
at a later stage. This enables product manufacturers to easily keep their manufactured products
supplied with the latest program releases without removal and re-insertion of the device.
Holtek Write Pins MCU Programming Pins Function
ICPDA PA0 Programming Serial Data
ICPCK PA2 Programming Serial Clock
VDD VDD Power Supply
VSS VSS Ground
The Program Memory can be programmed serially in-circuit using this 4-wire interface. Data
is downloaded and uploaded serially on a single pin with an additional line for the clock. Two
additional lines are required for the power supply and ground. The technical details regarding the
in-circuit programming of the device are beyond the scope of this document and will be supplied in
supplementary literature.
Rev. 1.40 18 October 29, 2020

BC68F2123
Writer Connector MCU Programming

Signals Pins
Writer_VDD VDD
ICPDA PA0
ICPCK PA2
Writer_VSS VSS
* *
To other Circuit
Note: * may be resistor or capacitor. The resistance of * must be greater than 1kΩ or the capacitance
of * must be less than 1nF.
On-Chip Debug Support – OCDS

There is an EV chip which is used to emulate the real device. This EV chip device also provides
an "On-Chip Debug" function to debug the device during the development process. The EV chip
and the actual MCU device are almost functionally compatible except for the "On-Chip Debug"
function. Users can use the EV chip device to emulate the real chip device behavior by connecting
the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is
the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin.
When users use the EV chip for debugging, other functions which are shared with the OCDSDA and
OCDSCK pins in the device will have no effect in the EV chip. However, the two OCDS pins which
are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins
for ICP. For more detailed OCDS information, refer to the corresponding document named "Holtek
e-Link for 8-bit MCU OCDS User’s Guide".
Holtek e-Link Pins EV Chip Pins Pin Description
OCDSDA OCDSDA On-chip Debug Support Data/Address input/output
OCDSCK OCDSCK On-chip Debug Support Clock input
VDD VDD Power Supply
GND VSS Ground
Rev. 1.40 19 October 29, 2020

BC68F2123
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored.
Structure
Divided into two sections, the first of these is an area of RAM, known as the Special Function Data
Memory. Here are located registers which are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some
remain protected from user manipulation. The second area of Data Memory is known as the General
Purpose Data Memory, which is reserved for general purpose use. All locations within this area are
read and write accessible under program control.
The overall Data Memory is subdivided into two banks. The Special Purpose Data Memory registers
are accessible in all banks, with the exception of the EEC register at address 40H, which is only
accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the
Bank Pointer to the correct value. The start address of the Data Memory is the address 00H.
MCU Special Purpose MCU General Purpose
Data Memory Data Memory
Located Banks Capacity Address
0, 1 64×8 Bank 0: 40H~7FH
Data Memory Summary
00H
Special Purpose
Data Memory
(Bank 0 & Bank 1)
3FH
40H Bank 1
General Purpose
Data Memory
(Bank 0)
7FH Bank 0
Data Memory Structure
General Purpose Data Memory

There is a 64 byte general purpose data memory which is arranged in Bank 0. All microcontroller
programs require an area of read/write memory where temporary data can be stored and retrieved for
use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area
of Data Memory is fully accessible by the user programing for both reading and writing operations.
By using the bit operation instructions individual bits can be set or reset under program control
giving the user a large range of flexibility for bit manipulation in the Data Memory.
Rev. 1.40 20 October 29, 2020

BC68F2123
Special Purpose Data Memory

This area of Data Memory is where registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are both readable and writeable but some are
protected and are readable only, the details of which are located under the relevant Special Function
Register section. Note that for locations that are unused, any read instruction to these addresses will
return the value "00H".
Bank0 & Bank1 Bank0 & Bank1
00H IAR0 20H
01H MP0 21H
02H IAR1 22H
03H MP1 23H
04H BP 24H
05H ACC 25H RSTC
06H PCL 26H PASR
07H TBLP 27H PBSR
08H TBLH 28H STM0C0
09H 29H STM0C1
0AH STATUS 2AH STM0DL
0BH SMOD 2BH STM0DH
0CH LVDC 2CH STM0AL
0DH INTEG 2DH STM0AH
0EH INTC0 2EH

0FH INTC1 2FH PB
10H 30H PBC
11H MFI0 31H PBPU
12H MFI1 32H PTM1C0
13H 33H PTM1C1
14H PA 34H PTM1DL
15H PAC 35H PTM1DH
16H PAPU 36H PTM1AL
17H PAWU 37H PTM1AH
18H IFS0 38H PTM1RPL
19H WDTC 39H PTM1RPH
1AH 3AH
1BH TBC
1CH SMOD1
1DH
1EH EEA
1FH EED 3FH
40H EEC
: Unused, read as “00”
Special Purpose Data Memory Structure
Rev. 1.40 21 October 29, 2020

BC68F2123
Special Function Register Description

Most of the Special Function Register details will be described in their relevant functional section,
however several registers require a separate description in this section.
Indirect Addressing Registers – IAR0, IAR1

The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal Data
Memory register space, do not actually physically exist as normal registers. The method of indirect
addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory
Pointers, in contrast to direct memory addressing, where the actual memory address is specified.
Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these
registers but rather to the memory location specified by their corresponding Memory Pointers, MP0
or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1
and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not
physically implemented, reading the Indirect Addressing Registers indirectly will return a result of
"00H" and writing to the registers indirectly will result in no operation.
Memory Pointers – MP0, MP1

Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be manipulated in the same way as normal
registers providing a convenient way with which to address and track data. When any operation to
the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller
is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to
access data from all banks according to BP register. Direct Addressing can only be used with Bank 0,
all other Banks must be addressed indirectly using MP1 and IAR1.
The following example shows how to clear a section of four Data Memory locations already defined
as locations adres1 to adres4.
Indirect Addressing Program Example

data .section ´data´
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 ´code´
org 00h
start:
mov a,04h ; setup size of block
mov block,a
mov a,offset adres1 ; Accumulator loaded with first RAM address
mov mp0,a ; setup memory pointer with first RAM address
loop:
clr IAR0 ; clear the data at address defined by mp0
inc mp0 ; increment memory pointer
sdz block ; check if last memory location has been cleared
jmp loop
continue:
The important point to note here is that in the example shown above, no reference is made to specific
Data Memory addresses.
Rev. 1.40 22 October 29, 2020

BC68F2123
Bank Pointer – BP
For this device, the Data Memory is divided into two banks, Bank0 and Bank1. Selecting the
required Data Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer is used to
select Data Memory Banks 0~1.
The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the IDLE
or SLEEP Mode, in which case, the Data Memory bank remains unaffected. It should be noted
that the Special Function Data Memory is not affected by the bank selection, which means that the
Special Function Registers can be accessed from within any bank. Directly addressing the Data
Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer.
Accessing data from Bank1 must be implemented using Indirect Addressing.
• BP Register
Bit 7 6 5 4 3 2 1 0
Name — — — — — — — DMBP0
R/W — — — — — — — R/W
POR — — — — — — — 0
Bit 7~1 Unimplemented, read as "0"

Bit 0 DMBP0: Select Data Memory Bank
0: Bank 0
1: Bank 1
Accumulator – ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user-defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register – PCL

To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Look-up Table Registers – TBLP, TBLH

These two special function registers are used to control operation of the look-up table which is
stored in the Program Memory. TBLP is the table pointer and indicate the location where the table
data is located. Its value must be setup before any table read commands are executed. Its value
can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data
pointing and reading. TBLH is the location where the high order byte of the table data is stored
after a table read data instruction has been executed. Note that the lower order table data byte is
transferred to a user defined location.
Rev. 1.40 23 October 29, 2020

BC68F2123
Status Register – STATUS

This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation
and system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing
the "HALT" or "CLR WDT" instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
• C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
• PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by
executing the "HALT" instruction.
• TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is
set by a WDT time-out.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the subroutine can corrupt the status register, precautions must be taken to correctly save it.
Rev. 1.40 24 October 29, 2020

BC68F2123
• STATUS Register
Bit 7 6 5 4 3 2 1 0
Name — — TO PDF OV Z AC C
R/W — — R R R/W R/W R/W R/W
POR — — 0 0 x x x x
"x": unknown
Bit 5 TO: Watchdog Time-out flag
0: After power up or executing the "CLR WDT" or "HALT" instruction
1: A watchdog time-out occurred.
Bit 4 PDF: Power down flag
0: After power up or executing the "CLR WDT" instruction
1: By executing the "HALT" instruction
Bit 3 OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Bit 2 Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1 AC: Auxiliary flag
0: No auxiliary carry
1: An operation results in a carry out of the low nibbles in addition, or no borrow
from the high nibble into the low nibble in subtraction
Bit 0 C: Carry flag
0: No carry-out
1: An operation results in a carry during an addition operation or if a borrow does
not take place during a subtraction operation
The "C" flag is also affected by a rotate through carry instruction.
Rev. 1.40 25 October 29, 2020

BC68F2123
EEPROM Data Memory

This device contains an area of internal EEPROM Data Memory. EEPROM, is by its nature a non-
volatile form of re-programmable memory, with data retention even when its power supply is
removed. By incorporating this kind of data memory, a whole new host of application possibilities
are made available to the designer. The availability of EEPROM storage allows information such
as product identification numbers, calibration values, specific user data, system setup data or other
product information to be stored directly within the product microcontroller. The process of reading
and writing data to the EEPROM memory has been reduced to a very trivial affair.
EEPROM Data Memory Structure

The EEPROM Data Memory capacity is 32×8 bits for the device. Unlike the Program Memory and
RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and
is therefore not directly addressable in the same way as the other types of memory. Read and Write
operations to the EEPROM are carried out in single byte operations using an address and a data
register in Bank 0 and a single control register in Bank 1.
EEPROM Registers
Three registers control the overall operation of the internal EEPROM Data Memory. These are the
address registers, EEA, the data register, EED and a single control register, EEC. As both the EEA
and EED registers are located in Bank 0, they can be directly accessed in the same way as any other
Special Function Register. The EEC register however, being located in Bank1, cannot be directly
addressed and can only be read from or written to indirectly using the MP1 Memory Pointer and
Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in
Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register,
BP, set to the value, 01H, before any operations on the EEC register are executed.
Register Bit
Name 7 6 5 4 3 2 1 0
EEA — — — EEA4 EEA3 EEA2 EEA1 EEA0
EED D7 D6 D5 D4 D3 D2 D1 D0
EEC — — — — WREN WR RDEN RD
EEPROM Register List
• EEA Register
Bit 7 6 5 4 3 2 1 0
Name — — — EEA4 EEA3 EEA2 EEA1 EEA0
R/W — — — R/W R/W R/W R/W R/W
POR — — — 0 0 0 0 0

Bit 4~0 EEA4~EEA0: Data EEPROM address bit 4 ~ bit 0
Rev. 1.40 26 October 29, 2020

BC68F2123
• EED Register
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit 7~0 D7~D0: Data EEPROM data bit 7 ~ bit 0
• EEC Register
Bit 7 6 5 4 3 2 1 0
Name — — — — WREN WR RDEN RD
R/W — — — — R/W R/W R/W R/W
POR — — — — 0 0 0 0

Bit 3 WREN: Data EEPROM Write Enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data
EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM write operations.
Bit 2 WR: EEPROM Write Control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application
program will activate a write cycle. This bit will be automatically reset to zero by the
hardware after the write cycle has finished. Setting this bit high will have no effect if
the WREN has not first been set high.
Bit 1 RDEN: Data EEPROM Read Enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM read operations.
Bit 0 RD: EEPROM Read Control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application
program will activate a read cycle. This bit will be automatically reset to zero by the
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: 1. The WREN, WR, RDEN and RD cannot be set high at the same time in one instruction. The
WR and RD cannot be set high at the same time.
2. Ensure that the fLIRC clock is stable before executing the write operation.
3. Ensure that the write operation is totally complete before changing the contents of the
EEPROM related registers.
Rev. 1.40 27 October 29, 2020

BC68F2123
Reading Data from the EEPROM

To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set
high to enable the read function. The EEPROM address of the data to be read must then be placed
in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated.
Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When
the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can
be read from the EED register. The data will remain in the EED register until another read or write
operation is executed. The application program can poll the RD bit to determine when the data is
valid for reading.
Writing Data to the EEPROM

The EEPROM address of the data to be written must first be placed in the EEA register and the data
placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC
register must first be set high to enable the write function. After this, the WR bit in the EEC register
must be immediately set high to initiate a write cycle. These two instructions must be executed in
two consecutive instruction cycles. The global interrupt bit EMI should also first be cleared before
implementing any write operations, and then set again after the write cycle has started. Note that
setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the
EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to
microcontroller system clock, a certain time will elapse before the data will have been written into
the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the
WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates,
the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the
data has been written to the EEPROM. The application program can therefore poll the WR bit to
determine when the write cycle has ended.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered-on the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data
Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a
further measure of protection against spurious write operations. During normal program operation,
ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect
write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. When an
EEPROM write cycle ends, the DEF request flag will be set. If the global and EEPROM interrupt
are enabled and the stack is not full, a jump to the EEPROM Interrupt vector will take place. When
the EEPROM interrupt is serviced, the EEPROM interrupt flag will be automatically reset. More
details can be obtained in the Interrupt section.
Rev. 1.40 28 October 29, 2020

BC68F2123
Programming Considerations
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be
enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also
the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the
EEPROM control register exists. Although certainly not necessary, consideration might be given
in the application program to the checking of the validity of new write data by a simple read back
process.
When writing data the WR bit must be set high immediately after the WREN bit has been set high,
to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared
before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device
should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally
complete. Otherwise, the EEPROM read or write operation will fail.
Programming Examples
Reading data from the EEPROM – polling method

MOV A, EEPROM_ADRES ; user defined address
MOV EEA, A
MOV A, 040H ; setup memory pointer MP1
MOV MP1, A ; MP1 points to EEC register
MOV A, 01H ; setup Bank Pointer
MOV BP, A
SET IAR1.1 ; set RDEN bit, enable read operations
SET IAR1.0 ; start Read Cycle - set RD bit
BACK:
SZ IAR1.0 ; check for read cycle end
JMP BACK
CLR IAR1 ; disable EEPROM read if no more read operations are required
CLR BP
MOV A, EED ; move read data to register
MOV READ_DATA, A
Note: For each read operation, the address register should be re-specified followed by setting the RD
bit high to activate a read cycle even if the target address is consecutive.
Writing Data to the EEPROM – polling method

MOV A, EEPROM_ADRES ; user defined address
MOV EEA, A
MOV A, EEPROM_DATA ; user defined data
MOV EED, A
MOV A, 040H ; setup memory pointer MP1
MOV MP1, A ; MP1 points to EEC register
MOV A, 01H ; setup Bank Pointer
MOV BP, A
CLR EMI
SET IAR1.3 ; set WREN bit, enable write operations
SET IAR1.2 ; start Write Cycle - set WR bit– executed immediately after
; set WREN bit
SET EMI
BACK:
SZ IAR1.2 ; check for write cycle end
JMP BACK
CLR BP
Rev. 1.40 29 October 29, 2020

BC68F2123
Oscillators
Various oscillator options offer the user a wide range of functions according to their various
application requirements. The flexible features of the oscillator functions ensure that the best
optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation
are selected through registers.
Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer and Time Base Interrupts. Two fully integrated internal oscillators, requiring
no external components, are provided to form a wide range of both fast and slow system oscillators.
The higher frequency oscillator provides higher performance but carry with it the disadvantage of
higher power requirements, while the opposite is of course true for the lower frequency oscillator.
With the capability of dynamically switching between fast and slow system clock, these devices
have the flexibility to optimize the performance/power ratio, a feature especially important in power
sensitive portable applications.
Type Name Freq.
Internal High Speed RC HIRC 8MHz
Internal Low Speed RC LIRC 32kHz
Oscillator Types
System Clock Configurations

There are two methods of generating the system clock, a high speed oscillator and a low speed
oscillator. The high speed oscillator is the internal 8MHz RC oscillator. The low speed oscillator is
the internal 32kHz RC oscillator. Selecting whether the low or high speed oscillator is used as the
system oscillator is implemented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register
and as the system clock can be dynamically selected.
fH/2
High Speed Oscillator fH/4
fH/8
fH fSYS
HIRC Prescaler fH/16
fH/32
fH/64
Low Speed Oscillator HLCLK

CKS2~CKS0 bits
fL
LIRC
System Clock Configurations
Rev. 1.40 30 October 29, 2020

BC68F2123
Internal RC Oscillator – HIRC

The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has a fixed frequency of 8MHz. Device trimming during the
manufacturing process and the inclusion of internal frequency compensation circuits are used to
ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised.
Internal 32kHz Oscillator – LIRC

The internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated
RC oscillator with a typical frequency of 32kHz, requiring no external components for its
implementation. Device trimming during the manufacturing process and the inclusion of internal
frequency compensation circuits are used to ensure that the influence of the power supply voltage,
temperature and process variations on the oscillation frequency are minimised.
Supplementary Oscillator
The low speed oscillator, in addition to providing a system clock source is also used to provide
a clock source to two other device functions. These are the Watchdog Timer and the Time Base
Interrupts.
Operating Modes and System Clocks

Present day applications require that their microcontrollers have high performance but often still
demand that they consume as little power as possible, conflicting requirements that are especially
true in battery powered portable applications. The fast clocks required for high performance will
by their nature increase current consumption and of course vice-versa, lower speed clocks reduce
current consumption. As Holtek has provided the device with both high and low speed clock sources
and the means to switch between them dynamically, the user can optimise the operation of their
microcontroller to achieve the best performance/power ratio.
System Clocks
The device has two different clock sources for both the CPU and peripheral function operation. By
providing the user with clock options using register programming, a clock system can be configured
to obtain maximum application performance.
The main system clock, can come from either a high frequency, fH, or a low frequency, fL, and is
selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system
clock can be sourced from HIRC oscillator. The low speed system clock source can be sourced from
the internal clock fL. The other choice, which is a divided version of the high speed system oscillator
has a range of fH/2~fH/64.
There is one additional internal clock for the peripheral circuits, the Time Base clock, fTBC. fTBC is
sourced from the LIRC oscillators. The fTBC clock is used as a source for the Time Base interrupt
functions and for the TMs.
Rev. 1.40 31 October 29, 2020

BC68F2123
fH/2
High Speed Oscillator fH/4

fH/8
fH
HIRC Prescaler fSYS
fH/16
fH/32
fH/64
Low Speed Oscillator

HLCLK
fLIRC fL CKS2~CKS0 bits
LIRC
WDT
fTBC
IDLEN fTB
Time Base 0
fSYS/4
TBCK Time Base 1
Device Clock Configurations
Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillator will stop
to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use.
System Operation Modes

There are six different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance and
power requirements of the application. There are two modes allowing normal operation of the
microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0,
SLEEP1, IDLE0 and IDLE1 mode are used when the microcontroller CPU is switched off to
conserve power.
Operating Description
Mode CPU fSYS fLIRC fTBC
NORMAL mode On fH~fH/64 On On
SLOW mode On fL On On
IDLE0 mode Off Off On On
IDLE1 mode Off On On On
SLEEP0 mode Off Off Off Off
SLEEP1 mode Off Off On Off
NORMAL Mode
As the name suggests this is one of the main operating modes where the microcontroller has all
of its functions operational and where the system clock is provided the high speed oscillator. This
mode operates allowing the microcontroller to operate normally with a clock source will come from
the high speed oscillator HIRC. The high speed oscillator will however first be divided by a ratio
ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the
SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided
clock ratio reduces the operating current.
Rev. 1.40 32 October 29, 2020

BC68F2123
SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower
speed clock source. The clock source used will be from the low speed oscillator LIRC. Running
the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW
Mode, the fH is off.
SLEEP0 Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the
SMOD register is low. In the SLEEP0 mode the CPU will be stopped, the Watchdog Timer function
is disabled, and the fLIRC clock will be stopped.
SLEEP1 Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the
SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fLIRC clocks will
continue to operate as the Watchdog Timer function is enabled.
IDLE0 Mode
The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the SMOD1 register is low. In the IDLE0 Mode the
system oscillator will be inhibited from driving the CPU but some peripheral functions will remain
operational such as the Watchdog Timer and TMs. In the IDLE0 Mode, the system oscillator will be
stopped.
IDLE1 Mode
The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the SMOD1 register is high. In the IDLE1 Mode the
system oscillator will be inhibited from driving the CPU but may continue to provide a clock source
to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1
Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low
speed system oscillator. In the IDLE1 Mode, the Watchdog Timer clock, fLIRC, will be on.
Control Register
The SMOD register and the FSYSON bit in the SMOD1 register are used to control the internal
clocks within the device.
• SMOD Register
Bit 7 6 5 4 3 2 1 0
Name CKS2 CKS1 CKS0 – LTO HTO IDLEN HLCLK
R/W R/W R/W R/W – R R R/W R/W
POR 0 0 0 – 0 0 1 1
Bit 7~5 CKS2~CKS0: System clock selection when HLCLK is "0"

000: fL (LIRC)
001: fL (LIRC)
010: fH/64
011: fH/32
100: fH/16
101: fH/8
110: fH/4
111: fH/2
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source directly derived from fL or fH, a divided version of
the high speed system oscillator can also be chosen as the system clock source.
Rev. 1.40 33 October 29, 2020

BC68F2123
Bit 4 Unimplemented, read as "0"

Bit 3 LTO: Low speed oscillator ready flag
0: Not ready
1: Ready
This is the low speed system oscillator ready flag which indicates when the low speed
oscillator is stable after power on reset or a wake-up has occurred. The flag will be low
when in the SLEEP0 Mode, but after a wake-up has occurred the flag will change to a
high level after 1~2 cycles if the LIRC oscillator is used.
Bit 2 HTO: High speed oscillator ready flag
0: Not ready
1: Ready
This is the high speed oscillator ready flag which indicates when the high speed
system oscillator is stable. This flag is cleared to "0" by hardware when the device is
powered on and then changes to a high level after the high speed system oscillator is
stable. Therefore this flag will always be read as "1" by the application program after
device power-on.
Bit 1 IDLEN: IDLE Mode Control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
device will enter the IDLE Mode. If FSYSON bit is high, the CPU will stop running
but the system clock will continue to keep the peripheral functions operational in the
IDLE1 Mode. If FSYSON bit is low, the CPU and the system clock will all stop in
IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT
instruction is executed.
Bit 0 HLCLK: System Clock Selection
0: fH/2~fH/64 or fL
1: fH
This bit is used to select if the fH clock or the fH/2~fH/64 or fL clock is used as the
system clock. When the bit is high the fH clock will be selected and if low the
fH/2~fH/64 or fL clock will be selected. When system clock switches from the fH clock
to the fL clock and the fH clock will be automatically switched off to conserve power.
• SMOD1 Register
Bit 7 6 5 4 3 2 1 0
Name FSYSON — — — RSTF LVRF — WRF
R/W R/W — — — R/W R/W — R/W
POR 0 — — — 0 x — 0
"x": unknown
Bit 7 FSYSON: fSYS on/off control in IDLE Mode
0: Disable
1: Enable
Bit 3 RSTF: RSTC register software reset flag
Described elsewhere
Bit 2 LVRF: LVR function reset flag
Described elsewhere
Bit 0 WRF: WDT Control register software reset flag
Described elsewhere
Rev. 1.40 34 October 29, 2020

BC68F2123
Operating Mode Switching

The device can switch between operating modes dynamically allowing the user to select the best
performance/power ratio for the present task in hand. In this way microcontroller operations that
do not require high performance can be executed using slower clocks thus requiring less operating
current and prolonging battery life in portable applications.
In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed
using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the
NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When
a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is
determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the SMOD1
register.
When the HLCLK bit switches to a low level, which implies that clock source is switched from the
high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high
speed clock source will stop running to conserve power. When this happens it must be noted that the
fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other
internal functions such as the TMs.
SLOW
NORMAL
fSYS=fL
fSYS=fH~fH/64
fL on
fH on
CPU run
CPU run
fSYS on
fSYS on
fLIRC on
fLIRC on
fH on
SLEEP0 IDLE0
HALT instruction executed HALT instruction executed
fSYS off CPU stop
CPU stop IDLEN=1
IDLEN=0 FSYSON=0
fLIRC off fSYS off
WDT off fLIRC on
SLEEP1 IDLE1
HALT instruction executed HALT instruction executed
fSYS off CPU stop
CPU stop IDLEN=1
IDLEN=0 FSYSON=1
fLIRC on fSYS on
WDT on fLIRC on
NORMAL Mode to SLOW Mode Switching

When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore
consumes more power, the system clock can switch to run in the SLOW Mode by setting the HLCLK
bit to "0" and setting the CKS2~CKS0 bits to "000" or "001" in the SMOD register. This will then use
the low speed system oscillator which will consume less power. Users may decide to do this for certain
operations which do not require high performance and can subsequently reduce power consumption.
The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be
stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register.
Rev. 1.40 35 October 29, 2020

BC68F2123
NORMAL Mode
CKS2~CKS0 = 00xB &

HLCLK = 0
SLOW Mode
WDT is off
IDLEN=0
HALT instruction is executed
SLEEP0 Mode
WDT is on
IDLEN=0
SLEEP1 Mode
IDLEN=1, FSYSON=0
IDLE0 Mode
IDLEN=1, FSYSON=1
IDLE1 Mode
SLOW Mode to NORMAL Mode Switching

In SLOW Mode the system uses LIRC low speed system oscillator. To switch back to the NORMAL
Mode, where the high speed system oscillator is used, the HLCLK bit should be set to "1" or
HLCLK bit is "0", but CKS2~CKS0 is set to "010", "011", "100", "101", "110" or "111". As a certain
amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is
checked.
SLOW Mode
CKS2~CKS0 ≠ 000B or 001B

as HLCLK = 0 or HLCLK = 1
NORMAL Mode
WDT is off
IDLEN=0
SLEEP0 Mode
WDT is on
IDLEN=0
SLEEP1 Mode
IDLEN=1, FSYSON=0
IDLE0 Mode
IDLEN=1, FSYSON=1
IDLE1 Mode
Rev. 1.40 36 October 29, 2020

BC68F2123
Entering the SLEEP0 Mode

There is only one way for the device to enter the SLEEP0 Mode and that is to execute the "HALT"
instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the
WDT off. When this instruction is executed under the conditions described above, the following will
occur:
• The system clock, WDT clock and Time Base clock will be stopped and the application program
will stop at the "HALT" instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and stopped.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the SLEEP1 Mode

There is only one way for the devices to enter the SLEEP1 Mode and that is to execute the "HALT"
WDT on. When this instruction is executed under the conditions described above, the following will
occur:
• The system clock and Time Base clock will be stopped and the application program will stop at
the "HALT" instruction, but the WDT will remain with the clock source coming from the fLIRC
clock.
• The WDT will be cleared and resume counting if the WDT is enabled.
will be cleared.
Entering the IDLE0 Mode

There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT"
FSYSON bit in SMOD1 register equal to "0". When this instruction is executed under the conditions
described above, the following will occur:
• The system clock will be stopped and the application program will stop at the "HALT"
instruction, but the Time Base clock will be on.
will be cleared.
Rev. 1.40 37 October 29, 2020

BC68F2123
Entering the IDLE1 Mode

There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT"
FSYSON bit in SMOD1 register equal to "1". When this instruction is executed under the conditions
described above, the following will occur:
• The system clock and Time Base clock will be on and the application program will stop at the
"HALT" instruction.
will be cleared.
Standby Current Considerations

As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the
device to as low a value as possible, perhaps only in the order of several micro-amps except in the
IDLE1 Mode, there are other considerations which must also be taken into account by the circuit
designer if the power consumption is to be minimised. Special attention must be made to the I/O pins
on the device. All high-impedance input pins must be connected to either a fixed high or low level as
any floating input pins could create internal oscillations and result in increased current consumption.
This also applies to devices which have different package types, as there may be unbonded pins.
These must either be setup as outputs or if setup as inputs must have pull-high resistors connected.
Care must also be taken with the loads, which are connected to I/O pins, which are setup as
outputs. These should be placed in a condition in which minimum current is drawn or connected
only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode
the system oscillator is on, if the system oscillator is from the high speed system oscillator, the
additional standby current will also be perhaps in the order of several hundred micro-amps.
Wake-up
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources
listed as follows:
• An external reset
• An external falling edge on Port A
• A system interrupt
• A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset,
however, If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated.
Although both of these wake-up methods will initiate a reset operation, the actual source of the
wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog Timer instructions and is set when executing the
"HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and Stack Pointer, the other flags remain in their original status.
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at
the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then
two possible situations may occur. The first is where the related interrupt is disabled or the interrupt
Rev. 1.40 38 October 29, 2020

BC68F2123
is enabled but the stack is full, in which case the program will resume execution at the instruction
following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not
be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled
or when a stack level becomes free. The other situation is where the related interrupt is enabled and
the stack is not full, in which case the regular interrupt response takes place. If an interrupt request
flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related
interrupt will be disabled.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source

The Watchdog Timer clock source is provided by the internal fLIRC clock which is supplied by the
LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 215 to give
longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The
LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 3V. However, it
should be noted that this specified internal clock period can vary with VDD, temperature and process
variations. The WDT can be enabled/disabled using the WDTC register.
Watchdog Timer Control Register

A single register, WDTC, controls the required timeout period as well as the enable/disable
operation. The WRF software reset flag will be indicated in the SMOD1 register. These registers
control the overall operation of the Watchdog Timer.
• WDTC Register
Bit 7 6 5 4 3 2 1 0
Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0
POR 0 1 0 1 0 0 1 1
Bit 7~ 3 WE4~WE0: WDT function software control

10101: WDT disable
01010: WDT enable
Other values: Reset MCU
When these bits are changed to any other values by the environmental noise to reset
the microcontroller, the reset operation will be activated after 2~3 LIRC clock cycles
and the WRF bit will be set to 1 to indicate the reset source.
Bit 2~ 0 WS2~WS0: WDT Time-out period selection
000: 28/ fLIRC
001: 29/fLIRC
010: 210/fLIRC
011: 211/fLIRC
100: 212/fLIRC
101: 213/fLIRC
110: 214/fLIRC
111: 215/fLIRC
These three bits determine the division ratio of the Watchdog Timer source clock,
which in turn determines the timeout period.
Rev. 1.40 39 October 29, 2020

BC68F2123
• SMOD1 Register
Bit 7 6 5 4 3 2 1 0
R/W R/W — — — R/W R/W — R/W
POR 0 — — — 0 x — 0
"x": unknown
Described elsewhere
Described elsewhere
Described elsewhere
0: Not occur
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
Watchdog Timer Operation

The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, the clear WDT instructions will not be executed
in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With
regard to the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC
register to additional enable/disable and reset control of the Watchdog Timer.
WE4~WE0 Bits WDT Function
10101B Disable
01010B Enable
Any other value Reset MCU
Watchdog Timer Enable/Disable Control
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Four methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDTC software reset, which means a value other than 01010B and 10101B is written
into the WE4~WE0 bit locations, the second is an external hardware reset, which means a low level
on the external reset pin, the third is using the Watchdog Timer software clear instruction and the
fourth is via a HALT instruction. There is only one method of using software instruction to clear the
Watchdog Timer. That is to use the single "CLR WDT" instruction to clear the WDT.
The maximum time-out period is when the 215 division ratio is selected. As an example, with a 32
kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 1
second for the 215 division ratio, and a minimum timeout of 8ms for the 28 division ration.
Rev. 1.40 40 October 29, 2020

BC68F2123
WDTC Register WE4~WE0 bits Reset MCU
RES pin reset CLR

“CLR WDT”Instruction
“HALT”Instruction
fLIRC
LIRC 11-stage Divider
8-to-1 MUX 7-stage Divider WDT Time-out

(28/fLIRC ~ 215/fLIRC)
WS2~WS0
Watchdog Timer
Reset and Initialisation

A reset function is a fundamental part of any microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside parameters. The most important reset condition
is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the
microcontroller, after a short delay, will be in a well defined state and ready to execute the first program
instruction. After this power-on reset, certain important internal registers will be set to defined states
before the program commences. One of these registers is the Program Counter, which will be reset to
zero forcing the microcontroller to begin program execution from the lowest Program Memory address.
In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset
condition when the microcontroller is running. One example of this is where after power has been
applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case,
known as a normal operation reset, some of the microcontroller registers remain unchanged allowing
the microcontroller to proceed with normal operation after the reset line is allowed to return high.
Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All
types of reset operations result in different register conditions being setup. Another reset exists in the
form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power
supply voltage falls below a certain threshold.
Reset Functions
There are several ways in which a microcontroller reset can occur, through events occurring both
internally and externally:
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that
all pins will be first set to inputs.
VDD 0.9VDD
RES
tRSTD+tSST
Internal Reset
Note: tRSTD is power-on delay, typical time=50ms

Power-On Reset Timing Chart
Rev. 1.40 41 October 29, 2020

BC68F2123
RES Pin Reset

Although the microcontroller has an internal RC reset function, if the VDD power supply rise time
is not fast enough or does not stabilise quickly at power-on, the internal reset function may be
incapable of providing proper reset operation. For this reason it is recommended that an external
RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin
remains low for an extended period to allow the power supply to stabilise. During this time delay,
normal operation of the microcontroller will be inhibited. After the RES line reaches a certain
voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the
microcontroller will begin normal operation. The abbreviation SST in the figures stands for System
Start-up Timer.
For most applications a resistor connected between VDD and the RES pin and a capacitor connected
between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected
to the RES pin should be kept as short as possible to minimize any stray noise interference. For
applications that operate within an environment where more noise is present the Enhanced Reset
Circuit shown is recommended.
VDD
VDD
1N4148* 10kΩ~
100kΩ
0.01µF**
RES
300Ω*
0.1µF~1µF
VSS
Note: "*" It is recommended that this component is added for added ESD protection
"**" It is recommended that this component is added in environments where power line noise
is significant
External RES Circuit
Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in
the case of other resets, the Program Counter will reset to zero and program execution initiated from
this point.
0.9VDD
RES 0.4VDD
tRSTD+tSST
Internal Reset
Note: tRSTD is power-on delay, typical time=16.7ms

RES Reset Timing Chart
Rev. 1.40 42 October 29, 2020

BC68F2123
• RSTC External Reset Register

Bit 7 6 5 4 3 2 1 0
Name RSTC7 RSTC6 RSTC5 RSTC4 RSTC3 RSTC2 RSTC1 RSTC0
R/W R/W R/W R/W R/W R R R/W R/W
POR 0 1 0 1 0 1 0 1
————
Bit 7~0 RSTC7~RSTC0: PA7/RES selection

01010101: Configured as PA7 pin or other pin-shared function
10101010: Configured as RES pin
Other Values: MCU reset (reset will be active after 2~3 LIRC clock for debounce time)
All reset will reset this register as POR value except WDT time out Hardware warm
reset.
Note the RSTC register setting has the higher priority for selection of the RES pin
function than the PA7 pin-shared function selection register.
Low Voltage Reset – LVR

The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of
the device and provide an MCU reset should the value fall below a certain predefined level. The
LVR function is always enabled during the normal and slow modes with a specific LVR voltage
VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur
when changing the battery, the LVR will automatically reset the device internally and the LVRF bit
in the SMOD1 register will also be set to1. For a valid LVR signal, a low voltage, i.e., a voltage in
the range between 0.9V~ VLVR must exist for greater than the value tLVR specified in the LVD/LVR
Electrical Characteristics. If the low voltage state does not exceed this value, the LVR will ignore the
low supply voltage and will not perform a reset function. The actual VLVR is 2.1V, the LVR will reset
the device after 2~3 LIRC clock cycles. Note that the LVR function will be automatically disabled
when the device enters the SLEEP/IDLE mode.
LVR
tRSTD + tSST
Internal Reset
Note:tRSTD is power-on delay, typical time=50ms

Low Voltage Reset Timing Chart
• SMOD1 Register
Bit 7 6 5 4 3 2 1 0
R/W R/W — — — R/W R/W — R/W
POR 0 — — — 0 x — 0
"x": unknown
Described elsewhere
0: Not active
1: Active
This bit is set to 1 by the RSTC register setting and cleared to 0 by the application program.
Note that this bit can only be cleared to 0 by the application program or POR reset.
Rev. 1.40 43 October 29, 2020

BC68F2123

0: Not active
1: Active
This bit can be cleared to "0", but can not be set to "1"
Described elsewhere.
Watchdog Time-out Reset during Normal Operation

The Watchdog time-out flag TO will be set to "1" when Watchdog time-out Reset during normal
operations.
WDT Time-out
tRSTD
Internal Reset
Note: tRSTD is power-on delay, typical time=16.7ms

WDT Time-out Reset during Normal Operation Timing Chart
Watchdog Time-out Reset during SLEEP or IDLE Mode

The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for
tSST details.
WDT Time-out
tSST
Internal Reset
WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart
Reset Initial Conditions

The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO PDF RESET Conditions
0 0 Power-on reset
u u LVR reset
1 u WDT time-out reset during NORMAL or SLOW Mode operation
1 1 WDT time-out reset during IDLE or SLEEP Mode operation
Note: "u" stands for unchanged
Rev. 1.40 44 October 29, 2020

BC68F2123
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item Condition After RESET
Program Counter Reset to zero
Interrupts All interrupts will be disabled
WDT Clear after reset, WDT begins counting
Timer Modules Timer Modules will be turned off
Input/Output Ports I/O ports will be setup as inputs
Stack Pointer Stack Pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers. Note that where
more than one package type exists the table will reflect the situation for the larger package type.
WDT Time-out RES Reset
Reset RES Reset WDT Time-out
Register (Normal (Normal
(Power-on) (HALT) (HALT)*
Operation) Operation)
Program
000H 000H 000H 000H 000H
Counter
MP0 1xxx xxxx 1xxx xxxx 1xxx xxxx 1xxx xxxx 1uuu uuuu
MP1 1xxx xxxx 1xxx xxxx 1xxx xxxx 1xxx xxxx 1uuu uuuu
BP ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
PCL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu
STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu - - 11 u u u u
SMOD 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 uuu- uuuu
LVDC --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu
INTEG ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu
INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu
INTC1 0-00 0-00 0-00 0-00 0-00 0-00 0-00 0-00 u-uu u-uu
MFI0 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu
MFI1 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu
PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PAWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
IFS0 0000 0-00 0000 0-00 0000 0-00 0000 0-00 uuuu u-uu
WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuuu
TBC 0 0 11 - 111 0 0 11 - 111 0 0 11 - 111 0 0 11 - 111 uuuu –uuu
SMOD1 0--- 0x-0 0--- 0x-0 0--- 0x-0 0--- 0x-0 u--- uu-u
EEA ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu
EED 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
RSTC 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu
PASR 000- ---- 000- ---- 000- ---- 000- ---- uuu- ----
PBSR --00 000- --00 000- --00 000- --00 000- --uu uuu-
STM0C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
STM0C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
Rev. 1.40 45 October 29, 2020

BC68F2123
WDT Time-out RES Reset

Reset RES Reset WDT Time-out
Register (Normal (Normal
(Power-on) (HALT) (HALT)*
Operation) Operation)
STM0DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
STM0DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu
STM0AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
STM0AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu
PB - - 11 1111 - - 11 1111 - - 11 1111 - - 11 1111 --uu uuuu
PBC - - 11 1111 - - 11 1111 - - 11 1111 - - 11 1111 --uu uuuu
PBPU --00 0000 --00 0000 --00 0000 --00 0000 --uu uuuu
PTM1C0 0000 0--- 0000 0--- 0000 0--- 0000 0--- uuuu u---
PTM1C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PTM1DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PTM1DH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu
PTM1AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PTM1AH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu
PTM1RPL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu
PTM1RPH ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu
EEC ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu
Note: "*" stands for warm reset
"-" stands for "unimplemented"
"u" stands for "unchanged"
"x" stands for "unknown"
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
The devices provide bidirectional input/output lines labeled with port names PA~PB. These I/O
ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used for input and output operations. For input
operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge
of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is
latched and remains unchanged until the output latch is rewritten.
Register Bit
Name 7 6 5 4 3 2 1 0
PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0
PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0
PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0
PB — — PB5 PB4 PB3 PB2 PB1 PB0
PBC — — PBC5 PBC4 PBC3 PBC2 PBC1 PBC0
PBPU — — PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0
"—": Unimplemented, read as "0"
I/O Logic Function Register List
Rev. 1.40 46 October 29, 2020

BC68F2123
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as a digital input have the capability of being connected to an internal pull-high resistor.
These pull-high resistors are selected using register PAPU~PBPU, and are implemented using weak
PMOS transistors.
Note that the pull-high resistor can be controlled by the relevant pull-high control register only when
the pin-shared functional pin is selected as a digital input or NMOS output. Otherwise, the pull-high
resistors cannot be enabled.
• PxPU Register
Bit 7 6 5 4 3 2 1 0
Name PxPU7 PxPU6 PxPU5 PxPU4 PxPU3 PxPU2 PxPU1 PxPU0
POR 0 0 0 0 0 0 0 0
Bit 7~0 I/O Port x Pin: pull-high function control

0: Disable
1: Enable
The PxPUn bit is used to control the pin pull-high function. Here the "x" can be A and B.
However, the actual available bits for each I/O Port may be different.
Special attention should be paid to the unbonded lines, PA3, PA4 and PB4, which must
either be set as outputs or if sets as inputs must have pull-high resistors connected to
avoid unwanted power consumption result from floating input conditions.
For the PB2 and PB3 lines, which are internally connected to the RF transmitter module,
the corresponding PBPU2 and PBPU3 bits should be kept as "0" after power on.
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port
A pins from high to low. This function is especially suitable for applications that can be woken up
via external switches. Each pin on Port A can be selected individually to have this wake-up feature
using the PAWU register.
Note that the wake-up function can be controlled by the wake-up control registers only when the pin
is selected as a general purpose input and the MCU enters the IDLE or SLEEP mode.
• PAWU Register
Bit 7 6 5 4 3 2 1 0
Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0
POR 0 0 0 0 0 0 0 0
Bit 7~0 PAWU7~PAWU0: PA7~PA0 pin wake-up function control

0: Disable
1: Enable
Rev. 1.40 47 October 29, 2020

BC68F2123
I/O Port Input/Output Control

Each I/O port has its own control register known as PAC~PBC, to control the input/output
configuration. With these control registers, each CMOS output or input can be reconfigured
dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its
associated port control register. For the I/O pin to function as an input, the corresponding bit of the
control register must be written as a "1". This will then allow the logic state of the input pin to be
directly read by instructions. When the corresponding bit of the control register is written as a "0",
the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions
can still be used to read the output register. However, it should be noted that the program will in fact
only read the status of the output data latch and not the actual logic status of the output pin.
• PxC Register
Bit 7 6 5 4 3 2 1 0
Name PxC7 PxC6 PxC5 PxC4 PxC3 PxC2 PxC1 PxC0
POR 1 1 1 1 1 1 1 1
PxCn: I/O Port x Pin type selection

0: Output
1: Input
The PxCn bit is used to control the pin type selection. Here the "x" can be A and B. However,
the actual available bits for each I/O Port may be different.
Special attention should be paid to the unbonded lines, PA3, PA4 and PB4, which must
either be set as outputs or if sets as inputs must have pull-high resistors connected to avoid
unwanted power consumption result from floating input conditions.
For the PB2 and PB3 lines, which are internally connected to the RF transmitter module, the
corresponding PBC2 and PBC3 bits should be cleared to zero to select the PB2 and PB3 as
outputs.
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but by
supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the
desired function of the multi-function I/O pins is selected by a series of registers via the application
program control.
Pin-shared Function Selection Registers

The limited number of supplied pins in a package can impose restrictions on the amount of functions
a certain device can contain. However by allowing the same pins to share several different functions
and providing a means of function selection, a wide range of different functions can be incorporated
into even relatively small package sizes. The device includes Port "x" pin shared function selection
register, labeled as PxSR, and input function selection register, labeled as IFS0, which can select the
desired functions of the multi-function pin-shared pins.
The most important point to note is to make sure that the desired pin-shared function is properly
selected and also deselected. For most pin-shared functions, to select the desired pin-shared function,
the pin-shared function should first be correctly selected using the corresponding pin-shared control
register. After that the corresponding peripheral functional setting should be configured and then
the peripheral function can be enabled. However, a special point must be noted for some digital
input pins, such as INT, PTCK1, etc, which share the same pin-shared control configuration with
their corresponding general purpose I/O functions when setting the relevant pin-shared control bit
Rev. 1.40 48 October 29, 2020

BC68F2123
fields. To select these pin functions, in addition to the necessary pin-shared control and peripheral
functional setup aforementioned, they must also be setup as an input by setting the corresponding bit
in the I/O port control register. To correctly deselect the pin-shared function, the peripheral function
should first be disabled and then the corresponding pin-shared function control register can be
modified to select other pin-shared functions.
Register Bit
Name 7 6 5 4 3 2 1 0
PASR PAS7 PAS6 PAS5 — — — — —
PBSR — — PBS5 PBS4 PBS3 PBS2 PBS1 —
IFS0 PTCK1PS1 PTCK1PS0 STCK0PS STP0IPS PTP1IPS — INTPS1 INTPS0
Pin-shared Function Selection Register List
• IFS0 Register
Bit 7 6 5 4 3 2 1 0
Name PTCK1PS1 PTCK1PS0 STCK0PS STP0IPS PTP1IPS — INTPS1 INTPS0
R/W R/W R/W R/W R/W R/W — R/W R/W
POR 0 0 0 0 0 — 0 0
Bit 7~6 PTCK1PS1~PTCK1PS0: PTCK1 input source pin selection

00: Reserve
01: PTCK1 on PA6
10: PTCK1 on PA7
11: PTCK1 on PB1
Bit 5 STCK0PS: STCK0 input source pin selection
0: Reserve
1: STCK0 on PA2
Bit 4 STP0IPS: STP0I input source pin selection
0: STP0I on PA6
1: STP0I on PA0
Bit 3 PTP1IPS: PTP1I input source pin selection
0: PTP1I on PA5
1: PTP1I on PB0
Bit 1~0 INTPS1~INTPS0: INT input source pin selection
00: Reserve
01: INT on PA2
10: Reserve
11: INT on PA5
• PASR Register
Bit 7 6 5 4 3 2 1 0
Name PAS7 PAS6 PAS5 — — — — —
R/W R/W R/W R/W — — — — —
POR 0 0 0 — — — — —
Bit 7 PAS7: PA7 Pin-Shared Function Selection

0: PA7/PTCK1
1: STP0B
Note: PAS7 is valid when RSTC=55H
0: PA6/PTCK1/STP0I
1: STP0
Rev. 1.40 49 October 29, 2020

BC68F2123

This bit should be kept as "0".
• PBSR Register
Bit 7 6 5 4 3 2 1 0
Name — — PBS5 PBS4 PBS3 PBS2 PBS1 —
R/W — — R/W R/W R/W R/W R/W —
POR — — 0 0 0 0 0 —

Bit 5 PBS5: PB5 Pin-Shared Function Selection
0: PB5
1: PTP1
0: PB1/PTCK1
1: STP0B
I/O Pin Structures

The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As
the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a
guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared
structures does not permit all types to be shown.
VDD
Pull-high
Control Bit Register Weak
Select Pull-up
Data Bus D Q
Write Control Register CK Q

S
Chip Reset
I/O pin
Read Control Register
Data Bit
D Q
Write Data Register CK Q
S
M
U
X
Read Data Register
System Wake-up wake-up Select PA only
Generic Input/Output Structure
Rev. 1.40 50 October 29, 2020

BC68F2123
Within the user program, one of the first things to consider is port initialisation. After a reset, all
of the I/O data and port control registers will be set high. This means that all I/O pins will default
to an input state, the level of which depends on the other connected circuitry and whether pull-
high selections have been chosen. If the port control registers are then programmed to setup some
pins as outputs, these output pins will have an initial high output value unless the associated port
data registers are first programmed. Selecting which pins are inputs and which are outputs can be
achieved byte-wide by loading the correct values into the appropriate port control register or by
programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i"
instructions. Note that when using these bit control instructions, a read-modify-write operation takes
place. The microcontroller must first read in the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output ports.
Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP
or IDLE Mode, various methods are available to wake the device up. One of these is a high to low
transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.
Timer Modules – TM
One of the most fundamental functions in any microcontroller device is the ability to control and
measure time. To implement time related functions the device includes several Timer Modules,
abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide
operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output
as well as being the functional unit for the generation of PWM signals. Each of the TMs has two
individual interrupts. The addition of input and output pins for each TM ensures that users are
provided with timing units with a wide and flexible range of features.
The common features of the different TM types are described here with more detailed information
provided in the individual Standard and Periodic TM sections.
Introduction
The device contains two TMs with each TM having a reference name of TM0~TM1. Each individual
TM can be categorised as a certain type, namely Standard Type TM or Periodic Type TM. Although
similar in nature, the different TM types vary in their feature complexity. The common features to
the Standard and Periodic TMs will be described in this section and the detailed operation will be
described in corresponding sections. The main features and differences between the two types of
TMs are summarised in the accompanying table.
Function STM PTM
Timer/Counter √ √
Input Capture √ √
Compare Match Output √ √
PWM Output √ √
Single Pulse Output √ √
PWM Alignment Edge Edge
PWM Adjustment Period & Duty Duty or Period Duty or Period
TM Function Summary
Rev. 1.40 51 October 29, 2020

BC68F2123
TM Operation
The two different types of TMs offer a diverse range of functions, from simple timing operations
to PWM signal generation. The key to understanding how the TM operates is to see it in terms of
a free running counter whose value is then compared with the value of pre-programmed internal
comparators. When the free running counter has the same value as the pre-programmed comparator,
known as a compare match situation, a TM interrupt signal will be generated which can clear the
counter and perhaps also change the condition of the TM output pin. The internal TM counter is
driven by a user selectable clock source, which can be an internal clock or an external pin.
TM Clock Sources
The clock source which drives the main counter in each TM can originate from various sources. The
selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTM
control registers. The clock source can be a ratio of either the system clock fSYS or the internal high
clock fH, the fTBC clock source or the external xTCKn pin. The xTCKn pin clock source is used to
allow an external signal to drive the TM as an external clock source or for event counting.
TM Interrupts
The Standard and Periodic type TMs each has two internal interrupts, the internal comparator A
or comparator P, which generate a TM interrupt when a compare match condition occurs. When a
TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM
output pin.
TM External Pins
Each of the TMs, irrespective of what type, has two TM input pins, with the label xTCKn and
xTPnI. The TM input pin xTCKn, is essentially a clock source for the TM and is selected using the
xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows an external clock
source to drive the internal TM. This external TM input pin is shared with other functions but will
be connected to the internal TM if selected using the xTnCK2~xTnCK0 bits. The TM input pin can
be chosen to have either a rising or falling active edge.
The other TM input pin, xTPnI, is the capture input whose active edge can be a rising edge, a falling
edge or both rising and falling edges and the active edge transition type is selected using the xTnIO1
and xTnIO0 bits in the xTMnC1 register.
The TMs each have one or two output pins with the label xTPn and xTPnB. When the TM is in the
Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low
level or to toggle when a compare match situation occurs. The external xTPn output pin is also the
pin where the TM generates the PWM output waveform.
As the TM input and output pins are pin-shared with other functions, the TM input or output
function must first be setup using relevant pin-shared function selection register. The details of the
pin-shared function selection are described in the pin-shared function section.
TM
STM0 PTM1
Pins
Input pins STCK0, STP0I PTCK1, PTP1I
Output pins STP0, STP0B PTP1
TM External Pins
Rev. 1.40 52 October 29, 2020

BC68F2123
Inverted Output
STP0B
Output
STP0
STM
Capture Input
STP0I
TCK Input
STCK0
STM Function Pin Block Diagram
Output
PTP1
Capture Input
PTM PTP1I
TCK Input
PTCK1
PTM Function Pin Block Diagram
The TM Counter Registers and the Capture/Compare CCRA register, and CCRP register pair for
Periodic Timer Module, all have a low and high byte structure. The high bytes can be directly
accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing
to these register pairs must be carried out in a specific way. The important point to note is that data
transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read
operation to its corresponding high byte is executed.
As the CCRA register and CCRP registers are implemented in the way shown in the following
diagram and accessing the register is carried out CCRP low byte register using the following
access procedures. Accessing the CCRA or CCRP low byte register without following these access
procedures will result in unpredictable values.
PTM Counter Register (Read only)
PTM1DL PTM1DH
STM Counter Register (Read only)
STM0DL STM0DH
8-bit Buffer
8-bit Buffer
PTM1AL PTM1AH
PTM CCRA Register (Read/Write)

STM0AL STM0AH
STM CCRA Register (Read/Write) PTM1RPL PTM1RPH
PTM CCRP Register (Read/Write)

Data Data
Bus Bus
Rev. 1.40 53 October 29, 2020

BC68F2123
The following steps show the read and write procedures:

• Writing Data to CCRA or PTM CCRP
♦ Step 1. Write data to Low Byte STM0AL, PTM1AL or PTM1RPL
– note that here data is only written to the 8-bit buffer.

♦ Step 2. Write data to High Byte STM0AH, PTM1AH or PTM1RPH
– here data is written directly to the high byte registers and simultaneously data is latched
from the 8-bit buffer to the Low Byte registers.
• Reading Data from the Counter Registers and CCRA or PTM CCRP
♦ Step 1. Read data from the High Byte STM0DH, STM0AH,PTM1DH, PTM1AH or PTM1RPH
– here data is read directly from the High Byte registers and simultaneously data is latched
from the Low Byte register into the 8-bit buffer.
♦ Step 2. Read data from the Low Byte STM0DL, STM0AL, PTM1DL, PTM1AL or PTM1RPL
– this step reads data from the 8-bit buffer.
Standard Type TM – STM

The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can
be controlled with two external input pins and can drive two external output pins.
TM Type TM Name TM Input Pin TM Output Pin
10-bit STM STM0 STCK0, STP0I STP0, STP0B
CCRP
Comparator P Match
3-bit Comparator P STMP0F Interrupt
fSYS/4 000
fSYS 001 ST1OC
b7~b9
fH/16 010
fH/64 011 Counter Clear 0 Output Polarity STP0
10-bit Count-up Counter
fTBC 100 1 Control Control STP0B
fTBC 101 ST0ON
110 ST0PAU ST0CCLR
b0~b9 ST0M1, ST0M0 ST0POL
STCK0 111 ST0IO1, ST0IO0
Comparator A Match
ST0CK2~ST0CK0 10-bit Comparator A STMA0F Interrupt
ST0IO1, ST0IO0
Edge
CCRA STP0I
Detector
Note: The STM0 external pins are pin-shared with other functions, so before using the STM0
functions, the pin-shared function registers must be set properly to enable the STM0 pin
function. The STCK0 and STP0I pins, if used, must also be set as an input by setting the
corresponding bits in the port control register.
Standard Type TM Block Diagram
Standard TM Operation
At its core is a 10-bit count-up counter which is driven by a user selectable internal clock source.
There are also two internal comparators with the names, Comparator A and Comparator P. These
comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is 3-bit
wide whose value is compared with the highest 3 bits in the counter while the CCRA is the 10 bits
and therefore compares with all counter bits.
Rev. 1.40 54 October 29, 2020

BC68F2123
The only way of changing the value of the 10-bit counter using the application program, is to
clear the counter by changing the ST0ON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Standard
Type TM can operate in a number of different operational modes, can be driven by different clock
sources and can also control an output pin. All operating setup conditions are selected using relevant
internal registers.
Standard Type TM Register Description

Overall operation of the Standard TM is controlled using series of registers. A read only register
pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store
the internal 10-bit CCRA value. The remaining two registers are control registers which setup the
different operating and control modes as well as three CCRP bits.
Register Bit
Name 7 6 5 4 3 2 1 0
STM0C0 ST0PAU ST0CK2 ST0CK1 ST0CK0 ST0ON ST0RP2 ST0RP1 ST0RP0
STM0C1 ST0M1 ST0M0 ST0IO1 ST0IO0 ST0OC ST0POL ST0DPX ST0CCLR
STM0DL D7 D6 D5 D4 D3 D2 D1 D0
STM0DH — — — — — — D9 D8
STM0AL D7 D6 D5 D4 D3 D2 D1 D0
STM0AH — — — — — — D9 D8
10-bit Standard TM Register List
• STM0C0 Register
Bit 7 6 5 4 3 2 1 0
Name ST0PAU ST0CK2 ST0CK1 ST0CK0 ST0ON ST0RP2 ST0RP1 ST0RP0
POR 0 0 0 0 0 0 0 0
Bit 7 ST0PAU: STM0 Counter Pause Control

0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the STM will remain powered
up and continue to consume power. The counter will retain its residual value when
this bit changes from low to high and resume counting from this value when the bit
changes to a low value again.
Bit 6~4 ST0CK2~ST0CK0: Select STM0 Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: fTBC
110: STCK0 rising edge clock
111: STCK0 falling edge clock
These three bits are used to select the clock source for the STM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fH and fTBC are other internal clocks, the details of which can
be found in the oscillator section.
Rev. 1.40 55 October 29, 2020

BC68F2123
Bit 3 ST0ON: STM0 Counter On/Off Control

0: Off
1: On
This bit controls the overall on/off function of the STM. Setting the bit high enables
the counter to run, clearing the bit disables the STM. Clearing this bit to zero will
stop the counter from counting and turn off the STM which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value until the bit returns high again. If the STM is in
the Compare Match Output Mode or the PWM output Mode or Single Pulse Output
Mode then the STM output pin will be reset to its initial condition, as specified by the
ST0OC bit, when the ST0ON bit changes from low to high.
Bit 2~0 ST0RP2~ ST0RP0: STM0 CCRP 3-bit register, compared with the STM0 Counter
bit 9 ~ bit 7
Comparator P Match Period
000: 1024 STM0 clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which are
then compared with the internal counter's highest three bits. The result of this comparison
can be selected to clear the internal counter if the ST0CCLR bit is set to zero. Setting the
ST0CCLR bit to zero ensures that a compare match with the CCRP values will reset the
internal counter. As the CCRP bits are only compared with the highest three counter bits,
the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in
effect allowing the counter to overflow at its maximum value.
• STM0C1 Register
Bit 7 6 5 4 3 2 1 0
Name ST0M1 ST0M0 ST0IO1 ST0IO0 ST0OC ST0POL ST0DPX ST0CCLR
POR 0 0 0 0 0 0 0 0
Bit 7~6 ST0M1~ ST0M0: Select STM0 Operating Mode

00: Compare Match Output Mode
01: Capture Input Mode
10: PWM output Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the STM. To ensure reliable operation
the STM should be switched off before any changes are made to the ST0M1 and
ST0M0 bits. In the Timer/Counter Mode, the STM output pin state is undefined.
Bit 5~4 ST0IO1~ ST0IO0: Select STM0 External Pin Function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM output Mode/ Single Pulse Output Mode
00: PWM Output inactive state
01: PWM Output active state
10: PWM output
11: Single pulse output
Rev. 1.40 56 October 29, 2020

BC68F2123
Capture Input Mode

00: Input capture at rising edge of STP0I
01: Input capture at falling edge of STP0I
10: Input capture at falling/rising edge of STP0I
11: Input capture disabled
Timer/counter Mode:
Unused
These two bits are used to determine how the TM external pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the TM is running.
In the Compare Match Output Mode, the ST0IO1~ST0IO0 bits determine how the
STM0 output pin changes state when a compare match occurs from the Comparator A.
The TM output pin can be setup to switch high, switch low or to toggle its present state
when a compare match occurs from the Comparator A. When the ST0IO1~ST0IO0
bits are both zero, then no change will take place on the output. The initial value of
the TM output pin should be setup using the ST0OC bit. Note that the output level
requested by the ST0IO1~ST0IO0 bits must be different from the initial value setup
using the ST0OC bit otherwise no change will occur on the TM output pin when a
compare match occurs. After the TM output pin changes state, it can be reset to its
initial level by changing the level of the ST0ON bit from low to high.
In the PWM Output Mode, the ST0IO1 and ST0IO0 bits determine how the TM output
pin changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to change the values of
the ST0IO1 and ST0IO0 bits only after the TM has been switched off. Unpredictable
PWM outputs will occur if the ST0IO1 and ST0IO0 bits are changed when the TM is
running.
Bit 3 ST0OC: STM0 Output control bit
0: Initial low
1: Initial high
PWM Output Mode/ Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the STM output pin. Its operation depends upon
whether STM is being used in the Compare Match Output Mode or in the PWM
Output Mode/ Single Pulse Output Mode. It has no effect if the STM is in the Timer/
Counter Mode. In the Compare Match Output Mode it determines the logic level
of the STM output pin before a compare match occurs. In the PWM output Mode it
determines if the PWM signal is active high or active low. In the Single Pulse Output
Mode it determines the logic level of the STM output pin when the ST0ON bit
changes from low to high.
Bit 2 ST0POL: STM0 STP0 Output polarity Control
0: Non-inverted
1: Inverted
This bit controls the polarity of the STP0 output pin. When the bit is set high the STM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
Bit 1 ST0DPX: STM0 PWM period/duty Control
0: CCRP – period; CCRA – duty
1: CCRP – duty; CCRA – period
This bit, determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0 ST0CCLR: Select STM0 Counter clear condition
0: STM0 Comparator P match
1: STM0 Comparator A match
Rev. 1.40 57 October 29, 2020

BC68F2123
This bit is used to select the method which clears the counter. Remember that the
Standard TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the ST0CCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The ST0CCLR bit is not
used in the PWM output mode, Single Pulse or Input Capture Mode.
• STM0DL Register
Bit 7 6 5 4 3 2 1 0
R/W R R R R R R R R
POR 0 0 0 0 0 0 0 0
Bit 7~0 D7~D0: STM0 Counter Low Byte Register bit 7 ~ bit 0
STM0 10-bit Counter bit 7 ~ bit 0
• STM0DH Register
Bit 7 6 5 4 3 2 1 0
Name — — — — — — D9 D8
R/W — — — — — — R R
POR — — — — — — 0 0

Bit 1~0 D9~D8: STM0 Counter High Byte Register bit 1 ~ bit 0
STM0 10-bit Counter bit 9 ~ bit 8
• STM0AL Register
Bit 7 6 5 4 3 2 1 0
POR 0 0 0 0 0 0 0 0
Bit 7~0 D7~D0: STM0 CCRA Low Byte Register bit 7 ~ bit 0
STM0 10-bit CCRA bit 7 ~ bit 0
• STM0AH Register
Bit 7 6 5 4 3 2 1 0
Name — — — — — — D9 D8
R/W — — — — — — R/W R/W
POR — — — — — — 0 0

Bit 1~0 D9~D8: STM0 CCRA High Byte Register bit 1 ~ bit 0
STM0 10-bit CCRA bit 9 ~ bit 8
Rev. 1.40 58 October 29, 2020

BC68F2123
Standard Type TM Operating Modes

The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the ST0M1 and ST0M0 bits in the STM0C1 register.
Compare Output Mode

To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register, should be set to 00
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the ST0CCLR bit is low, there are two ways in which the counter can be
cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all
zero which allows the counter to overflow. Here both STMA0F and STMP0F interrupt request flags
for Comparator A and Comparator P respectively, will both be generated.
If the ST0CCLR bit in the STM0C1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the STMA0F interrupt request flag will
be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore
when ST0CCLR is high no STMP0F interrupt request flag will be generated. In the Compare
Match Output Mode, the CCRA can not be set to "0". If the CCRA bits are all zero, the counter will
overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the STMA0F interrupt
request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the STM output pin, will change
state. The STM output pin condition however only changes state when an STMA0F interrupt request
flag is generated after a compare match occurs from Comparator A. The STMP0F interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the STM
output pin. The way in which the STM output pin changes state are determined by the condition of
the ST0IO1 and ST0IO0 bits in the STM0C1 register. The STM output pin can be selected using
the ST0IO1 and ST0IO0 bits to go high, to go low or to toggle from its present condition when a
compare match occurs from Comparator A. The initial condition of the STM output pin, which is
setup after the ST0ON bit changes from low to high, is setup using the ST0OC bit. Note that if the
ST0IO1 and ST0IO0 bits are zero then no pin change will take place.
Rev. 1.40 59 October 29, 2020

BC68F2123
Counter Value Counter overflow ST0CCLR = 0; ST0M [1:0] = 00

CCRP > 0
CCRP=0
Counter cleared by CCRP value
0x3FF
CCRP > 0 Counter
Resume Restart
CCRP
Pause Stop
CCRA
Time
ST0ON
ST0PAU
ST0POL
CCRP Int.
flag STMP0F
CCRA Int.
flag STMA0F
STM O/P Pin
Output not affected by

Output pin set to STMA0F flag. Remains High
Output Toggle Output Inverts
initial Level Low until reset by ST0ON bit
with STMA0F flag when ST0POL is high
if ST0OC=0 Output Pin
Note ST0IO [1:0] = 10 Reset to Initial value
Here ST0IO [1:0] = 11 Active High Output select Output controlled by
Toggle Output select other pin-shared function
Compare Match Output Mode – ST0CCLR=0

Note: 1. With ST0CCLR=0 a Comparator P match will clear the counter
2. The TM output pin controlled only by the STMA0F flag
3. The output pin reset to initial state by a ST0ON bit rising edge
Rev. 1.40 60 October 29, 2020

BC68F2123
Counter Value ST0CCLR = 1; ST0M [1:0] = 00
CCRA > 0 Counter cleared by CCRA value CCRA = 0

Counter overflow
0x3FF
Resume CCRA=0
CCRA
Pause Stop Counter Restart
CCRP
Time
ST0ON
ST0PAU
ST0POL
No STMA0F flag
generated on
CCRA Int. CCRA overflow
flag STMA0F
CCRP Int.
flag STMP0F
STMP0F not Output

does not
generated change
STM O/P Pin
STMA0F flag. Remains High Output Inverts
Output Toggle
Output pin set to until reset by ST0ON bit when ST0POL is high
with STMA0F flag Output Pin
initial Level Low if
ST0OC=0 Note ST0IO [1:0] = 10 Reset to Initial value
Here ST0IO [1:0] = 11 Active High Output select Output controlled by
Compare Match Output Mode – ST0CCLR=1

Note: 1. With ST0CCLR=1 a Comparator A match will clear the counter
2. The TM output pin controlled only by the STMA0F flag
3. The output pin reset to initial state by a ST0ON rising edge
4. The STMP0F flag is not generated when ST0CCLR=1
Rev. 1.40 61 October 29, 2020

BC68F2123
Timer/Counter Mode
To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register should be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the
STM output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the STM output pin is not used in
this mode, the pin can be used as a normal I/O pin or other pin-shared function by setting pin-share
function register.
PWM Output Mode

To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register should be set to 10 respectively
and also the ST0IO1 and ST0IO0 bits should be set to 10 respectively. The PWM function within
the STM is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM output mode, the ST0CCLR bit has no effect as the
PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one
register is used to clear the internal counter and thus control the PWM waveform frequency, while
the other one is used to control the duty cycle. Which register is used to control either frequency
or duty cycle is determined using the ST0DPX bit in the STM0C1 register. The PWM waveform
frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The ST0OC bit in the STM0C1 register is used
to select the required polarity of the PWM waveform while the two ST0IO1 and ST0IO0 bits are
used to enable the PWM output or to force the STM output pin to a fixed high or low level. The
ST0POL bit is used to reverse the polarity of the PWM output waveform.
• 10-bit STM, PWM Output Mode, Edge-aligned Mode, ST0DPX=0

CCRP 001b 010b 011b 100b 101b 110b 111b 000b
Period 128 256 384 512 640 768 896 1024
Duty CCRA
If fSYS=8MHz, TM clock source is fSYS/4, CCRP=100b and CCRA=128,

The STM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 4kHz, duty = 128/512 = 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 10-bit STM, PWM Output Mode, Edge-aligned Mode, ST0DPX=1

CCRP 001b 010b 011b 100b 101b 110b 111b 000b
Period CCRA
Duty 128 256 384 512 640 768 896 1024
The PWM output period is determined by the CCRA register value together with the STM clock
while the PWM duty cycle is defined by the CCRP register value.
Rev. 1.40 62 October 29, 2020

BC68F2123
Counter Value ST0DPX = 0; ST0M [1:0] = 10

Counter cleared by
CCRP
Counter Reset when
ST0ON returns high
CCRP
Counter Stop if
Pause Resume
ST0ON bit low
CCRA
Time
ST0ON
ST0PAU
ST0POL
CCRA Int.
flag STMA0F
CCRP Int.
flag STMP0F
STM O/P Pin

(ST0OC=1)
STM O/P Pin
(ST0OC=0)
PWM Duty Cycle PWM resumes

set by CCRA operation
Output controlled by
other pin-shared function Output Inverts
when ST0POL = 1
PWM Period set by CCRP
PWM Output Mode – ST0DPX=0

Note: 1. Here ST0DPX=0 – Counter cleared by CCRP
2. A counter clear sets PWM Period
3. The internal PWM function continues running even when ST0IO[1:0]=00 or 01
4. The ST0CCLR bit has no influence on PWM operation
Rev. 1.40 63 October 29, 2020

BC68F2123
Counter Value ST0DPX = 1; ST0M [1:0] = 10

Counter cleared by
CCRA
Counter Reset when
ST0ON returns high
CCRA
Counter Stop if
Pause Resume
ST0ON bit low
CCRP
Time
ST0ON
ST0PAU
ST0POL
CCRP Int.
flag STMP0F
CCRA Int.
flag STMA0F
STM O/P Pin

(ST0OC=1)
STM O/P Pin
(ST0OC=0)

set by CCRP operation
Output controlled by
other pin-shared function Output Inverts
when ST0POL = 1
PWM Period set by CCRA
PWM Output Mode – ST0DPX=1

Note: 1. Here ST0DPX=1 – Counter cleared by CCRA
2. A counter clear sets PWM Period
3. The internal PWM function continues even when ST0IO[1:0]=00 or 01
4. The ST0CCLR bit has no influence on PWM operation
Rev. 1.40 64 October 29, 2020

BC68F2123
Single Pulse Mode

To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register should be set to 10
respectively and also the ST0IO1 and ST0IO0 bits should be set to 11 respectively. The Single Pulse
Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin.
The trigger for the pulse output leading edge is a low to high transition of the ST0ON bit, which
can be implemented using the application program. However in the Single Pulse Mode, the ST0ON
bit can also be made to automatically change from low to high using the external STCK0 pin,
which will in turn initiate the Single Pulse output. When the ST0ON bit transitions to a high level,
the counter will start running and the pulse leading edge will be generated. The ST0ON bit should
remain high when the pulse is in its active state. The generated pulse trailing edge will be generated
when the ST0ON bit is cleared to zero, which can be implemented using the application program or
when a compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the ST0ON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the
pulse width. A compare match from Comparator A will also generate a STM interrupt. The counter
can only be reset back to zero when the ST0ON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The ST0CCLR and ST0DPX bits are not used
in this Mode.
Leading Edge Trailing Edge

S/W Command S/W Command
SET“ST0ON” ST0ON bit ST0ON bit CLR“ST0ON”
or or
0®1 1®0
STCK0 Pin CCRA Compare
Transition Match
STP0/STP0B Output Pin
Pulse Width = CCRA Value
Single Pulse Generation
Rev. 1.40 65 October 29, 2020

BC68F2123
Counter Value ST0M [1:0] = 10 ; ST0IO [1:0] = 11

Counter stopped
by CCRA Counter Reset when
ST0ON returns high
CCRA
Resume Counter Stops
Pause by software
CCRP
Time
ST0ON
Auto. set by
Software Cleared by STCK0 pin Software
Trigger CCRA match Software Software Software Trigger
Trigger Trigger Clear
STCK0 pin
STCK0 pin
ST0PAU Trigger
ST0POL
No CCRP Interrupts
CCRP Int. Flag generated
STMP0F
CCRA Int. Flag

STMA0F
STM O/P Pin

(ST0OC=1)
STM O/P Pin

(ST0OC=0)
Pulse Width Output Inverts
set by CCRA when ST0POL = 1
Single Pulse Mode

Note: 1. Counter stopped by CCRA match
2. CCRP is not used
3. The pulse is triggered by setting the ST0ON bit high
4. In the Single Pulse Mode, ST0IO [1:0] must be set to "11" and can not be changed.
Rev. 1.40 66 October 29, 2020

BC68F2123
Capture Input Mode

To select this mode bits ST0M1 and ST0M0 in the STM0C1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal is
supplied on the STP0I, whose active edge can be either a rising edge, a falling edge or both rising
and falling edges; the active edge transition type is selected using the ST0IO1 and ST0IO0 bits in
the STM0C1 register. The counter is started when the ST0ON bit changes from low to high which is
initiated using the application program.
When the required edge transition appears on the STP0I the present value in the counter will be
latched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur on
the STP0I the counter will continue to free run until the ST0ON bit changes from high to low. When
a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value
can be used to control the maximum counter value. When a CCRP compare match occurs from
Comparator P, a STM interrupt will also be generated. Counting the number of overflow interrupt
signals from the CCRP can be a useful method in measuring long pulse widths. The ST0IO1 and
ST0IO0 bits can select the active trigger edge on the STP0I to be a rising edge, falling edge or both
edge types. If the ST0IO1 and ST0IO0 bits are both set high, then no capture operation will take
place irrespective of what happens on the STP0I, however it must be noted that the counter will
continue to run.
The ST0CCLR and ST0DPX bits are not used in this Mode.
Rev. 1.40 67 October 29, 2020

BC68F2123
Counter Value ST0M [1:0] = 01

Counter cleared by
CCRP
Counter Counter
Stop Reset
CCRP
YY Resume
Pause
XX
Time
ST0ON
ST0PAU
Active Active Active
edge edge edge
STM capture
pin STP0I
CCRA Int.
Flag STMA0F
CCRP Int.
Flag STMP0F
CCRA
Value
XX YY XX YY
ST0IO [1:0]
Value
00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disable Capture
Capture Input Mode

Note: 1. ST0M[1:0]=01 and active edge set by the ST0IO[1:0] bits
2. A TM Capture input pin active edge transfers the counter value to CCRA
3. The ST0CCLR and ST0DPX bits are not used
4. No output function – ST0OC and ST0POL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to
zero.
Rev. 1.40 68 October 29, 2020

BC68F2123
Periodic Type TM – PTM

The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can
also be controlled with two external input pins and can drive two external output pins.
TM Type TM Name TM Input Pin TM Output Pin
10-bit PTM PTM1 PTCK1, PTP1I PTP1
Periodic TM Operation
At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock
source. There are two internal comparators with the names, Comparator A and Comparator P. These
comparators will compare the value in the counter with the CCRA and CCRP registers.
The only way of changing the value of the 10-bit counter using the application program, is to
clear the counter by changing the PT1ON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Periodic
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control the output pin. All operating setup conditions are
selected using relevant internal registers.
CCRP
Comparator P Match
10-bit Comparator P PTMP1F Interrupt
fSYS/4 000
fSYS 001 PT1OC
b0~b9
fH/16 010
fH/64 011 Counter Clear 0 Output Polarity
10-bit Count-up Counter PTP1
fTBC 100 1 Control Control
fTBC 101 PT1ON PT1CCLR
110 PT1PAU b0~b9 PT1M1, PT1M0 PT1POL
PTCK1 111 PT1IO1, PT1IO0
Comparator A Match
10-bit Comparator A PTMA1F Interrupt
PT1CK2~PT1CK0
PT1IO1, PT1IO0 PT1CKS
Edge 0 PTP1I
CCRA
Detector 1
Note: The PTM1 external pins are pin-shared with other functions, so before using the PTM1
functions, the pin-shared function registers must be set properly to enable the PTM1 pin
function. The PTCK1 and PTP1I pins, if used, must also be set as an input by setting the
corresponding bits in the port control register.
Periodic Type TM Block Diagram
Rev. 1.40 69 October 29, 2020

BC68F2123
Periodic Type TM Register Description

Overall operation of the Periodic TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store
the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which
setup the different operating and control modes.
Register Bit
Name 7 6 5 4 3 2 1 0
PTM1C0 PT1PAU PT1CK2 PT1CK1 PT1CK0 PT1ON — — —
PTM1C1 PT1M1 PT1M0 PT1IO1 PT1IO0 PT1OC PT1POL PT1CKS PT1CCLR
PTM1DL D7 D6 D5 D4 D3 D2 D1 D0
PTM1DH — — — — — — D9 D8
PTM1AL D7 D6 D5 D4 D3 D2 D1 D0
PTM1AH — — — — — — D9 D8
PTM1RPL D7 D6 D5 D4 D3 D2 D1 D0
PTM1RPH — — — — — — D9 D8
10-bit Periodic TM Register List
• PTM1C0 Register
Bit 7 6 5 4 3 2 1 0
Name PT1PAU PT1CK2 PT1CK1 PT1CK0 PT1ON — — —
R/W R/W R/W R/W R/W R/W — — —
POR 0 0 0 0 0 — — —
Bit 7 PT1PAU: PTM1 Counter Pause Control

0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6~4 PT1CK2~PT1CK0: Select PTM1 Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: fTBC
110: PTCK1 rising edge clock
111: PTCK1 falling edge clock
These three bits are used to select the clock source for the TM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fTBC is another internal clock, the details of which can be found
in the oscillator section.
Bit 3 PT1ON: PTM1 Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the
counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the
counter from counting and turn off the TM which will reduce its power consumption.
When the bit changes state from low to high the internal counter value will be reset to
zero, however when the bit changes from high to low, the internal counter will retain
its residual value until the bit returns high again.
Rev. 1.40 70 October 29, 2020

BC68F2123
If the TM is in the Compare Match Output Mode then the TM output pin will be reset
to its initial condition, as specified by the TM Output control bit, when the bit changes
from low to high.
• PTM1C1 Register
Bit 7 6 5 4 3 2 1 0
Name PT1M1 PT1M0 PT1IO1 PT1IO0 PT1OC PT1POL PT1CKS PT1CCLR
POR 0 0 0 0 0 0 0 0
Bit 7~6 PT1M1~ PT1M0: Select PTM1 Operation Mode

00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Output Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation
the TM should be switched off before any changes are made to the PT1M1 and
PT1M0 bits. In the Timer/Counter Mode, the PTM output pin state is undefined.
Bit 5~4 PT1IO1~ PT1IO0: Select PTM1 External Pin Function
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/Single Pulse Output Mode
00: PWM Output inactive state
01: PWM Output active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of PTP1I or PTCK1
01: Input capture at falling edge of PTP1I or PTCK1
10: Input capture at falling/rising edge of PTP1I or PTCK1
11: Input capture disabled
Timer/counter Mode
Unused
These two bits are used to determine how the TM external pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the TM is running.
In the Compare Match Output Mode, the PT1IO1 and PT1IO0 bits determine how
the TM output pin changes state when a compare match occurs from the Comparator
A. The TM output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When these bits are
both zero, then no change will take place on the output. The initial value of the TM
output pin should be setup using the PT1OC bit. Note that the output level requested
by the PT1IO1 and PT1IO0 bits must be different from the initial value setup using
the PT1OC bit otherwise no change will occur on the TM output pin when a compare
match occurs. After the TM output pin changes state, it can be reset to its initial level
by changing the level of the PT1ON bit from low to high.
In the PWM Output Mode, the PT1IO1 and PT1IO0 bits determine how the TM output
pin changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to change the values of the
PT1IO1 and PT1IO0 bits only after the TM has been switched off. Unpredictable PWM
outputs will occur if the PT1IO1 and PT1IO0 bits are changed when the TM is running.
Rev. 1.40 71 October 29, 2020

BC68F2123
Bit 3 PT1OC: PTP1 Output control bit

0: Initial low
1: Initial high
PWM Mode/ Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon
whether TM is being used in the Compare Match Output Mode or in the PWM Mode/
Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In
the Compare Match Output Mode it determines the logic level of the TM output pin
before a compare match occurs. In the PWM Mode it determines if the PWM signal is
active high or active low.
Bit 2 PT1POL: PTP1 Output polarity Control
0: non-inverted
1: inverted
This bit controls the polarity of the PTP1 output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
PTM1 is in the Timer/Counter Mode.
Bit 1 PT1CKS: PTM1 capture trigger source select
0: From PTP1I
1: From PTCK1 pin
Bit 0 PT1CCLR: Select PTM1 Counter clear condition
0: PTM Comparatror P match
1: PTM Comparatror A match
This bit is used to select the method which clears the counter. Remember that the
Periodic TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the PT1CCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The PT1CCLR bit is not
used in the PWM, Single Pulse or Input Capture Mode.
• PTM1DL Register
Bit 7 6 5 4 3 2 1 0
R/W R R R R R R R R
POR 0 0 0 0 0 0 0 0
Bit 7~0 PTM1DL: PTM1 Counter Low Byte Register bit 7 ~ bit 0
PTM1 10-bit Counter bit 7 ~ bit 0
• PTM1DH Register
Bit 7 6 5 4 3 2 1 0
Name — — — — — — D9 D8
R/W — — — — — — R R
POR — — — — — — 0 0

Bit 1~0 PTM1DH: PTM1 Counter High Byte Register bit 1 ~ bit 0
PTM1 10-bit Counter bit 9 ~ bit 8
Rev. 1.40 72 October 29, 2020

BC68F2123
• PTM1AL Register
Bit 7 6 5 4 3 2 1 0
POR 0 0 0 0 0 0 0 0
Bit 7~0 PTM1AL: PTM1 CCRA Low Byte Register bit 7 ~ bit 0
PTM1 10-bit CCRA bit 7 ~ bit 0
• PTM1AH Register
Bit 7 6 5 4 3 2 1 0
Name — — — — — — D9 D8
R/W — — — — — — R/W R/W
POR — — — — — — 0 0

Bit 1~0 PTM1AH: PTM1 CCRA High Byte Register bit 1 ~ bit 0
PTM1 10-bit CCRA bit 9 ~ bit 8
• PTM1RPL Register
Bit 7 6 5 4 3 2 1 0
POR 0 0 0 0 0 0 0 0
Bit 7~0 PTM1RPL: PTM1 CCRP Low Byte Register bit 7 ~ bit 0
PTM1 10-bit CCRP bit 7 ~ bit 0
• PTM1RPH Register
Bit 7 6 5 4 3 2 1 0
Name — — — — — — D9 D8
R/W — — — — — — R/W R/W
POR — — — — — — 0 0

Bit 1~0 PTM1RPH: PTM1 CCRP High Byte Register bit 1 ~ bit 0
PTM1 10-bit CCRP bit 9 ~ bit 8
Rev. 1.40 73 October 29, 2020

BC68F2123
Periodic Type TM Operating Modes

The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the PT1M1 and PT1M0 bits in the PTM1C1 register.

To select this mode, bits PT1M1 and PT1M0 in the PTM1C1 register, should be all cleared to
00 respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the PT1CCLR bit is low, there are two ways in which the counter can be
cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits
are all zero which allows the counter to overflow. Here both the PTMA1F and PTMP1F interrupt
request flags for Comparator A and Comparator P respectively, will both be generated.
If the PT1CCLR bit in the PTM1C1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the PTMA1F interrupt request flag will
be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore
when PT1CCLR is high no PTMP1F interrupt request flag will be generated. In the Compare
Match Output Mode, the CCRA can not be set to "0". If the CCRA bits are all zero, the counter will
overflow when it reaches its maximum 10-bit, 3FF Hex, value, however here the PTMA1F interrupt
request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the TM output pin, will change state.
The TM output pin condition however only changes state when a PTMA1F interrupt request flag is
generated after a compare match occurs from Comparator A. The PTMP1F interrupt request flag,
generated from a compare match from Comparator P, will have no effect on the TM output pin.
The way in which the TM output pin changes state are determined by the condition of the PT1IO1
and PT1IO0 bits in the PTM1C1 register. The TM output pin can be selected using the PT1IO1
and PT1IO0 bits to go high, to go low or to toggle from its present condition when a compare
match occurs from Comparator A. The initial condition of the TM output pin, which is setup after
the PT1ON bit changes from low to high, is setup using the PT1OC bit. Note that if the PT1IO1,
PT1IO0 bits are zero then no pin change will take place.
Rev. 1.40 74 October 29, 2020

BC68F2123
Counter Value Counter overflow

PT1CCLR = 0; PT1M [1:0] = 00
CCRP > 0
CCRP=0
Counter cleared by CCRP value
0x3FF
CCRP > 0 Counter
Resume Restart
CCRP
Pause Stop
CCRA
Time
PT1ON
PT1PAU
PT1POL
CCRP Int. Flag

PTM1PF
CCRA Int. Flag

PTM1AF
PTM1 O/P Pin

Output pin set to PTM1AF flag. Remains High Output Inverts when
Output Toggle
initial Level Low if until reset by PT1ON bit PT1POL is high
with PTM1AF flag Output Pin
PT1OC=0 Reset to Initial value
Here PT1IO [1:0] = 11 Note PT1IO [1:0] = 10 Output controlled by other
Toggle Output select Active High Output select pin-shared function
Compare Match Output Mode – PT1CCLR=0

Note: 1. With PT1CCLR=0 – a Comparator P match will clear the counter
2. The TM output pin is controlled only by the PTMA1F flag
3. The output pin is reset to initial state by a PT1ON bit rising edge
Rev. 1.40 75 October 29, 2020

BC68F2123
Counter Value PT1CCLR = 1; PT1M [1:0] = 00
CCRA > 0 Counter cleared by CCRA value CCRA = 0

Counter overflow
0x3FF
Resume CCRA=0
CCRA
Pause Stop Counter Restart
CCRP
Time
PT1ON
PT1PAU
PT1POL
No PTM1AF flag
generated on
CCRA overflow
CCRA Int.
Flag PTM1AF
CCRP Int.
Flag PTM1PF
PTM1PF not Output does

generated not change
PTM1 O/P
Pin
PTM1AF flag. Remains High Output Inverts
Output Toggle
Output pin set to until reset by PT1ON bit when PT1POL is high
with PTM1AF flag Output Pin
initial Level Low if
Note PT1IO [1:0] = 10 Reset to Initial value
PT1OC=0 Here PT1IO [1:0] = 11
Active High Output select Output controlled by
Compare Match Output Mode – PT1CCLR=1

Note: 1. With PT1CCLR=1 – a Comparator A match will clear the counter
2. The TM output pin is controlled only by the PTMA1F flag
3. The output pin is reset to initial state by a PT1ON rising edge
4. The PTMP1F flag is not generated when PT1CCLR=1
Rev. 1.40 76 October 29, 2020

BC68F2123
Timer/Counter Mode
To select this mode, bits PT1M1 and PT1M0 in the PTM1C1 register should all be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the
TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the TM output pin is not used in this
mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode

To select this mode, bits PT1M1 and PT1M0 in the PTM1C1 register should be set to 10 respectively
and also the PT1IO1 and PT1IO0 bits should be set to 10 respectively. The PWM function within
the TM is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the PT1CCLR bit has no effect as the PWM
period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, CCRP
register pair is used to clear the internal counter and thus control the PWM waveform frequency,
while the CCRA register pair is used to control the duty cycle. The PWM waveform frequency and
duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The PT1OC bit in the PTM1C1 register is used to
select the required polarity of the PWM waveform while the two PT1IO1 and PT1IO0 bits are used
to enable the PWM output or to force the TM output pin to a fixed high or low level. The PT1POL
bit is used to reverse the polarity of the PWM output waveform.
• 10-bit PTM, PWM Output Mode, Edge-aligned Mode

CCRP 1~1023 0
Period 1~1023 1024
Duty CCRA
If fSYS=8MHz, PTM clock source select fSYS/4, CCRP=512 and CCRA=128,

The PTM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 4kHz, duty = 128/512 = 25%
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
Rev. 1.40 77 October 29, 2020

BC68F2123
Counter Value
PT1M [1:0] = 10
Counter cleared by
CCRP
Counter Reset when
PT1ON returns high
CCRP
Counter Stop if
Pause Resume
PT1ON bit low
CCRA
Time
PT1ON
PT1PAU
PTPOL
CCRA Int. Flag

PTM1AF
CCRP Int. Flag

PTM1PF
PTM1 O/P Pin

(PT1OC=1)
PTM1 O/P Pin
(PT1OC=0)

set by CCRA
operation
Output controlled by Output Inverts
other pin-shared function When PT1POL = 1
PWM Period set by CCRP
PWM Output Mode

Note: 1. Here Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when PT1IO[1:0]=00 or 01
4. The PT1CCLR bit has no influence on PWM operation
Rev. 1.40 78 October 29, 2020

BC68F2123
Single Pulse Output Mode

To select this mode, the required bit pairs, PT1M1 and PT1M0 should be set to 10 respectively and
also the corresponding PT1IO1 and PT1IO0 bits should be set to 11 respectively. The Single Pulse
Output Mode, as the name suggests, will generate a single shot pulse on the PTM output pin.
The trigger for the pulse output leading edge is a low to high transition of the PT1ON bit, which
can be implemented using the application program. However in the Single Pulse Output Mode, the
PT1ON bit can also be made to automatically change from low to high using the external PTCK1
pin, which will in turn initiate the Single Pulse output. When the PT1ON bit transitions to a high
level, the counter will start running and the pulse leading edge will be generated. The PT1ON bit
should remain high when the pulse is in its active state. The generated pulse trailing edge will be
generated when the PT1ON bit is cleared to zero, which can be implemented using the application
program or when a compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the PT1ON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control
the pulse width. A compare match from Comparator A will also generate TM interrupts. The counter
can only be reset back to zero when the PT1ON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The PT1CCLR bit is also not used.
CCRA CCRA
Leading Edge Trailing Edge
S/W Command S/W Command
SET“PT1ON” PT1ON bit PT1ON bit CLR“PT1ON”
or or
0à1 1à0
PTCK1 Pin CCRA Compare
Transition Match
PTP1 Output Pin
Pulse Width = CCRA Value
Single Pulse Generation
Rev. 1.40 79 October 29, 2020

BC68F2123
Counter Value PT1M [1:0] = 10 ; PT1IO [1:0] = 11

Counter stopped by
CCRA
Counter Reset when
PT1ON returns high
CCRA
Resume Counter Stops
Pause by software
CCRP
Time
PT1ON
Auto. set by
PTCK1 pin
Software Cleared by Software
Trigger CCRA match Software Software Software Trigger
Trigger Trigger Clear
PTCK1 pin
PTCK1 pin
PT1PAU Trigger
PT1POL
No CCRP
CCRP Int. Flag Interrupts
PTM1PF generated
CCRA Int. Flag

PTM1AF
PTM1 O/P Pin

(PT1OC=1)
PTM1 O/P Pin

(PT1OC=0)
Pulse Width Output Inverts
set by CCRA when PT1POL = 1
Single Pulse Mode

Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse is triggered by the PTCK1 pin or by setting the PT1ON bit high
4. A PTCK1 pin active edge will automatically set the PT1ON bit high
5. In the Single Pulse Mode, PT1IO [1:0] must be set to "11" and can not be changed.
Rev. 1.40 80 October 29, 2020

BC68F2123
Capture Input Mode

To select this mode bits PT1M1 and PT1M0 in the PTM1C1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal
is supplied on the PTP1I or PTCK1 pin, selected by the PT1CKS bit in the PTM1C1 register. The
input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the
active edge transition type is selected using the PT1IO1 and PT1IO0 bits in the PTM1C1 register.
The counter is started when the PT1ON bit changes from low to high which is initiated using the
application program.
When the required edge transition appears on the PTP1I or PTCK1 pin the present value in the
counter will be latched into the CCRA register and a TM interrupt generated. Irrespective of what
events occur on the PTP1I or PTCK1 pin the counter will continue to free run until the PT1ON bit
changes from high to low. When a CCRP compare match occurs the counter will reset back to zero;
in this way the CCRP value can be used to control the maximum counter value. When a CCRP
compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the
number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse
widths. The PT1IO1 and PT1IO0 bits can select the active trigger edge on the PTP1I or PTCK1 pin
to be a rising edge, falling edge or both edge types. If the PT1IO1 and PT1IO0 bits are both set high,
then no capture operation will take place irrespective of what happens on the PTP1I or PTCK1 pin,
however it must be noted that the counter will continue to run. The PT1CCLR, PT1OC and PT1POL
bits are not used in this Mode..
Rev. 1.40 81 October 29, 2020

BC68F2123
Counter Value PT1M[1:0] = 01

Counter cleared by
CCRP
Counter Counter
Stop Reset
CCRP
YY Resume
Pause
XX
Time
PT1ON
PT1PAU
Active Active
edge edge Active edge
PTM1 Capture Pin

PTP1I or PTCK1
CCRA Int.
Flag PTM1AF
CCRP Int.
Flag PTM1PF
CCRA Value XX YY XX YY
PT1IO [1:0] Value 00 - Rising edge 01 - Falling edge 10 - Both edges 11 - Disable Capture
Capture Input Mode

Note: 1. PT1M[1:0]=01 and active edge set by the PT1IO[1:0] bits
2. A TM Capture input pin active edge transfers counter value to CCRA
3. The PT1CCLR bit is not used
4. No output function – PT1OC and PT1POL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to
zero
Rev. 1.40 82 October 29, 2020

BC68F2123
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an
internal function such as a Timer Module requires microcontroller attention, their corresponding
interrupt will enforce a temporary suspension of the main program allowing the microcontroller to
direct attention to their respective needs. The device contains several external interrupt and internal
interrupt functions. The external interrupt is generated by the action of the external INT pin, while
the internal interrupts are generated by various internal functions such as the TMs, EEPROM write
and Time Bases, etc.
Interrupt Registers
Overall interrupt control, which basically means the setting of request flags when certain
microcontroller conditions occur and the setting of interrupt enable bits by the application program,
is controlled by a series of registers, located in the Special Purpose Data Memory, as shown
in the accompanying table. The number of registers falls into three categories. The first is the
INTC0~INTC1 registers which setup the primary interrupts, the second is the MFI0~MFI1 registers
which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external
interrupt trigger edge type.
Each register contains a number of enable bits to enable or disable individual registers as well as
interrupt flags to indicate the presence of an interrupt request. The naming convention of these
follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of
that interrupt followed by either an "E" for enable/disable bit or "F" for request flag.
Function Enable Bit Request Flag Notes
Global EMI — —
External Interrupt INTE INTF —
Time Base TBnE TBnF n=0~1
EEPROM DEE DEF —
Multi-function MFnE MFnF n=0~1
STMP0E STMP0F
STM —
STMA0E STMA0F
PTMP1E PTMP1F
PTM —
PTMA1E PTMA1F
Interrupt Register Bit Naming Conventions
Register Bit
Name 7 6 5 4 3 2 1 0
INTEG — — — — — — INT0S1 INT0S0
INTC0 — TB1F TB0F INTF TB1E TB0E INTE EMI
INTC1 MF1F — DEF MF0F MF1E — DEE MF0E
MFI0 — — STMA0F STMP0F — — STMA0E STMP0E
MFI1 — — PTMA1F PTMP1F — — PTMA1E PTMP1E
Interrupt Register List
Rev. 1.40 83 October 29, 2020

BC68F2123
• INTEG Register
Bit 7 6 5 4 3 2 1 0
Name — — — — — — INT0S1 INT0S0
R/W — — — — — — R/W R/W
POR — — — — — — 0 0

Bit 1~0 INT0S1~INT0S0: Defines INT pin external interrupt active edge
00: Disable
01: Rising edge
10: Falling edge
11: Rising and falling edges
• INTC0 Register
Bit 7 6 5 4 3 2 1 0
Name — TB1F TB0F INTF TB1E TB0E INTE EMI
R/W — R/W R/W R/W R/W R/W R/W R/W
POR — 0 0 0 0 0 0 0

Bit 6 TB1F: Time Base 1 interrupt request flag
0: No request
1: Interrupt request
Bit 5 TB0F: Time Base 0 interrupt request flag
0: No request
Bit 4 INTF: INT interrupt request flag
0: No request
Bit 3 TB1E: Time Base 1 interrupt control
0: Disable
1: Enable
Bit 2 TB0E: Time Base 0 interrupt control
0: Disable
1: Enable
Bit 1 INTE: INT interrupt control
0: Disable
1: Enable
Bit 0 EMI: Global interrupt control
0: Disable
1: Enable
• INTC1 Register
Bit 7 6 5 4 3 2 1 0
Name MF1F — DEF MF0F MF1E — DEE MF0E
R/W R/W — R/W R/W R/W — R/W R/W
POR 0 — 0 0 0 — 0 0
Bit 7 MF1F: Multi-function interrupt 1 request flag

0: No request
Bit 5 DEF: Data EEPROM interrupt request flag
0: No request
Rev. 1.40 84 October 29, 2020

BC68F2123
Bit 4 MF0F: Multi-function interrupt 0 request flag

0: No request
Bit 3 MF1E: Multi-function interrupt 1 control
0: Disable
1: Enable
Bit 1 DEE: Data EEPROM interrupt control
0: Disable
1: Enable
Bit 0 MF0E: Multi-function interrupt 0 control
0: Disable
1: Enable
• MFI0 Register
Bit 7 6 5 4 3 2 1 0
Name — — STMA0F STMP0F — — STMA0E STMP0E
R/W — — R/W R/W — — R/W R/W
POR — — 0 0 — — 0 0

Bit 5 STMA0F: STM0 Comparator A match interrupt request flag
0: No request
Bit 4 STMP0F: STM0 Comparator P match interrupt request flag
0: No request
Bit 1 STMA0E: STM0 Comparator A match interrupt control
0: Disable
1: Enable
Bit 0 STMP0E: STM0 Comparator P match interrupt control
0: Disable
1: Enable
• MFI1 Register
Bit 7 6 5 4 3 2 1 0
Name — — PTMA1F PTMP1F — — PTMA1E PTMP1E
R/W — — R/W R/W — — R/W R/W
POR — — 0 0 — — 0 0

Bit 5 PTMA1F: PTM1 Comparator A match interrupt request flag
0: No request
Bit 4 PTMP1F: PTM1 Comparator P match interrupt request flag
0: No request
Bit 1 PTMA1E: PTM1 Comparator A match interrupt control
0: Disable
1: Enable
Bit 0 PTMP1E: PTM1 Comparator P match interrupt control
0: Disable
1: Enable
Rev. 1.40 85 October 29, 2020

BC68F2123
Interrupt Operation
When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A
match etc., the relevant interrupt request flag will be set. Whether the request flag actually generates
a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable
bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is
zero then although the interrupt request flag is set an actual interrupt will not be generated and the
program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to
zero, will disable all interrupts.
When an interrupt is generated, the Program Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will
then fetch its next instruction from this interrupt vector. The instruction at this vector will usually
be a "JMP" which will jump to another section of program which is known as the interrupt service
routine. Here is located the code to control the appropriate interrupt. The interrupt service routine
must be terminated with a "RETI", which retrieves the original Program Counter address from
the stack and allows the microcontroller to continue with normal execution at the point where the
interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
accompanying diagrams with their order of priority. Some interrupt sources have their own
individual vector while others share the same multi-function interrupt vector. Once an interrupt
subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit,
EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring.
However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded.
If an interrupt requires immediate servicing while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until
the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from
becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that
is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or
IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set
before the device is in SLEEP or IDLE Mode.
EMI auto disabled in ISR

Legend
xxF Request Flag, no auto reset in ISR Interrupt Request Enable Master
Name Flags Bits Enable Vector Priority
xxF Request Flag, auto reset in ISR High
INT Pin INTF INTE EMI 04H
xxE Enable Bits
Interrupt
Time Base 0 TB0F TB0E EMI 08H
Request Enable
Name Flags Bits
Time Base 1 TB1F TB1E EMI 0CH
STM P STMP0F STMP0E
STM A STMA0F STMA0E M. Funct. 0 MF0F MF0E EMI 10H
EEPROM DEF DEE EMI 14H

PTM P PTMP1F PTMP1E
PTM A PTMA1F PTMA1E M. Funct. 1 MF1F MF1E EMI 1CH

Low
Interrupts contained within
Multi-Function Interrupts
Interrupt Structure
Rev. 1.40 86 October 29, 2020

BC68F2123
External Interrupt
The external interrupt is controlled by signal transitions on the pin INT. An external interrupt
request will take place when the external interrupt request flag, INTF, is set, which will occur
when a transition, whose type is chosen by the edge select bits, appears on the external interrupt
pin. To allow the program to branch to its respective interrupt vector address, the global interrupt
enable bit, EMI, and respective external interrupt enable bit, INTE, must first be set. Additionally
the correct interrupt edge type must be selected using the INTEG register to enable the external
interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared
with I/O pin, it can only be configured as external interrupt pin if its external interrupt enable bit
in the corresponding interrupt register has been set and the external interrupt pin is selected by the
corresponding pin-shared function selection bits. The pin must also be setup as an input by setting
the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full
and the correct transition type appears on the external interrupt pin, a subroutine call to the external
interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag,
INTF will be automatically reset and the EMI bit will be automatically cleared to disable other
interrupts. Note that any pull-high resistor selections on the external interrupt pin will remain valid
even if the pin is used as an external interrupt input.
The INTEG register is used to select the type of active edge that will trigger the external interrupt.
A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt.
Note that the INTEG register can also be used to disable the external interrupt function.
Time Base Interrupts

The function of the Time Base Interrupts is to provide regular time signal in the form of an internal
interrupt. They are controlled by the overflow signals from their respective timer functions. When
these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the
program to branch to their respective interrupt vector addresses, the global interrupt enable bit,
EMI and Time Base interrupt enable bits, TB0E or TB1E, must first be set. When the interrupt is
enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector
locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F
or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts.
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their
clock sources originate from the internal clock source fSYS/4 or fTBC and then pass through a divider,
the division ratio of which is selected by programming the appropriate bits in the TBC register to
obtain longer interrupt periods whose value ranges. The clock source which in turn controls the
Time Base interrupt period is selected using the TBCK bit in the TBC register.
TB02 ~ TB00
÷ 28 ~ 215 Time Base 0 Interrupt

fSYS/4 M fTB
U
fTBC X
LIRC
÷ 212 ~ 215 Time Base 1 Interrupt
TBCK Bit
TB11 ~ TB10
Time Base Interrupts
Rev. 1.40 87 October 29, 2020

BC68F2123
• TBC Register
Bit 7 6 5 4 3 2 1 0
Name TBON TBCK TB11 TB10 — TB02 TB01 TB00
R/W R/W R/W R/W R/W — R/W R/W R/W
POR 0 0 1 1 — 1 1 1
Bit 7 TBON: TB0 and TB1 Control

0: Disable
1: Enable
Bit 6 TBCK: Select TB0 and TB1 clock source
0: fTBC
1: fSYS/4
Bit 5~4 TB11~TB10: Select Time Base 1 Time-out Period
00: 212/fTB
01: 213/fTB
10: 214/fTB
11: 215/fTB
Bit 2~0 TB02~TB00: Select Time Base 0 Time-out Period
000: 28/fTB
001: 29/fTB
010: 210/fTB
011: 211/fTB
100: 212/fTB
101: 213/fTB
110: 214/fTB
111: 215/fTB
Multi-function Interrupts
Within the device there are two Multi-function interrupts. Unlike the other independent interrupts,
these interrupts have no independent sources, but rather are formed from other existing interrupt
sources, namely the TM Interrupts.
A Multi-function interrupt request will take place when any of the Multi-function interrupt request
flags, MFnF are set. The Multi-function interrupt flags will be set when any of their included
functions generate an interrupt request flag. To allow the program to branch to its respective
interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and
either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine
call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the
related Multi-function request flag will be automatically reset and the EMI bit will be automatically
cleared to disable other interrupts.
However, it must be noted that, although the Multi-function Interrupt flags will be automatically
reset when the interrupt is serviced, the request flags from the original source of the Multi-function
interrupts will not be automatically reset and must be manually reset by the application program.
EEPROM Write Interrupt

An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set,
which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective
interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit,
DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write
cycle ends, a subroutine call to the respective EEPROM Interrupt vector will take place. When the
EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts
and the EEPROM interrupt request flag also will be automatically cleared.
Rev. 1.40 88 October 29, 2020

BC68F2123
TM Interrupts
The Standard and Periodic Type TMs each have two interrupts, one comes from the comparator A
match situation and the other comes from the comparator P match situation. All of the TM interrupts
are contained within the Multi-function Interrupts. For all of the TM types there are two interrupt
request flags and two enable control bits. A TM interrupt request will take place when any of the TM
request flags are set, a situation which occurs when a TM comparator P or A match situation happens.
To allow the program to branch to its respective interrupt vector address, the global interrupt enable
bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE,
must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match
situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take
place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other
interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt
request flags will not be automatically cleared, they have to be cleared by the application program.
Interrupt Wake-up Function

Each of the interrupt functions has the capability of waking up the microcontroller when in the
SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to
high and is independent of whether the interrupt is enabled or not. Therefore, even though the device
is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge
transitions on the external interrupt pin may cause their respective interrupt flag to be set high and
consequently generate an interrupt.
Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up
function is to be disabled then the corresponding interrupt request flag should be set high before the device
enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function.
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will remain in this condition in the
interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt
service routine is executed, as only the Multi-function interrupt request flag will be automatically
cleared, the individual request flag for the function needs to be cleared by the application program.
It is recommended that programs do not use the "CALL" instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will be
damaged once a CALL subroutine is executed in the interrupt subroutine.
Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is
required to prevent a certain interrupt from waking up the microcontroller then its respective request
flag should be first set high before enter the SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the
contents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service routine.
To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI
instruction in addition to executing a return to the main program also automatically sets the EMI bit high
to allow further interrupts. The RET instruction however only executes a return to the main program
leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts.
Rev. 1.40 89 October 29, 2020

BC68F2123
Low Voltage Detector – LVD

The device has a Low Voltage Detector function, also known as LVD. This enabled the device to
monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain
level. This function may be especially useful in battery applications where the supply voltage will
gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated.
LVD Register
The Low Voltage Detector function is controlled using a single register with the name LVDC. Three
bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which
a low voltage condition will be determined. A low voltage condition is indicated when the LVDO
bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage
value. The ENLVD bit is used to control the overall on/off function of the low voltage detector.
Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the
internal low voltage detector circuits. As the low voltage detector will consume a certain amount of
power, it may be desirable to switch off the circuit when not in use, an important consideration in
power sensitive battery powered applications.
• LVDC Register
Bit 7 6 5 4 3 2 1 0
Name — — LVDO ENLVD — VLVD2 VLVD1 VLVD0
R/W — — R R/W — R/W R/W R/W
POR — — 0 0 — 0 0 0

Bit 5 LVDO: LVD Output flag
0: No Low Voltage Detected
1: Low Voltage Detected
Bit 4 ENLVD: Low Voltage Detector Enable control
0: Disable
1: Enable
Bit 2~0 VLVD2~VLVD0: LVD Voltage selection
000: 2.0V
001: 2.2V
010: 2.4V
011: 2.7V
100: 3.0V
101: 3.3V
110: 3.6V
111: 4.0V
Rev. 1.40 90 October 29, 2020

BC68F2123
LVD Operation
The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a
pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V.
When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will
be set high indicating a low power supply voltage condition. When the device is in the SLEEP or
IDLE mode, the low voltage detector will be automatically disabled. After enabling the Low Voltage
Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO
bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of
VLVD, there may be multiple bit LVDO transitions.
VDD
VLVD
LVDEN
LVDO
tLVDS
LVD Operation
RF Transmitter
The RF transmitter can operate in the 315MHz, 433MHz, 868MHz and 915MHz frequency bands.
It consists of a highly integrated fractional-N synthesizer and a Class-E power amplifier and can
support OOK modulation with symbol rate of up to 25ksps. An I2C interface is also included for the
frequency, output power and other parameter configuration when operating in the I2C mode.
DVDDRF DVDD
XOSC XOIN
SDA/DIN VDDRF
Freq.
Digital
Control Synth.
Logic OOK RFOUT
PA
SCL/PCLK Modulator
Ramp
Control
PAVSS
VDDRF VDDRF PAVSS VSSRF_PA

VEF Fuse &
Data Memory
GND EP
: Exposed Pad
Rev. 1.40 91 October 29, 2020

BC68F2123
State Control
The RF transmitter module has an integrated state control machine that control the state transition
between different modes.
Power On State
Power off
After power up
VDDRF and DVDDRF
Normal Mode
POR l2C Mode

Deep Sleep
Procedure
{DIN keep High

& PCLK Low(>16µs)
Detect High edge} or
DIN L→H
I2C time out(20ms)
or PCLK H→L
I2C Mode
Transmitting
TOFF[3:0]=F DIN keep High

4~32ms Timer Transmit Done
& DIN L→H & PCLK Low(>16µs)
times up & DIN H→L
Detect High edge
Standby
& Time on
After RF transmitter module power-on, the transmitter module will perform a POR procedure and
then automatically enter the Deep Sleep Mode to wait for a transmitting start condition.
When the DIN is pulled high or the PCLK signal changes from high to low, the transmitting is
started. When data transmission is finished and the DIN pin state changes from high to low, the
device will enter the Standby state and the Timer, whose timeout period is determined by DLY_
TOFF bit field in the CFG1 register, will turn on and start to count. The device will return to the
Deep Sleep Mode when the Timer overflows. However, it should be noted that when the DLY_
TOFF[3:0] bit value is "1111", the device will start to transmit again without entering the Deep
Sleep Mode once the DIN pin state changes from low to high.
Sleep tStartup tST Transmit Sleep
STATE
High Stop
DIN Low Valid TX Data Low
PA Out RF Signal
10µs
TX Enabled by DIN Input
Rev. 1.40 92 October 29, 2020

BC68F2123
The transmitter module can enter the I2C mode from the Normal mode. If the PCLK line is pulled
low and stays at low level for more than 16μs, the RF transmitter enters the I2C Mode during which
the RF transmitter special function registers can be configured by using I2C commands. When the
module receives a correct I2C STOP signal followed by the PCLK line pulled low and stay at low
level for more than 16μs, the RF transmitter will return to the Normal Mode.
>16μs tENI2C >16μs tEXI2C

I2C I2C
Start Condition Stop Condition
PCLK/SCL
DIN/SDA
ACK
2 2
Normal Mode into I C Mode I C Serial Programming I2C Mode Terminate
Enter / Exit I2C Mode
In the I2C Mode, the RF transmitter internal relevant registers can be configured using I2C serial
programming. The transmitter only supports the I2C format for byte write, page write, byte read and
page read format. The transmission procedure is shown as below.
It should be noted that the I2C is a non-standard I2C interface, which only supports a single device
for connection.
Symbol definition:
• S: Start symbol
• RS: Repeat Start
• P: Stop symbol
• DADDR[6:0]: device address, 21h
• R/W: read write select, R(0): write, (1): read
• RADDR[7:0]: register address
• ACK: A(0):ACK, NA(1):NAK
• Bus Direction:
host to device:
device to host:
Byte Write
S DADDR[6:0] W A RADDR[7:0] A DATA A P
Page Write
S DADDR[6:0] W A RADDR[7:0] A DATA A DATA(n+1) A DATA(n+x) A P
Byte Read
S DADDR[6:0] W A RADDR[7:0] A RS DADDR[6:0] R A DATA NA P
Page Read
S DADDR[6:0] W A RADDR[7:0] A RS DADDR[6:0] R A DATA(n) A DATA(n+1) A DATA(n+x) NA P
Rev. 1.40 93 October 29, 2020

BC68F2123
tHIGH tLOW Repeated Start

Stop Start
Slave Addres
SCL
SDA
th(DAT) tsu(DAT)
tBUF
th(STA) tsu(STA)
Stop
SRW ACK Data ACK

SCL
SDA
tf(SDA) tr(SDA) tf(SCL) tr(SCL)

tsu(STO)
S = Start (1 bit)
SA = Slave Address (7 bits)
SR = SRW bit (1 bit)
M = Slave device send acknowledge bit (1 bit)
D = Data (8 bits)
A = ACK (RXAK bit for transmitter, TXAK for receiver, 1 bit)
P = Stop (1 bit)
I2C Communication Timing Diagram
RF Transmitter Module Registers

The module can be setup and operated using a series of internal registers. The RF module commands
and data are written into and read from the RF transmitter module using its internal I2C bus. This list
provides a summary of all internal registers.
Register Bit
Address
Name 7 6 5 4 3 2 1 0
00h CFG0 Setting0 XO_TRIM[5:0]
01h CFG1 DLY_TOFF[3:0] Setting1
02h CFG2 D[7:0]
03h CFG3 D7 Setting2 TXPWR[3:0]
04h CFG4 D_N[5:0] BAND_SEL[1:0]
05h CFG5 D_K[11:4]
06h CFG6 D_K[19:12]
07h CFG7 D7 Setting3
Rev. 1.40 94 October 29, 2020

BC68F2123
If the RF transmitter module registers are not programmed using I2C serial programming, it will
have a default state described in the following, determined by register initial values.
Modulation Mode: OOK
Operating Frequency: 433.92MHz
TX Output Power: 10dBm
XTAL Capacitor Load: 16.651pF
Power Off Delay Time: 32ms
• CFG0: Configuration Control Register 0

Address Bit 7 6 5 4 3 2 1 0
Name Setting0 XO_TRIM[5:0]
00h R/W R/W R/W R/W
Initial Value 1 0 1 0 0 0 0 0
Bit 7~6 Setting0: Must be [0b10]

Bit 5~0 XO_TRIM[5:0]: Trim value of the internal capacitor array for different crystal CLOAD
Based on XO fabricated by YOKETAN corporation.
49US 16MHz XO w/ 16pF Cload: The default setting is 1B. Within ±40ppm frequency
error, 1 trim code shift -2.88ppm.
3225SMD 16MHz XO w/16pF C load: The default setting is 28. Within ±20ppm
frequency error, 1 trim code shift -0.37ppm.
Rev. 1.40 95 October 29, 2020

BC68F2123

Address Bit 7 6 5 4 3 2 1 0
Name DLY_TOFF[3:0] Setting1
01h R/W R/W R/W
Bit 7~4 DLY_TOFF[3:0]: Transmitter Auto Power Off Delay Time

t=2ms×(DLY_TOFF[3:0]+2)
0000: 4ms
0001: 6ms
0010: 8ms
:
1110: 32ms
1111: Infinite – Never enter the Deep Sleep Mode

Address Bit 7 6 5 4 3 2 1 0
Name D[7:0]
02h R/W R/W
Bit 7~0 D[7:0]: Reserved bits, cannot be changed

Address Bit 7 6 5 4 3 2 1 0
Name D7 Setting2 TXPWR[3:0]
03h R/W R/W R/W R/W
Bit 7 D7: Reserved bit, cannot be changed

Bit 6~4 Setting 2: Must be [0b100]
Bit 3~0 TXPWR[3:0]: RF Output Power
The device has several output power values which are 0, 5, 10, and 13dBm.
TXPWR[3:0] RF Output Power TXPWR[3:0] RF Output Power Fine Tune Level
0000 0dBm XX00 0
0100 5dBm XX01 1
1000 10dBm XX10 2
1100 13dBm XX11 3
Note that the adjust range: Level 3 > Level 2 > Level 1 > Level 0.
Note: Output power level could vary due to different matching components and
placement on the PCB. The matching variation could significantly impact the
output power level below +5dBm setting.

Address Bit 7 6 5 4 3 2 1 0
Name D_N[5:0] BAND_SEL[1:0]
04h R/W R/W R/W
Bit 7~2 D_N[5:0]: Integer of dividend for MMD
Rev. 1.40 96 October 29, 2020

BC68F2123
Bit 1~0 BAND_SEL[1:0]: Band Frequency Coarse Control

BAND_SEL Frequency
00 315MHz
01 433MHz
10 868MHz
11 915MHz
Note that the BAND_SEL only select an approximate frequency range while the exact
frequency value is determined by the D_N and D_K bit fields.

Address Bit 7 6 5 4 3 2 1 0
Name D_K[11:4]
05h R/W R/W

Address Bit 7 6 5 4 3 2 1 0
Name D_K[19:12]
06h R/W R/W
D_K[19:4]: 16-bit Fractional of dividend for MMD

D_N&D_K example.
X’TAL=16MHz and TX band =433MHz
1. D_N → (433M×Divider)/16M=54.125
Take the integer part → D_N=54-32=22 → 010110
2. D_K → (433M×Divider)/16M=54.125
Take the fractional part → D_K=0.125×220=131072 → 0010-0000-0000-0000
3. The example frequency can be referred in the following table.
Band_SEL Frequency Divider X’TAL D_N[5:0] D_K[19:4]
315MHz 315MHz 2 16MHz 000111 0110-0000-0000-0000
433MHz 433MHz 2 16MHz 010110 0010-0000-0000-0000
433MHz 433.92MHz 2 16MHz 010110 0011-1101-0111-0000
868MHz 868MHz 1 16MHz 010110 0100-0000-0000-0000
915MHz 915MHz 1 16MHz 011001 0011-0000-0000-0000

Address Bit 7 6 5 4 3 2 1 0
Name D7 Setting3
07h R/W R R/W
Bit 7 D7: Reserved bit

Rev. 1.40 97 October 29, 2020

BC68F2123
Application Circuits
VDDRF
VDD
VDD DVDDRF VDDRF
I/O
HOLTEK RF RFOUT
MCU Part
XOIN
I/O Matching Circuit
EP
VSS VSSRF_PA
Rev. 1.40 98 October 29, 2020

BC68F2123
Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data

The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
Rev. 1.40 99 October 29, 2020

BC68F2123
Logical and Rotate Operation

The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
which rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer

Program branching takes the form of either jumps to specified locations using the JMP instruction
or to a subroutine using the CALL instruction. They differ in the sense that in the case of a
subroutine call, the program must return to the instruction immediately when the subroutine has
been carried out. This is done by placing a return instruction "RET" in the subroutine which will
cause the program to jump back to the address right after the CALL instruction. In the case of a JMP
instruction, the program simply jumps to the desired location. There is no requirement to jump back
to the original jumping off point as in the case of the CALL instruction. One special and extremely
useful set of branch instructions are the conditional branches. Here a decision is first made regarding
the condition of a certain data memory or individual bits. Depending upon the conditions, the
program will continue with the next instruction or skip over it and jump to the following instruction.
These instructions are the key to decision making and branching within the program perhaps
determined by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m].i"
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port with
the correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.
Table Read Operations

Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be set as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the "HALT" instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
Rev. 1.40 100 October 29, 2020

BC68F2123
Instruction Set Summary

The following table depicts a summary of the instruction set categorised according to function and
can be consulted as a basic instruction reference using the following listed conventions.
Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic Description Cycles Flag Affected
Arithmetic
ADD A,[m] Add Data Memory to ACC 1 Z, C, AC, OV
ADDM A,[m] Add ACC to Data Memory 1Note Z, C, AC, OV
ADD A,x Add immediate data to ACC 1 Z, C, AC, OV
ADC A,[m] Add Data Memory to ACC with Carry 1 Z, C, AC, OV
ADCM A,[m] Add ACC to Data memory with Carry 1Note Z, C, AC, OV
SUB A,x Subtract immediate data from the ACC 1 Z, C, AC, OV
SUB A,[m] Subtract Data Memory from ACC 1 Z, C, AC, OV
SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory 1Note Z, C, AC, OV
SBC A,[m] Subtract Data Memory from ACC with Carry 1 Z, C, AC, OV
SBCM A,[m] Subtract Data Memory from ACC with Carry, result in Data Memory 1Note Z, C, AC, OV
DAA [m] Decimal adjust ACC for Addition with result in Data Memory 1Note C
Logic Operation
AND A,[m] Logical AND Data Memory to ACC 1 Z
OR A,[m] Logical OR Data Memory to ACC 1 Z
XOR A,[m] Logical XOR Data Memory to ACC 1 Z
ANDM A,[m] Logical AND ACC to Data Memory 1Note Z
ORM A,[m] Logical OR ACC to Data Memory 1Note Z
XORM A,[m] Logical XOR ACC to Data Memory 1Note Z
AND A,x Logical AND immediate Data to ACC 1 Z
OR A,x Logical OR immediate Data to ACC 1 Z
XOR A,x Logical XOR immediate Data to ACC 1 Z
CPL [m] Complement Data Memory 1Note Z
CPLA [m] Complement Data Memory with result in ACC 1 Z
Increment & Decrement
INCA [m] Increment Data Memory with result in ACC 1 Z
INC [m] Increment Data Memory 1Note Z
DECA [m] Decrement Data Memory with result in ACC 1 Z
DEC [m] Decrement Data Memory 1Note Z
Rotate
RRA [m] Rotate Data Memory right with result in ACC 1 None
RR [m] Rotate Data Memory right 1Note None
RRCA [m] Rotate Data Memory right through Carry with result in ACC 1 C
RRC [m] Rotate Data Memory right through Carry 1Note C
RLA [m] Rotate Data Memory left with result in ACC 1 None
RL [m] Rotate Data Memory left 1Note None
RLCA [m] Rotate Data Memory left through Carry with result in ACC 1 C
RLC [m] Rotate Data Memory left through Carry 1Note C
Rev. 1.40 101 October 29, 2020

BC68F2123
Mnemonic Description Cycles Flag Affected

Data Move
MOV A,[m] Move Data Memory to ACC 1 None
MOV [m],A Move ACC to Data Memory 1Note None
MOV A,x Move immediate data to ACC 1 None
Bit Operation
CLR [m].i Clear bit of Data Memory 1Note None
SET [m].i Set bit of Data Memory 1Note None
Branch Operation
JMP addr Jump unconditionally 2 None
SZ [m] Skip if Data Memory is zero 1Note None
SZA [m] Skip if Data Memory is zero with data movement to ACC 1Note None
SZ [m].i Skip if bit i of Data Memory is zero 1Note None
SNZ [m].i Skip if bit i of Data Memory is not zero 1Note None
SIZ [m] Skip if increment Data Memory is zero 1Note None
SDZ [m] Skip if decrement Data Memory is zero 1Note None
SIZA [m] Skip if increment Data Memory is zero with result in ACC 1Note None
SDZA [m] Skip if decrement Data Memory is zero with result in ACC 1Note None
CALL addr Subroutine call 2 None
RET Return from subroutine 2 None
RET A,x Return from subroutine and load immediate data to ACC 2 None
RETI Return from interrupt 2 None
Table Read Operation
TABRD [m] Read table (specific page or current page) to TBLH and Data Memory 2Note None
TABRDL [m] Read table (last page) to TBLH and Data Memory 2Note None
Miscellaneous
NOP No operation 1 None
CLR [m] Clear Data Memory 1Note None
SET [m] Set Data Memory 1Note None
CLR WDT Clear Watchdog Timer 1 TO, PDF
SWAP [m] Swap nibbles of Data Memory 1Note None
SWAPA [m] Swap nibbles of Data Memory with result in ACC 1 None
HALT Enter power down mode 1 TO, PDF
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no
skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
Rev. 1.40 102 October 29, 2020

BC68F2123
Instruction Definition
ADC A,[m] Add Data Memory to ACC with Carry

Description The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
Operation ACC ← ACC + [m] + C
Affected flag(s) OV, Z, AC, C
ADCM A,[m] Add ACC to Data Memory with Carry

Description The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the specified Data Memory.
Operation [m] ← ACC + [m] + C
ADD A,[m] Add Data Memory to ACC

Description The contents of the specified Data Memory and the Accumulator are added.
Operation ACC ← ACC + [m]
ADD A,x Add immediate data to ACC

Description The contents of the Accumulator and the specified immediate data are added.
Operation ACC ← ACC + x
ADDM A,[m] Add ACC to Data Memory

Description The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the specified Data Memory.
Operation [m] ← ACC + [m]
AND A,[m] Logical AND Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation ACC ← ACC ″AND″ [m]
Affected flag(s) Z
AND A,x Logical AND immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bit wise logical AND
Operation ACC ← ACC ″AND″ x
Affected flag(s) Z
ANDM A,[m] Logical AND ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
Operation [m] ← ACC ″AND″ [m]
Affected flag(s) Z
Rev. 1.40 103 October 29, 2020

BC68F2123
CALL addr Subroutine call

Description Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation Stack ← Program Counter + 1
Program Counter ← addr
Affected flag(s) None
CLR [m] Clear Data Memory

Description Each bit of the specified Data Memory is cleared to 0.
Operation [m] ← 00H
CLR [m].i Clear bit of Data Memory

Description Bit i of the specified Data Memory is cleared to 0.
Operation [m].i ← 0
CLR WDT Clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared.
Operation WDT cleared
TO ← 0
PDF ← 0
Affected flag(s) TO, PDF
CPL [m] Complement Data Memory

Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
Operation [m] ← [m]
Affected flag(s) Z
CPLA [m] Complement Data Memory with result in ACC

Description Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC ← [m]
Affected flag(s) Z
DAA [m] Decimal-Adjust ACC for addition with result in Data Memory
Description Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
Operation [m] ← ACC + 00H or
[m] ← ACC + 06H or
[m] ← ACC + 60H or
[m] ← ACC + 66H
Affected flag(s) C
Rev. 1.40 104 October 29, 2020

BC68F2123
DEC [m] Decrement Data Memory

Description Data in the specified Data Memory is decremented by 1.
Operation [m] ← [m] − 1
Affected flag(s) Z
DECA [m] Decrement Data Memory with result in ACC

Description Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
Operation ACC ← [m] − 1
Affected flag(s) Z
HALT Enter power down mode

Description This instruction stops the program execution and turns off the system clock. The contents of
the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
Operation TO ← 0
PDF ← 1
Affected flag(s) TO, PDF
INC [m] Increment Data Memory

Description Data in the specified Data Memory is incremented by 1.
Operation [m] ← [m] + 1
Affected flag(s) Z
INCA [m] Increment Data Memory with result in ACC

Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
Operation ACC ← [m] + 1
Affected flag(s) Z
JMP addr Jump unconditionally

Description The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation Program Counter ← addr
MOV A,[m] Move Data Memory to ACC

Description The contents of the specified Data Memory are copied to the Accumulator.
MOV A,x Move immediate data to ACC

Description The immediate data specified is loaded into the Accumulator.
Operation ACC ← x
MOV [m],A Move ACC to Data Memory

Description The contents of the Accumulator are copied to the specified Data Memory.
Operation [m] ← ACC
Rev. 1.40 105 October 29, 2020

BC68F2123
NOP No operation
Description No operation is performed. Execution continues with the next instruction.
Operation No operation
OR A,[m] Logical OR Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
Operation ACC ← ACC ″OR″ [m]
Affected flag(s) Z
OR A,x Logical OR immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR
Operation ACC ← ACC ″OR″ x
Affected flag(s) Z
ORM A,[m] Logical OR ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR
Operation [m] ← ACC ″OR″ [m]
Affected flag(s) Z
RET Return from subroutine

Description The Program Counter is restored from the stack. Program execution continues at the restored
address.
Operation Program Counter ← Stack
RET A,x Return from subroutine and load immediate data to ACC
Description The Program Counter is restored from the stack and the Accumulator loaded with the specified
immediate data. Program execution continues at the restored address.
ACC ← x
RETI Return from interrupt

Description The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the
RETI instruction is executed, the pending Interrupt routine will be processed before returning
to the main program.
EMI ← 1
RL [m] Rotate Data Memory left

Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
Operation [m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
Rev. 1.40 106 October 29, 2020

BC68F2123
RLA [m] Rotate Data Memory left with result in ACC

Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
Operation ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
RLC [m] Rotate Data Memory left through Carry

Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation [m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
Affected flag(s) C
RLCA [m] Rotate Data Memory left through Carry with result in ACC
Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
Affected flag(s) C
RR [m] Rotate Data Memory right

Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
Operation [m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
RRA [m] Rotate Data Memory right with result in ACC

Description Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
Operation ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
RRC [m] Rotate Data Memory right through Carry

Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation [m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
Affected flag(s) C
Rev. 1.40 107 October 29, 2020

BC68F2123
RRCA [m] Rotate Data Memory right through Carry with result in ACC
Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces
the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
Affected flag(s) C
SBC A,[m] Subtract Data Memory from ACC with Carry

Description The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the
result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation ACC ← ACC − [m] − C
SBCM A,[m] Subtract Data Memory from ACC with Carry and result in Data Memory
Description The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the
result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation [m] ← ACC − [m] − C
SDZ [m] Skip if decrement Data Memory is 0

Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation [m] ← [m] − 1
Skip if [m]=0
SDZA [m] Skip if decrement Data Memory is zero with result in ACC
Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
Operation ACC ← [m] − 1
Skip if ACC=0
SET [m] Set Data Memory

Description Each bit of the specified Data Memory is set to 1.
Operation [m] ← FFH
SET [m].i Set bit of Data Memory

Description Bit i of the specified Data Memory is set to 1.
Operation [m].i ← 1
Rev. 1.40 108 October 29, 2020

BC68F2123
SIZ [m] Skip if increment Data Memory is 0

Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation [m] ← [m] + 1
Skip if [m]=0
SIZA [m] Skip if increment Data Memory is zero with result in ACC
Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation ACC ← [m] + 1
Skip if ACC=0
SNZ [m].i Skip if bit i of Data Memory is not 0

Description If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation Skip if [m].i ≠ 0
SUB A,[m] Subtract Data Memory from ACC

Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is
stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be
cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation ACC ← ACC − [m]
SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory
Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is
stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be
cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation [m] ← ACC − [m]
SUB A,x Subtract immediate data from ACC

Description The immediate data specified by the code is subtracted from the contents of the Accumulator.
The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C
flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation ACC ← ACC − x
SWAP [m] Swap nibbles of Data Memory

Description The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation [m].3~[m].0 ↔ [m].7~[m].4
Rev. 1.40 109 October 29, 2020

BC68F2123
SWAPA [m] Swap nibbles of Data Memory with result in ACC

Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
SZ [m] Skip if Data Memory is 0

Description If the contents of the specified Data Memory is 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation Skip if [m]=0
SZA [m] Skip if Data Memory is 0 with data movement to ACC

Description The contents of the specified Data Memory are copied to the Accumulator. If the value is zero,
the following instruction is skipped. As this requires the insertion of a dummy instruction
while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Skip if [m]=0
SZ [m].i Skip if bit i of Data Memory is 0

Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Operation Skip if [m].i=0
TABRD [m] Read table (specific page or current page) to TBLH and Data Memory
Description The low byte of the program code addressed by the table pointer (TBHP and TBLP or only
TBLP if no TBHP) is moved to the specified Data Memory and the high byte moved to
TBLH.
Operation [m] ← program code (low byte)
TBLH ← program code (high byte)
TABRDL [m] Read table (last page) to TBLH and Data Memory
Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved
to the specified Data Memory and the high byte moved to TBLH.
Operation [m] ← program code (low byte)
TBLH ← program code (high byte)
XOR A,[m] Logical XOR Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR
Operation ACC ← ACC ″XOR″ [m]
Affected flag(s) Z
Rev. 1.40 110 October 29, 2020

BC68F2123
XORM A,[m] Logical XOR ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR
Operation [m] ← ACC ″XOR″ [m]
Affected flag(s) Z
XOR A,x Logical XOR immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
Operation ACC ← ACC ″XOR″ x
Affected flag(s) Z
Rev. 1.40 111 October 29, 2020

BC68F2123
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the Package/Carton Information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.40 112 October 29, 2020

BC68F2123
16-pin NSOP (150mil) Outline Dimensions (Exposed Pad)

D1
1 8

E2

16 9
THERMAL VARIATIONS ONLY

Dimensions in inch
Symbol
Min. Nom. Max.
A — 0.236 BSC —
B — 0.154 BSC —
D1 0.059 — —
E2 0.039 — —
C 0.012 — 0.020
C’ — 0.390 BSC —
D — — 0.069
E — 0.050 BSC —
F 0.004 — 0.010
G 0.016 — 0.050
H 0.004 — 0.010
α 0° — 8°
Dimensions in mm
Symbol
Min. Nom. Max.
A — 6.00 BSC —
B — 3.90 BSC —
D1 1.50 — —
E2 1.00 — —
C 0.31 — 0.51
C’ — 9.90 BSC —
D — — 1.75
E — 1.27 BSC —
F 0.10 — 0.25
G 0.40 — 1.27
H 0.10 — 0.25
α 0° — 8°
Rev. 1.40 113 October 29, 2020

BC68F2123
Copyright© 2020 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.
Rev. 1.40 114 October 29, 2020

BC68F2123v140

Uploaded by

Document Informationclick to expand document information

Document Informationclick to expand document information

Copyright:

Available Formats

BC68F2123v140

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

BC68F2123v140

Uploaded by

Copyright:

Available Formats

Sub-1GHz OOK RF Transmitter Flash MCU

Revision: V1.40 Date: October 29, 2020

Absolute Maximum Ratings.................................................................................. 9

Flash Program Memory....................................................................................... 16

Special Function Register Description.............................................................. 22

Rev. 1.40 2 October 29, 2020

Program Counter Low Register – PCL.........................................................................................23

EEPROM Data Memory........................................................................................ 26

Operating Modes and System Clocks............................................................... 31

Reset and Initialisation........................................................................................ 41

Timer Modules – TM............................................................................................ 51

Rev. 1.40 3 October 29, 2020

Standard Type TM – STM.................................................................................... 54

Periodic Type TM – PTM...................................................................................... 69

Low Voltage Detector – LVD............................................................................... 90

Instruction Set Summary.................................................................................. 101

Instruction Definition......................................................................................... 103

Rev. 1.40 4 October 29, 2020

Rev. 1.40 5 October 29, 2020

• I2C interface for RF transmitter configuration

Device Connection Diagram

Rev. 1.40 6 October 29, 2020

Functional Block Diagram

Reset ROM RAM

: Pin-Shared Node EP : Exposed pad, must be connected to ground

Rev. 1.40 7 October 29, 2020

Pin Name Function OPT I/T O/T Description

Rev. 1.40 8 October 29, 2020

Interconnection Signal Description

Absolute Maximum Ratings

Rev. 1.40 9 October 29, 2020

Rev. 1.40 10 October 29, 2020

LVD/LVR Electrical Characteristics

Power-on Reset Characteristics

VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV

RRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms

Rev. 1.40 11 October 29, 2020

Rev. 1.40 12 October 29, 2020

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Rev. 1.40 13 October 29, 2020

Clocking and Pipelining

Program Counter PC PC+1 PC+2

System Clock and Pipelining

Rev. 1.40 14 October 29, 2020

1 MOV A, [12H] Fetch Inst. 1 Execute Inst. 1

Rev. 1.40 15 October 29, 2020

Arithmetic and Logic Unit – ALU

Flash Program Memory

Program Memory Structure

Rev. 1.40 16 October 29, 2020

Register TBLH User Selected

Table Program Example

Rev. 1.40 17 October 29, 2020

Table Read Program Example

In Circuit Programming – ICP

Rev. 1.40 18 October 29, 2020

Writer Connector MCU Programming

On-Chip Debug Support – OCDS