MC68HC908JL8

MC68HC908JL8
MC68HC908JK8
MC68HC908KL8
MC68HC08JL8
MC68HC08JK8
Data Sheet
M68HC08
Microcontrollers
MC68HC908JL8
Rev. 3.1
3/2005
freescale.com
MC68HC908JL8
MC68HC908JK8
MC68HC908KL8
MC68HC08JL8
MC68HC08JK8
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
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available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash technology licensed from SST.
Freescale Semiconductor, Inc., 2005. All rights reserved.
MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1
Freescale Semiconductor
Revision History
Date
Revision
Level
Mar 2005
3.1
Nov 2004
Nov 2002
Page
Number(s)
Description
Added IRQ timing to Table 17-5 . Control Timing (5V) and Table 17-8 .
Control Timing (3V)
188, 190
Chapter 9 Serial Communications Interface (SCI) Corrected SCI

module clock source from OSCCLK to Bus Clock throughout.
121206
Figure 13-2 . Keyboard Interrupt Block Diagram

Removed incorrect Schmitt trigger in block diagram.
168
14.7.2 Stop Mode STOP_ICLKDIS bit does not affect stop mode
conditions for COP. Replaced section with new text.
176
Added Appendix A MC68HC08JL8 ROM parts.
201
Added Appendix B MC68HC908KL8.
207
First general release.

4
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 3 Configuration and Mask Option Registers (CONFIG & MOR) . . . . . . . . . . . . . . 41
Chapter 4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Chapter 5 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Chapter 6 Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Chapter 7 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Chapter 8 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Chapter 9 Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Chapter 10 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Chapter 11 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Chapter 12 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Chapter 13 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Chapter 14 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Chapter 15 Low Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Chapter 16 Break Module (BREAK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Chapter 17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Chapter 18 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Chapter 19 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Appendix A MC68HC08JL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Appendix B MC68HC908KL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

List of Chapters

6
Table of Contents
Chapter 1
General Description
1.1
1.2
1.3
1.4
1.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
18
20
21
Chapter 2
Memory
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Page Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
33
33
33
34
34
35
35
38
38
Chapter 3
Configuration and Mask Option Registers (CONFIG & MOR)
3.1
3.2
3.3
3.4
3.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Register 1 (CONFIG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Register 2 (CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mask Option Register (MOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
41
42
43
43
Chapter 4
Central Processor Unit (CPU)
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
45
46
46
46
47

Table of Contents
4.3.4
4.3.5
4.4
4.5
4.5.1
4.5.2
4.6
4.7
4.8
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
48
49
49
49
49
50
50
50
Chapter 5
System Integration Module (SIM)
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2
Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2.2
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2.3
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2.5
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2
SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.3
SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5
Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.1.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.1.2
SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2.1
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2.2
5.5.2.3
5.5.3
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.4
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.5
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1
Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.2
Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.3
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
63
63
63
63
64
64
64
65
66
66
66
66
67
67
67
67
67
67
69
70
70
71
72
72
72
72
73
73
73
74
75
75
76
77

8
Chapter 6
Oscillator (OSC)
6.1
6.2
6.2.1
6.2.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.5
6.5.1
6.5.2
6.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6) . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XTAL Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Oscillator Clock (ICLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
79
80
81
81
82
82
82
82
82
82
82
83
83
83
83
83
83
Chapter 7
Monitor ROM (MON)
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.4
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
ROM-Resident Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
PRGRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
MON_ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
MON_LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EE_WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EE_READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table of Contents
Chapter 8
Timer Interface Module (TIM)
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.1
TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.2
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.3
Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.3.1
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.3.2
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.4
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.4.1
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.4.2
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.4.3
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.7
TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.8
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.8.1
TIM Clock Pin (ADC12/T2CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.8.2
TIM Channel I/O Pins (PTD4/T1CH0, PTD5/T1CH1, PTE0/T2CH0, PTE1/T2CH1) . . . . .
8.9
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.9.1
TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.9.2
TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.9.3
TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.9.4
TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.9.5
TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
105
105
106
108
108
108
109
109
109
110
111
111
112
112
112
112
113
113
113
113
114
114
115
116
117
119
Chapter 9
Serial Communications Interface (SCI)
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3
Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4
9.4.1
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2.1
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2.2
Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2.3
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2.4
Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2.5
Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.2.6
Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.3.1
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
121
121
121
123
123
124
124
125
125
125
126
126
126
126

10
9.4.3.2
Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.3.3
Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.3.4
Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.3.5
Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.3.6
Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.3.7
Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.3.8
Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6
SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.7
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.7.1
TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.7.2
RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.8
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.8.1
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.8.2
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.8.3
SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.8.4
SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.8.5
SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.8.6
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.8.7
SCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
126
128
129
130
131
132
132
133
133
133
133
133
133
133
134
134
136
138
139
142
142
143
Chapter 10
Analog-to-Digital Converter (ADC)
10.1
10.2
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.4
10.5
10.5.1
10.5.2
10.6
10.6.1
10.7
10.7.1
10.7.2
10.7.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
145
145
145
146
147
147
147
147
147
147
147
148
148
148
148
148
150
150

11
Table of Contents
Chapter 11
Input/Output (I/O) Ports
11.1
11.2
11.2.1
11.2.2
11.2.3
11.3
11.3.1
11.3.2
11.4
11.4.1
11.4.2
11.4.3
11.5
11.5.1
11.5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A Input Pull-Up Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
151
153
153
153
155
156
156
156
157
158
158
160
160
160
161
Chapter 12
External Interrupt (IRQ)
12.1
12.2
12.3
12.3.1
12.4
12.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Status and Control Register (INTSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
163
163
163
164
165
166
Chapter 13
Keyboard Interrupt Module (KBI)
13.1
13.2
13.3
13.4
13.4.1
13.5
13.5.1
13.5.2
13.6
13.6.1
13.6.2
13.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
167
167
167
168
169
169
169
170
171
171
171
171
Chapter 14
Computer Operating Properly (COP)
14.1
14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12
14.3
14.3.1
14.3.2
14.3.3
14.3.4
14.3.5
14.3.6
14.3.7
14.4
14.5
14.6
14.7
14.7.1
14.7.2
14.8
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
174
174
174
174
174
174
174
175
175
175
175
175
176
176
176
Chapter 15
Low Voltage Inhibit (LVI)
15.1
15.2
15.3
15.4
15.5
15.5.1
15.5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
177
177
177
178
178
178
178
Chapter 16
Break Module (BREAK)
16.1
16.2
16.3
16.3.1
16.3.2
16.3.3
16.3.4
16.4
16.4.1
16.4.2
16.4.3
16.4.4
16.5
16.5.1
16.5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flag Protection During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Break Status and Control Register (BRKSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
179
179
179
180
180
180
180
181
181
181
182
183
183
183
183

13
Table of Contents
Chapter 17
Electrical Specifications
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
17.10
17.11
17.12
17.13
17.14
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
185
185
186
186
187
188
188
189
190
191
192
193
193
194
Chapter 18
Mechanical Specifications
18.1
18.2
18.3
18.4
18.5
18.6
18.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-Pin Plastic Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-Pin Small Outline Integrated Circuit Package (SOIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-Pin Plastic Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-Pin Small Outline Integrated Circuit Package (SOIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-Pin Shrink Dual In-Line Package (SDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
195
195
196
196
197
197
198
Chapter 19
Ordering Information
19.1
19.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Appendix A
MC68HC08JL8
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.7.1
A.8
A.9
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68HC08JL8 Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
201
201
201
202
204
204
204
204
205
206

14
Appendix B
MC68HC908KL8
B.1
B.2
B.3
B.4
B.5
B.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68HC908KL8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
207
207
207
210
210
210

15
Table of Contents

16
Chapter 1
General Description
1.1 Introduction
The MC68HC908JL8 is a member of the low-cost, high-performance M68HC08 Family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit
(CPU08) and are available with a variety of modules, memory sizes and types, and package types.
Table 1-1. Summary of Devices
Generic Part
Description
Pin Count
MC68HC908JL8
FLASH part
28 or 32
MC68HC908JK8
FLASH part
20
MC68HC08JL8
ROM part for MC68HC908JL8
28 or 32
MC68HC08JK8
ROM part for MC68HC908JK8
20
MC68HC908KL8
ADC-less MC68HC908JL8
28 or 32
1.2 Features
Features of the MC68HC908JL8 include the following:
High-performance M68HC08 architecture
Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
Low-power design; fully static with stop and wait modes
Maximum internal bus frequency:
8-MHz at 5V operating voltage
4-MHz at 3V operating voltage
Oscillator options:
Crystal or resonator
RC oscillator
8,192 bytes user program FLASH memory with security(1) feature
256 bytes of on-chip RAM
Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture,
output compare, and PWM capability on each channel; external clock input option on TIM2
13-channel, 8-bit analog-to-digital converter (ADC)
Serial communications interface module (SCI)
26 general-purpose input/output (I/O) ports:
8 keyboard interrupt with internal pull-up
1. No security feature is absolutely secure. However, Motorolas strategy is to make reading or copying the FLASH difficult for
unauthorized users.
17
General Description
11 LED drivers (sink)

2 25mA open-drain I/O with pull-up
Resident routines for in-circuit programming and EEPROM emulation
System protection features:
Optional computer operating properly (COP) reset, driven by internal RC oscillator
Optional low-voltage detection with reset and selectable trip points for 3V and 5V operation
Illegal opcode detection with reset
Illegal address detection with reset
Master reset pin with internal pull-up and power-on reset
IRQ with schmitt-trigger input and programmable pull-up
20-pin dual in-line package (PDIP), 20-pin small outline integrated package (SOIC), 28-pin PDIP,
28-pin SOIC, 32-pin shrink dual in-line package (SDIP), and 32-pin low-profile quad flat pack
(LQFP)
Specific features of the MC68HC908JL8 in 28-pin packages are:
23 general-purpose I/Os only
12-channel ADC
Timer I/O pins on TIM1 only
Specific features of the MC68HC908JL8 in 20-pin packages are:
15 general-purpose I/Os only
10-channel ADC
Timer I/O pins on TIM1 only
Features of the CPU08 include the following:

Enhanced HC05 programming model
Extensive loop control functions
16 addressing modes (eight more than the HC05)
16-bit index register and stack pointer
Memory-to-memory data transfers
Fast 8 8 multiply instruction
Fast 16/8 divide instruction
Binary-coded decimal (BCD) instructions
Optimization for controller applications
Efficient C language support
1.3 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC908JL8.

18
MCU Block Diagram

INTERNAL BUS
CONTROL AND STATUS REGISTERS 64 BYTES
USER FLASH 8,192 BYTES
PORTA
ARITHMETIC/LOGIC
UNIT (ALU)
PTA7/KBI7**
PTA6/KBI6**
PTA5/KBI5**
PTA4/KBI4**
PTA3/KBI3**
PTA2/KBI2**
PTA1/KBI1**
PTA0/KBI0**
PTB7/ADC7
PTB6/ADC6
PTB5/ADC5
PTB4/ADC4
PTB3/ADC3
PTB2/ADC2
PTB1/ADC1
PTB0/ADC0
KEYBOARD INTERRUPT
MODULE
8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
DDRA
CPU
REGISTERS
PORTB
M68HC08 CPU
2-CHANNEL TIMER INTERFACE

MODULE 1

MODULE 2
MONITOR ROM 959 BYTES
USER FLASH VECTORS 36 BYTES
POWER-ON RESET
MODULE
* RST
SYSTEM INTEGRATION
MODULE
LOW-VOLTAGE INHIBIT
MODULE
* IRQ
EXTERNAL INTERRUPT
MODULE
VDD
POWER
VSS
ADC REFERENCE
COMPUTER OPERATING
PROPERLY MODULE
PORTD
RC OSCILLATOR
INTERNAL OSCILLATOR
##
PTD7/RxD**
PTE
OSC2/RCCLK
ADC12/T2CLK
SERIAL COMMUNICATIONS
INTERFACE MODULE
DDRD
CRYSTAL OSCILLATOR
BREAK
MODULE
DDRE
OSC1
DDRB
USER RAM 256 BYTES
PTD6/TxD**
PTD5/T1CH1
PTD4/T1CH0
PTD3/ADC8
PTD2/ADC9
PTD1/ADC10
PTD0/ADC11
##
PTE1/T2CH1
#
PTE0/T2CH0
* Pin contains integrated pull-up device.

** Pin contains programmable pull-up device.
25mA open-drain if output pin.
LED direct sink pin.
Shared pin: OSC2/RCCLK/PTA6/KBI6.
# Pins available on 32-pin packages only.
## Pins available on 28-pin and 32-pin packages only.
Figure 1-1. MC68HC908JL8 Block Diagram

19
General Description
IRQ
ADC12/T2CLK
PTA7/KBI7
RST
PTA5/KBI5
30
29
28
27
26
25 PTD4/T1CH0
PTA0/KBI0
OSC1 1
31
32 VSS
1.4 Pin Assignments
24 PTD5/T1CH1
PTA2/KBI2
20
PTB0/ADC0
PTA3/KBI3
19
PTB1/ADC1
PTB7/ADC7
18
PTD1/ADC10
17 PTB2/ADC2
PTB3/ADC3 16
PTB5/ADC5 9
PTB6/ADC6 8
15
PTD3/ADC8
PTD0/ADC11
21
14
PTB4/ADC4
VDD
13
PTA4/KBI4
PTE1/T2CH1
22
12
PTE0/T2CH0
PTA1/KBI1
11
PTD2/ADC9
PTD6/TxD
23
10
PTD7/RxD
OSC2/RCCLK/PTA6/KBI6
Figure 1-2. 32-Pin LQFP Pin Assignment
IRQ
32
ADC12/T2CLK
PTA0/KBI0
31
PTA7/KBI7
VSS
30
RST
OSC1
29
PTA5/KBI5
28
PTD4/T1CH0
PTA1/KBI1
27
PTD5/T1CH1
VDD
26
PTD2/ADC9
PTA2/KBI2
25
PTA4/KBI4
PTA3/KBI3
24
PTD3/ADC8
PTB7/ADC7
10
23
PTB0/ADC0
PTB6/ADC6
11
22
PTB1/ADC1
PTB5/ADC5
12
21
PTD1/ADC10
PTD7/RxD
13
20
PTB2/ADC2
PTD6/TxD
14
19
PTB3/ADC3
PTE0/T2CH0
15
18
PTD0/ADC11
PTE1/T2CH1
16
17
PTB4/ADC4
Figure 1-3. 32-Pin SDIP Pin Assignment

20
Pin Functions
IRQ
28
RST
PTA0/KBI0
27
PTA5/KBI5
VSS
26
PTD4/T1CH0
OSC1
25
PTD5/T1CH1
24
PTD2/ADC9
PTA1/KBI1
23
PTA4/KBI4
VDD
22
PTD3/ADC8
PTA2/KBI2
21
PTB0/ADC0
PTA3/KBI3
20
PTB1/ADC1
PTB7/ADC7
10
19
PTD1/ADC10
PTB6/ADC6
11
18
PTB2/ADC2
PTB5/ADC5
12
17
PTB3/ADC3
PTD7/RxD
13
16
PTD0/ADC11
PTD6/TxD
14
15
PTB4/ADC4
Pins not available on 28-pin packages

PTE0/T2CH0
PTE1/T2CH1
ADC12/T2CLK
PTA7/KBI7
Internal pads are unconnected.
Set these unused port I/Os to output low.
Figure 1-4. 28-Pin PDIP/SOIC Pin Assignment
IRQ
20
RST
VSS
19
PTD4/T1CH0
OSC1
18
PTD5/T1CH1
17
PTD2/ADC9
VDD
16
PTD3/ADC8
PTB7/ADC7
15
PTB0/ADC0
PTA3/KBI3
PTE0/T2CH0
PTB6/ADC6
14
PTB1/ADC1
PTA4/KBI4
PTE1/T2CH1
PTB5/ADC5
13
PTB2/ADC2
PTA5/KBI5
PTD7/RxD
12
PTB3/ADC3
PTD6/TxD
10
11
PTB4/ADC4

PTA0/KBI0
PTD0/ADC11
PTA1/KBI1
PTD1/ADC10
PTA2/KBI2
ADC12/T2CLK
PTA7/KBI7
The 20-pin MC68HC908JL8 is designated MC68HC908JK8.
Figure 1-5. 20-Pin PDIP/SOIC Pin Assignment
1.5 Pin Functions

Description of the pin functions are provided in Table 1-2.

21
General Description
Table 1-2. Pin Functions

IN/OUT
VOLTAGE
LEVEL
In
5V or 3V
Out
0V
In/Out
VDD
External IRQ pin; with programmable internal pull-up and schmitt

trigger input.
In
VDD
Used for monitor mode entry.
In
VDD to VTST
Crystal or RC oscillator input.
In
VDD
OSC2: crystal oscillator output; inverted OSC1 signal.
Out
VDD
RCCLK: RC oscillator clock output.
Out
VDD
In/Out
VDD
ADC12: channel-12 input of ADC.
In
VSS to VDD
T2CLK: external input clock for TIM2.
In
VDD
In/Out
VDD
Each pin has programmable internal pull-up when configured as

input.
In
VDD
Pins as keyboard interrupts, KBI0KBI7.
In
VDD
PTA0PTA5 and PTA7 have LED direct sink capability.
Out
VSS
PTA6 as OSC2/RCCLK.
Out
VDD
In/Out
VDD
In
VSS to VDD
8-bit general purpose I/O port;

with programmable internal pull-ups on PTD6PTD7.
In/Out
VDD
PTD0PTD3 as ADC input channels, ADC11ADC8.
Input
VSS to VDD
Out
VSS
PTD4 as T1CH0 of TIM1.
In/Out
VDD
PTD5 as T1CH1 of TIM1.
In/Out
VDD
PTD6PTD7 have configurable 25mA open-drain output.
Out
VSS
PTD6 as TxD of SCI.
Out
VDD
PTD7 as RxD of SCI.
In
VDD
PIN NAME
PIN DESCRIPTION
VDD
Power supply.
VSS
Power supply ground.
RST
Reset input, active low;

with internal pull-up and schmitt trigger input.
IRQ
OSC1
OSC2/RCCLK
Pin as PTA6/KBI6 (see PTA0PTA7).

ADC12/T2CLK
8-bit general purpose I/O port.
PTA0PTA7

PTB0PTB7
Pins as ADC input channels, ADC0ADC7.
PTD2PTD3 and PTD6PTD7 have LED direct sink capability

PTD0PTD7

22
Pin Functions
Table 1-2. Pin Functions (Continued)

IN/OUT
VOLTAGE
LEVEL
In/Out
VDD
PTE0 as T2CH0 of TIM2.
In/Out
VDD
PTE1 as T2CH1 of TIM2.
In/Out
VDD
PIN NAME
PTE0PTE1
PIN DESCRIPTION
NOTE
Devices in 28-pin packages, the following pins are not available:
PTA7/KBI7, PTE0/T2CH0, PTE1/T2CH1, and ADC12/T2CLK.
Devices in 20-pin packages, the following pins are not available:
PTA0/KBI0PTA5/KBI5, PTD0/ADC11, PTD1/ADC10,
PTA7/KBI7, PTE0/T2CH0, PTE1/T2CH1, and ADC12/T2CLK.

23
General Description

24
Chapter 2
Memory
2.1 Introduction
The CPU08 can address 64-kbytes of memory space. The memory map, shown in Figure 2-1, includes:
8,192 bytes of user FLASH memory
36 bytes of user-defined vectors
959 bytes of monitor ROM
2.2 I/O Section

Addresses $0000$003F, shown in Figure 2-2, contain most of the control, status, and data registers.
Additional I/O registers have the following addresses:
$FE00; Break Status Register, BSR
$FE01; Reset Status Register, RSR
$FE02; Reserved
$FE03; Break Flag Control Register, BFCR
$FE04; Interrupt Status Register 1, INT1
$FE07; Reserved
$FE08; FLASH Control Register, FLCR
$FE09; Reserved
$FE0A; Reserved
$FE0B; Reserved
$FE0C; Break Address Register High, BRKH
$FE0D; Break Address Register Low, BRKL
$FE0E; Break Status and Control Register, BRKSCR
$FE0F; Reserved
$FFCF; FLASH Block Protect Register, FLBPR (FLASH register)
$FFD0; Mask Option Register, MOR (FLASH register)
$FFFF; COP Control Register, COPCTL
2.3 Monitor ROM

The 959 bytes at addresses $FC00$FDFF and $FE10$FFCE are reserved ROM addresses that
contain the instructions for the monitor functions. (See Chapter 7 Monitor ROM (MON).)

25
Memory
$0000
$003F
I/O REGISTERS
64 BYTES
$0040
$005F
RESERVED
32 BYTES
$0060
$015F
RAM
256 BYTES
$0160
$DBFF
UNIMPLEMENTED
55,968 BYTES
$DC00
$FBFF
FLASH MEMORY
8,192 BYTES
$FC00
$FDFF
MONITOR ROM
512 BYTES
$FE00
BREAK STATUS REGISTER (BSR)
$FE01
RESET STATUS REGISTER (RSR)
$FE02
RESERVED
$FE03
BREAK FLAG CONTROL REGISTER (BFCR)
$FE04
INTERRUPT STATUS REGISTER 1 (INT1)
$FE05
$FE06
$FE07
RESERVED
$FE08
FLASH CONTROL REGISTER (FLCR)
$FE09
$FF0B
RESERVED
$FE0C
BREAK ADDRESS HIGH REGISTER (BRKH)
$FE0D
BREAK ADDRESS LOW REGISTER (BRKL)
$FE0E
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0F
RESERVED
$FE10
$FFCE
MONITOR ROM
447 BYTES
$FFCF
FLASH BLOCK PROTECT REGISTER (FLBPR)
$FFD0
MASK OPTION REGISTER (MOR)
$FFD1
$FFDB
RESERVED
11 BYTES
$FFDC
$FFFF
USER FLASH VECTORS

36 BYTES
Figure 2-1. Memory Map

26
Monitor ROM
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0012
Register Name
Read:
Port A Data Register (PTA) Write:
Reset:
Read:
Port B Data Register (PTB) Write:
Reset:
Read:
Unimplemented Write:
Read:
Port D Data Register (PTD) Write:
Reset:
Read:
Data Direction Register A
Write:
(DDRA)
Reset:
Read:
Data Direction Register B
Write:
(DDRB)
Reset:
Read:
Read:
Data Direction Register D
Write:
(DDRD)
Reset:
Read:
Port E Data Register
Write:
(PTE)
Reset:
Read:
Read:
Port D Control Register
Write:
(PDCR)
Reset:
Bit 7
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTD2
PTD1
PTD0
Unaffected by reset
PTB7
PTB6
PTB5
PTB4
PTB3
Unaffected by reset
PTD7
PTD6
PTD5
PTD4
PTD3
Unaffected by reset
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
PTE1
PTE0
Unaffected by reset
SLOWD7 SLOWD6 PTDPU7

0
PTDPU6
DDRE1
DDRE0
Read:
Read:
Data Direction Register E
Write:
(DDRE)
Reset:
Port A Input Pull-up Read:

PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Enable Register Write:
(PTAPUE) Reset:
0
0
0
0
0
0
0
0
PTA7 Input Pull-up Read:
PTAPUE7
(PTA7PUE) Reset:
0
0
0
0
0
0
0
0
Read:
U = Unaffected
X = Indeterminate
= Unimplemented
= Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)

27
Memory
Addr.
$0013
$0014
$0015
Register Name
SCI Control Register 1
(SCC1)
(SCC2)
(SCC3)
$0016 SCI Status Register 1 (SCS1)
$0018
SCI Data Register

(SCDR)
$0019
SCI Baud Rate Register

(SCBR)
$001A
$001B
$001C
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Keyboard Status and Read:

Control Register Write:
(KBSCR) Reset:
Keyboard Interrupt Read:
(KBIER) Reset:
Bit 7
Bit 0
LOOPS
ENSCI
TXINV
WAKE
ILTY
PEN
PTY
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
R8
T8
DMARE
DMATE
ORIE
NEIE
FEIE
PEIE
U
SCTE
U
TC
0
SCRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
BKF
0
RPF
0
R7
T7
0
R6
T6
0
R5
T5
0
R2
T2
0
R1
T1
0
R0
T0
0
0
R4
R3
T4
T3
Unaffected by reset
SCP1
SCP0
SCR2
SCR1
SCR0
KEYF
0
ACKK
IMASKK
MODEK
KBIE7
KBIE6
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
IMASK
MODE
Read:
0
0
0
0
IRQF
IRQ Status and Control Read:
Register Write:
(INTSCR) Reset:
0
0
0
0
0
Read:
IRQPUD
R
R
LVIT1
LVIT0
Configuration Register 2
$001E
Write:
(CONFIG2)
Reset:
0
0
0
0*
0*
Read:
COPRS
R
R
LVID
R
Configuration Register 1
Write:
$001F
(CONFIG1)
Reset:
0
0
0
0
0
One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only.
$001D
$0020
$0021
TIM1 Status and Control Read:

Register Write:
(T1SC) Reset:
TIM1 Counter Register Read:
High Write:
(T1CNTH) Reset:
U = Unaffected
TOF
0
TOIE
TSTOP
0
TRST
0
ACK
0
R
0
STOP_
ICLKDIS
0
SSREC
STOP
COPD
PS2
PS1
PS0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
R
0
= Reserved
0
0
X = Indeterminate
0
0
= Unimplemented

28
Monitor ROM
Addr.
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002F
$0030
$0031
$0032
$0033
$0034
Register Name

Low Write:
(T1CNTL) Reset:
TIM Counter Modulo Read:
Register High Write:
(TMODH) Reset:
TIM1 Counter Modulo Read:
Register Low Write:
(T1MODL) Reset:
TIM1 Channel 0 Status Read:
and Control Register Write:
(T1SC0) Reset:
TIM1 Channel 0 Read:
(T1CH0H) Reset:
Register Low Write:
(T1CH0L) Reset:
(T1SC1) Reset:
(T1CH1H) Reset:
Register Low Write:
(T1CH1L) Reset:
Bit 7
Bit 0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
CH0F
0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit2
Bit1
Bit0
Indeterminate after reset
Bit7
Bit6
Bit5
Bit4
Bit3
CH1F
0
CH1IE
Bit15
Bit14
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit2
Bit1
Bit0
PS2
PS1
PS0
Bit7
Bit6
Bit5
Bit4
Bit3
Read:
TIM2 Status and Control Read:

Register Write:
(T2SC) Reset:
High Write:
(T2CNTH) Reset:
Low Write:
(T2CNTL) Reset:
(T2MODH) Reset:
Register Low Write:
(T2MODL) Reset:
U = Unaffected
TOF
0
TOIE
TSTOP
0
TRST
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
R
1
= Reserved
1
1
X = Indeterminate
1
1
= Unimplemented

29
Memory
Addr.
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
$003E
$003F
Register Name

(T2SC0) Reset:
(T2CH0H) Reset:
Register Low Write:
(T2CH0L) Reset:
(T2SC1) Reset:
(T2CH1H) Reset:
Register Low Write:
(T2CH1L) Reset:
Bit 0
CH0F
0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Bit3
CH1F
0
CH1IE
Bit15
Bit14
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Bit3
Read:
ADC Status and Control Read:
Register Write:
(ADSCR) Reset:
Read:
ADC Data Register
Write:
(ADR)
Reset:
Read:
ADC Input Clock Register
Write:
(ADICLK)
Reset:
Read:
Read:
$FE00 Break Status Register (BSR) Write:
Reset:
Note: Writing a logic 0 clears SBSW.
Read:
$FE01 Reset Status Register (RSR) Write:
POR:
Read:
$FE02
Reserved Write:
$FE03
Bit 7
Break Flag Control Read:

Register Write:
(BFCR) Reset:
U = Unaffected
COCO
0
AD7
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
AD6
0
AD5
1
AD4
1
AD3
1
AD2
1
AD1
1
AD0

0
0
ADIV2
ADIV1
ADIV0
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
BCFE
= Reserved
0
X = Indeterminate
= Unimplemented
SBSW
See note
0

30
Monitor ROM
Addr.
Register Name
$FE04
Interrupt Status Register 1

(INT1)
$FE05

(INT2)
$FE06

(INT3)
$FE07
Reserved
$FE08
$FE09
$FE0B
$FE0C
$FE0D
$FE0E
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Read:
FLASH Control Register
Write:
(FLCR)
Reset:
Read:
Reserved Write:
Break Address High Read:
Register Write:
(BRKH) Reset:
Break Address low Read:
Register Write:
(BRKL) Reset:
Break Status and Control Read:
Register Write:
(BRKSCR) Reset:
Bit 7
IF6
R
0
IF14
R
0
0
R
0
6
IF5
R
0
IF13
R
0
0
R
0
5
IF4
R
0
IF12
R
0
0
R
0
4
IF3
R
0
IF11
R
0
0
R
0
3
0
R
0
0
R
0
0
R
0
2
IF1
R
0
0
R
0
0
R
0
1
0
R
0
IF8
R
0
0
R
0
Bit 0
0
R
0
IF7
R
0
IF15
R
0
HVEN
MASS
ERASE
PGM
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
FLASH Block Protect Read:

BPR7
Register Write:
#
(FLBPR) Reset:
Read:
OSCSEL
Mask Option Register
$FFD0
Write:
(MOR)#
Reset:
# Non-volatile FLASH registers; write by programming.
$FFCF
$FFFF
Read:
COP Control Register
Write:
(COPCTL)
Reset:
U = Unaffected
Unaffected by reset; $FF when blank

R
X = Indeterminate
Low byte of reset vector

Writing clears COP counter (any value)
Unaffected by reset
= Unimplemented
R
= Reserved

31
Memory
.
Table 2-1. Vector Addresses

Vector Priority
INT Flag
Address
$FFD0
$FFDD
Not Used
$FFDE
ADC Conversion Complete Vector (High)
$FFDF
ADC Conversion Complete Vector (Low)
$FFE0
Keyboard Interrupt Vector (High)
$FFE1
Keyboard Interrupt Vector (Low)
$FFE2
SCI Transmit Vector (High)
$FFE3
SCI Transmit Vector (Low)
$FFE4
SCI Receive Vector (High)
$FFE5
SCI Receive Vector (Low)
$FFE6
SCI Error Vector (High)
$FFE7
SCI Error Vector (Low)
Lowest
IF15
IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
IF6
IF5
IF4
IF3
IF2
IF1
Vector
Not Used
$FFEC
TIM2 Overflow Vector (High)
$FFED
TIM2 Overflow Vector (Low)
$FFEE
TIM2 Channel 1 Vector (High)
$FFEF
TIM2 Channel 1 Vector (Low)
$FFF0
$FFF1
$FFF2
TIM1 Overflow Vector (High)
$FFF3
TIM1 Overflow Vector (Low)
$FFF4
$FFF5
$FFF6
$FFF7
Not Used
$FFFA
IRQ Vector (High)
$FFFB
IRQ Vector (Low)
$FFFC
SWI Vector (High)
$FFFD
SWI Vector (Low)
$FFFE
Reset Vector (High)
$FFFF
Reset Vector (Low)
Highest

32
Random-Access Memory (RAM)
2.4 Random-Access Memory (RAM)

Addresses $0060 through $015F are RAM locations. The location of the stack RAM is programmable.
The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero are 160 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero
RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global
variables.
Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU
registers.
NOTE
For M6805 compatibility, the H register is not stacked.
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in
the RAM during a subroutine or during the interrupt stacking operation.
2.5 FLASH Memory

This sub-section describes the operation of the embedded FLASH memory. The FLASH memory can be
read, programmed, and erased from a single external supply. The program and erase operations are
enabled through the use of an internal charge pump.
2.6 Functional Description

The FLASH memory consists of an array of 8,192 bytes for user memory plus a block of 36 bytes for user
interrupt vectors. An erased bit reads as logic 1 and a programmed bit reads as a logic 0. The FLASH
memory page size is defined as 64 bytes, and is the minimum size that can be erased in a page erase
operation. Program and erase operations are facilitated through control bits in FLASH control register
(FLCR).
The address ranges for the FLASH memory are:
$DC00$FBFF; user memory; 12,288 bytes
$FFDC$FFFF; user interrupt vectors; 36 bytes
Programming tools are available from Freescale. Contact your local Freescale representative for more
information.
NOTE
A security feature prevents viewing of the FLASH contents.(1)
unauthorized users.
33
Memory
2.7 FLASH Control Register

The FLASH control register (FCLR) controls FLASH program and erase operations.
Address:
Read:
$FE08
Bit 7
Write:
Reset:
Bit 0
HVEN
MASS
ERASE
PGM
Figure 2-3. FLASH Control Register (FLCR)

HVEN High Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for program and erase operations
in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for
program or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation or page erase operation when the
ERASE bit is set.
1 = Mass erase operation selected
0 = Page erase operation selected
ERASE Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation not selected
PGM Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE
bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation not selected
2.8 FLASH Page Erase Operation

Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes
starting from addresses $XX00, $XX40, $XX80 or $XXC0. The 36-byte user interrupt vectors area also
forms a page. Any page within the 8,192 bytes user memory area ($DC00$FBFF) can be erased alone.
The 36-byte user interrupt vectors cannot be erased by the page erase operation because of security
reasons. Mass erase is required to erase this page.
1. Set the ERASE bit and clear the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address within the page address range desired.
4. Wait for a time, tnvs (10s).
5. Set the HVEN bit.
6. Wait for a time terase (4ms).
34
FLASH Mass Erase Operation
7.
8.
9.
10.
Clear the ERASE bit.

Wait for a time, tnvh (5s).
Clear the HVEN bit.
After time, trcv (1s), the memory can be accessed in read mode again.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
2.9 FLASH Mass Erase Operation

Use the following procedure to erase the entire FLASH memory:
1. Set both the ERASE bit and the MASS bit in the FLASH control register.
3. Write any data to any FLASH location within the FLASH memory address range.
6. Wait for a time tmerase (4ms).
7. Clear the ERASE bit.
8. Wait for a time, tnvh1 (100s).
9. Clear the HVEN bit.
10. After time, trcv (1s), the memory can be accessed in read mode again.
NOTE
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
2.10 FLASH Program Operation

Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes
starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this
step-by-step procedure to program a row of FLASH memory:
(Figure 2-4 shows a flowchart of the programming algorithm.)
1. Set the PGM bit. This configures the memory for program operation and enables the latching of
address and data for programming.
3. Write any data to any FLASH location within the address range of the row to be programmed.
6. Wait for a time, tpgs (5s).
7. Write data to the FLASH address to be programmed.

35
Memory
8. Wait for time, tprog (30s).

9. Repeat steps 7 and 8 until all bytes within the row are programmed.
10. Clear the PGM bit.
11. Wait for time, tnvh (5s).
12. Clear the HVEN bit.
13. After time, trcv (1s), the memory can be accessed in read mode again.
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
The time between each FLASH address change (step 7 to step 7), or the
time between the last FLASH addressed programmed to clearing the PGM
bit (step 7 to step 10), must not exceed the maximum programming time,
tprog max.
NOTE
must be performed in the order shown, other unrelated operations may
occur between the steps.

36
FLASH Program Operation

1
Algorithm for programming

a row (32 bytes) of FLASH memory
Set PGM bit
Read the FLASH block protect register
Write any data to any FLASH location

within the address range of the row to
be programmed
Wait for a time, tnvs
Set HVEN bit
Wait for a time, tpgs
Write data to the FLASH address

to be programmed
Wait for a time, tprog
Completed
programming
this row?
NOTE:
The time between each FLASH address change (step 7 to step 7), or
the time between the last FLASH address programmed
to clearing PGM bit (step 7 to step 10)
must not exceed the maximum programming
time, tprog max.
10
Clear PGM bit
11
Wait for a time, tnvh
12
Clear HVEN bit
13
Wait for a time, trcv
This row program algorithm assumes the row/s

to be programmed are initially erased.
End of programming
Figure 2-4. FLASH Programming Flowchart

37
Memory
2.11 FLASH Block Protection

Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made to protect blocks of memory from unintentional erase or program operations
due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR).
The FLBPR determines the range of the FLASH memory which is to be protected. The range of the
protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory
($FFFF). When the memory is protected, the HVEN bit cannot be set in either erase or program
operations.
NOTE
In performing a program or erase operation, the FLASH block protect register must be read after setting
the PGM or ERASE bit and before asserting the HVEN bit
When the FLBPR is program with all 0s, the entire memory is protected from being programmed and
erased. When all the bits are erased
(all 1s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory, address ranges as shown in
2.12 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF, any
erase or program of the FLBPR or the protected block of FLASH memory is prohibited. The FLBPR itself
can be erased or programmed only with an external voltage, VTST, present on the IRQ pin. This voltage
also allows entry from reset into the monitor mode.
2.12 FLASH Block Protect Register

The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and
therefore can only be written during a programming sequence of the FLASH memory. The value in this
register determines the starting location of the protected range within the FLASH memory.
Address:
Read:
Write:
Reset:
$FFCF
Bit 7
Bit 0
BPR7
BPR6
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
Non-volatile FLASH register; write by programming.
Figure 2-5. FLASH Block Protect Register (FLBPR)

BPR[7:0] FLASH Block Protect Bits
BPR[7:0] represent bits [13:6] of a 16-bit memory address. Bits [15:14] are logic 1s and bits [5:0] are
logic 0s.
16-bit memory address
Start address of FLASH block protect
1 1
0 0 0 0 0 0
BPR[7:0]

38
FLASH Block Protect Register
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block
protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF.
With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 (at page
boundaries 64 bytes) within the FLASH memory.
Examples of protect start address:
BPR[7:0]
Start of Address of Protect Range (1)
$00$70
The entire FLASH memory is protected.
$71
(0111 0001)
$DC40 (1101 1100 0100 0000)
$72
(0111 0010)
$DC80 (1101 1100 1000 0000)
$73
(0111 0011)
$DCC0 (1101 1100 1100 0000)
and so on...
$FD
(1111 1101)
$FF40 (1111 1111 0100 0000)
$FE
(1111 1110)
$FF80 (1111 1111 1000 0000)
$FF
The entire FLASH memory is not protected.
1. The end address of the protected range is always $FFFF.

39
Memory

40
Chapter 3
3.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option register
(MOR).
The configuration registers enable or disable these options:
Computer operating properly module (COP)
COP timeout period (213 24 or 218 24 ICLK cycles)
Internal oscillator during stop mode

Low voltage inhibit (LVI) module
LVI module voltage trip point selection
STOP instruction
Stop mode recovery time (32 or 4096 ICLK cycles)
Pull-up on IRQ pin
The mask option register selects the oscillator option:

Crystal or RC

The configuration registers are used in the initialization of various options. The configuration registers can
be written once after each reset. All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU, it is recommended that these registers be written
immediately after reset. The configuration registers are located at $001E and $001F. The configuration
registers may be read at anytime.
NOTE
The options except LVIT[1:0] are one-time writable by the user after each
reset. The LVIT[1:0] bits are one-time writable by the user only after each
POR (power-on reset). The CONFIG registers are not in the FLASH
memory but are special registers containing one-time writable latches after
each reset. Upon a reset, the CONFIG registers default to predetermined
settings as shown in Figure 3-1 and Figure 3-2.
The mask option register (MOR) is used to select the oscillator option for the MCU: crystal oscillator or
RC oscillator. The MOR is implemented as a byte in FLASH memory. Hence, writing to the MOR requires
programming the byte.

41
3.3 Configuration Register 1 (CONFIG1)

Address:
Read:
Write:
Reset:
$001F
Bit 7
Bit 0
COPRS
LVID
SSREC
STOP
COPD
= Reserved
Figure 3-1. Configuration Register 1 (CONFIG1)

COPRS COP Rate Select Bit
COPRS selects the COP time-out period. Reset clears COPRS.
(See Chapter 14 Computer Operating Properly (COP).)
1 = COP timeout period is (213 24) ICLK cycles
LVID Low Voltage Inhibit Disable Bit
LVID disables the LVI module. Reset clears LVID.
(See Chapter 15 Low Voltage Inhibit (LVI).)
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
SSREC Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of
32 ICLK cycles instead of a 4096 ICLK cycle delay.
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
NOTE
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
STOP STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD COP Disable Bit
COPD disables the COP module. Reset clears COPD.
(See Chapter 14 Computer Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled

42
Configuration Register 2 (CONFIG2)
3.4 Configuration Register 2 (CONFIG2)

Address:
Read:
Write:
Reset:
POR:
$001E
Bit 7
Bit 0
IRQPUD
LVIT1
LVIT0
STOP_
ICLKDIS
= Reserved
Not affected Not affected
One-time writable register after each reset. LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only.

IRQPUD IRQ Pin Pull-Up Disable Bit
IRQPUD disconnects the internal pull-up on the IRQ pin.
1 = Internal pull-up is disconnected
0 = Internal pull-up is connected between IRQ pin and VDD
LVIT1, LVIT0 LVI Trip Voltage Selection Bits
Detail description of trip voltage selection is given in Chapter 15 Low Voltage Inhibit (LVI).
STOP_ICLKDIS Internal Oscillator Stop Mode Disable Bit
Setting STOP_ICLKDIS disables the internal oscillator during stop mode. When this bit is cleared, the
internal oscillator continues to operate in stop mode. Reset clears this bit.
1 = Internal oscillator disabled during stop mode
0 = Internal oscillator enabled during stop mode
3.5 Mask Option Register (MOR)

The mask option register (MOR) is implemented as a byte within the FLASH memory, and therefore can
only be written during a programming sequence of the FLASH memory. This register is read after a
power-on reset to determine the type of oscillator selected. (See Chapter 6 Oscillator (OSC).)
Address:
Read:
Write:
Erased:
$FFD0
Bit 7
Bit 0
OSCSEL
Reset:
Unaffected by reset

R
= Reserved
Figure 3-3. Mask Option Register (MOR)

OSCSEL Oscillator Select Bit
OSCSEL selects the oscillator type for the MCU. The erased or unprogrammed state of this bit is
logic 1, selecting the crystal oscillator option. This bit is unaffected by reset.
1 = Crystal oscillator
0 = RC oscillator
43
Bits 60 Should be left as logic 1s.

NOTE
When Crystal oscillator is selected, the OSC2/RCCLK/PTA6/KBI6 pin is
used as OSC2; other functions such as PTA6/KBI6 will not be available.

44
Chapter 4
4.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of
the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes, and architecture.
4.2 Features
Object code fully upward-compatible with M68HC05 Family

16-bit stack pointer with stack manipulation instructions
16-Bit Index Register with X-Register Manipulation Instructions
8-MHz CPU Internal Bus Frequency
64-Kbyte Program/Data Memory Space
16 Addressing Modes
Memory-to-Memory Data Moves without Using Accumulator
Fast 8-Bit by 8-Bit Multiply and 16-Bit by 8-Bit Divide Instructions
Enhanced Binary-Coded Decimal (BCD) Data Handling
Modular Architecture with Expandable Internal Bus Definition for Extension of Addressing Range
beyond 64 Kbytes
Low-Power Stop and Wait Modes

45
4.3 CPU Registers

Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map.
0
ACCUMULATOR (A)
0
15
H
INDEX REGISTER (H:X)
15
0
STACK POINTER (SP)
15
0
PROGRAM COUNTER (PC)
7
0
V 1 1 H I N Z C
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWOS COMPLEMENT OVERFLOW FLAG
Figure 4-1. CPU Registers
4.3.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and
the results of arithmetic/logic operations.
Bit 7
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 4-2. Accumulator (A)
4.3.2 Index Register

The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of
the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the
conditional address of the operand.
The index register can serve also as a temporary data storage location.

46
CPU Registers
Bit
15
14
13
12
11
10
Bit 0
Read:
Write:
Reset:
X = Indeterminate
Figure 4-3. Index Register (H:X)
4.3.3 Stack Pointer

The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a
reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an
index register to access data on the stack. The CPU uses the contents of the stack pointer to determine
the conditional address of the operand.
Bit
15
14
13
12
11
10
Bit 0
Read:
Write:
Reset:
Figure 4-4. Stack Pointer (SP)

NOTE
The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address
(page 0) space. For correct operation, the stack pointer must point only to
RAM locations.
4.3.4 Program Counter

The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
Normally, the program counter automatically increments to the next sequential memory location every
time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF.
The vector address is the address of the first instruction to be executed after exiting the reset state.

47
Bit
15
14
13
12
11
10
Bit 0
Read:
Write:
Reset:
Loaded with Vector from $FFFE and $FFFF
Figure 4-5. Program Counter (PC)
4.3.5 Condition Code Register

The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the
instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe
the functions of the condition code register.
Read:
Write:
Reset:
Bit 7
Bit 0
X = Indeterminate
Figure 4-6. Condition Code Register (CCR)

V Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch
instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
H Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an
add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and
C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled
when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.

48
Arithmetic/Logic Unit (ALU)
After the I bit is cleared, the highest-priority interrupt request is serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the
interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the
clear interrupt mask software instruction (CLI).
N Negative flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation
produces a negative result, setting bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z Zero flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of $00.
1 = Zero result
0 = Non-zero result
C Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some instructions such as bit test
and branch, shift, and rotate also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
4.4 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (Freescale document order number CPU08RM/AD) for a
description of the instructions and addressing modes and more detail about the architecture of the CPU.
4.5 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
4.5.1 Wait Mode

The WAIT instruction:
Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
4.5.2 Stop Mode

The STOP instruction:
Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.

49
4.6 CPU During Break Interrupts

If a break module is present on the MCU, the CPU starts a break interrupt by:
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
4.7 Instruction Set Summary

Table 4-1 provides a summary of the M68HC08 instruction set.
4.8 Opcode Map

The opcode map is provided in Table 4-2.
V H I N Z C
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
Add with Carry
A (A) + (M) + (C)
IMM
DIR
EXT
IX2
R R R R R
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
IMM
DIR
EXT
IX2
R R R R R
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add without Carry
AIS #opr
Add Immediate Value (Signed) to SP
SP (SP) + (16 M)
IMM
AIX #opr
Add Immediate Value (Signed) to H:X
H:X (H:X) + (16 M)
IMM
A (A) + (M)
ff
ee ff
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 4-1. Instruction Set Summary
2
3
4
4
3
2
4
5
ff
ee ff
2
3
4
4
3
2
4
5
A7
ii
AF
ii

50
Opcode Map
V H I N Z C
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
A (A) & (M)
Logical AND
Arithmetic Shift Left

(Same as LSL)
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
Arithmetic Shift Right
BCC rel
Branch if Carry Bit Clear
0
b7
b0
C
b7
b0
PC (PC) + 2 + rel ? (C) = 0
Mn 0
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
2
3
4
4
3
2
4
5
IMM
DIR
EXT
IX2
0 R R
IX1
IX
SP1
SP2
A4
B4
C4
D4
E4
F4
9EE4
9ED4
ii
dd
hh ll
ee ff
ff
DIR
INH
INH
R R R R
IX1
IX
SP1
38
48
58
68
78
9E68
dd
DIR
INH
INH
R R R R
IX1
IX
SP1
37
47
57
67
77
9E67
dd
ff
4
1
1
4
3
5
REL
24
rr
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)

DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
ff
ee ff
ff
ff
ff
4
1
1
4
3
5
BCLR n, opr
Clear Bit n in M
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC (PC) + 2 + rel ? (C) = 1
REL
25
rr
BEQ rel
Branch if Equal
PC (PC) + 2 + rel ? (Z) = 1
REL
27
rr
BGE opr
Branch if Greater Than or Equal To

(Signed Operands)
PC (PC) + 2 + rel ? (N V) = 0
REL
90
rr
BGT opr
Branch if Greater Than (Signed

Operands)
PC (PC) + 2 +rel ? (Z) | (N V)=0 REL
92
rr
BHCC rel
Branch if Half Carry Bit Clear
PC (PC) + 2 + rel ? (H) = 0
REL
28
rr
BHCS rel
Branch if Half Carry Bit Set
PC (PC) + 2 + rel ? (H) = 1
REL
29
rr
BHI rel
Branch if Higher
PC (PC) + 2 + rel ? (C) | (Z) = 0
REL
22
rr
BHS rel
Branch if Higher or Same

(Same as BCC)
PC (PC) + 2 + rel ? (C) = 0
REL
24
rr
BIH rel
Branch if IRQ Pin High
PC (PC) + 2 + rel ? IRQ = 1
REL
2F
rr
BIL rel
Branch if IRQ Pin Low
PC (PC) + 2 + rel ? IRQ = 0
REL
2E
rr

51
V H I N Z C
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
Bit Test
BLE opr
Branch if Less Than or Equal To

(Signed Operands)
BLO rel
Branch if Lower (Same as BCS)
BLS rel
(A) & (M)
IMM
DIR
EXT
IX2
0 R R
IX1
IX
SP1
SP2
PC (PC) + 2 + rel ? (Z) | (N V)=1 REL
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
ff
ee ff
2
3
4
4
3
2
4
5
93
rr
A5
B5
C5
D5
E5
F5
9EE5
9ED5
ii
dd
hh ll
ee ff
ff
PC (PC) + 2 + rel ? (C) = 1
REL
25
rr
Branch if Lower or Same
PC (PC) + 2 + rel ? (C) | (Z) = 1
REL
23
rr
BLT opr
Branch if Less Than (Signed Operands)
PC (PC) + 2 + rel ? (N V) = 1
REL
91
rr
BMC rel
Branch if Interrupt Mask Clear
PC (PC) + 2 + rel ? (I) = 0
REL
2C
rr
BMI rel
Branch if Minus
PC (PC) + 2 + rel ? (N) = 1
REL
2B
rr
BMS rel
Branch if Interrupt Mask Set
PC (PC) + 2 + rel ? (I) = 1
REL
2D
rr
BNE rel
Branch if Not Equal
PC (PC) + 2 + rel ? (Z) = 0
REL
26
rr
BPL rel
Branch if Plus
PC (PC) + 2 + rel ? (N) = 0
REL
2A
rr
BRA rel
Branch Always
PC (PC) + 2 + rel
REL
20
rr
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
R
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
REL
21
rr
PC (PC) + 3 + rel ? (Mn) = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
R
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)

DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BRCLR n,opr,rel Branch if Bit n in M Clear
BRN rel
Branch Never
BRSET n,opr,rel Branch if Bit n in M Set
BSET n,opr
Set Bit n in M
PC (PC) + 3 + rel ? (Mn) = 0
PC (PC) + 2

52
Opcode Map
V H I N Z C
BSR rel
Branch to Subroutine
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
Compare and Branch if Equal
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
PC (PC) + 2; push (PCL)

SP (SP) 1; push (PCH)
SP (SP) 1
PC (PC) + rel
REL
DIR
PC (PC) + 3 + rel ? (A) (M) = $00
IMM
PC (PC) + 3 + rel ? (A) (M) = $00
IMM
PC (PC) + 3 + rel ? (X) (M) = $00

IX1+
PC (PC) + 3 + rel ? (A) (M) = $00
IX+
PC (PC) + 2 + rel ? (A) (M) = $00
SP1
PC (PC) + 4 + rel ? (A) (M) = $00
AD
31
41
51
61
71
9E61
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
rr
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
CLC
Clear Carry Bit
C0
0 INH
98
CLI
Clear Interrupt Mask
I0
0 INH
9A
M $00
A $00
X $00
H $00
M $00
M $00
M $00
DIR
INH
INH
0 0 1 INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E6F
dd
(A) (M)
IMM
DIR
EXT
IX2
R R R R
IX1
IX
SP1
SP2
A1
B1
C1
D1
E1
F1
9EE1
9ED1
ii
dd
hh ll
ee ff
ff
DIR
INH
INH
0 R R 1
IX1
IX
SP1
33
43
53
63
73
9E63
dd
CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
Clear
Compare A with M
COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP
Complement (Ones Complement)
CPHX #opr
CPHX opr
Compare H:X with M
CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
Compare X with M
DAA
Decimal Adjust A
M (M) = $FF (M)

A (A) = $FF (M)
X (X) = $FF (M)
M (M) = $FF (M)
M (M) = $FF (M)
M (M) = $FF (M)
(H:X) (M:M + 1)
(X) (M)
(A)10
ff
ff
ff
ee ff
3
1
1
1
3
2
4
2
3
4
4
3
2
4
5
ff
4
1
1
4
3
5
65
75
ii ii+1
dd
3
4
IMM
DIR
EXT
IX2
R R R R
IX1
IX
SP1
SP2
A3
B3
C3
D3
E3
F3
9EE3
9ED3
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
U R R R INH
72
R R R R
IMM
DIR
ff
ff
ee ff

53
V H I N Z C
DBNZ opr,rel
DBNZA rel
Decrement and Branch if Not Zero
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP
Decrement
DIV
Divide
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Exclusive OR M with A
Increment
Jump
Jump to Subroutine
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
Load A from M
LDHX #opr
LDHX opr
Load H:X from M
A (A)1 or M (M)1 or X (X)1

DIR
PC (PC) + 3 + rel ? (result) 0
INH
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E6B
dd rr
rr
rr
ff rr
rr
ff rr
dd
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
5
3
3
5
4
6
M (M) 1
A (A) 1
X (X) 1
M (M) 1
M (M) 1
M (M) 1
DIR
INH
INH
R R R
IX1
IX
SP1
3A
4A
5A
6A
7A
9E6A
A (H:A)/(X)
H Remainder
R R INH
52
A (A M)
IMM
DIR
EXT
IX2
0 R R
IX1
IX
SP1
SP2
A8
B8
C8
D8
E8
F8
9EE8
9ED8
ii
dd
hh ll
ee ff
ff
M (M) + 1
A (A) + 1
X (X) + 1
M (M) + 1
M (M) + 1
M (M) + 1
DIR
INH
INH
R R R
IX1
IX
SP1
3C
4C
5C
6C
7C
9E6C
dd
PC Jump Address
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
PC (PC) + n (n = 1, 2, or 3)
Push (PCL); SP (SP) 1
Push (PCH); SP (SP) 1
PC Unconditional Address
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
4
5
6
5
4
A (M)
IMM
DIR
EXT
IX2
0 R R
IX1
IX
SP1
SP2
A6
B6
C6
D6
E6
F6
9EE6
9ED6
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5
ii jj
dd
3
4
H:X (M:M + 1)
0 R R
IMM
DIR
45
55
ff
ff
4
1
1
4
3
5
7
ff
ee ff
ff
ff
2
3
4
4
3
2
4
5
4
1
1
4
3
5

54
Opcode Map
V H I N Z C
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
IMM
DIR
EXT
IX2
0 R R
IX1
IX
SP1
SP2
AE
BE
CE
DE
EE
FE
9EEE
9EDE
ii
dd
hh ll
ee ff
ff
DIR
INH
INH
R R R R
IX1
IX
SP1
38
48
58
68
78
9E68
dd
DIR
INH
INH
R 0 R R
IX1
IX
SP1
34
44
54
64
74
9E64
dd
DD
DIX+
0 R R
IMD
IX+D
4E
5E
6E
7E
X:A (X) (A)
0 0 INH
42
M (M) = $00 (M)

A (A) = $00 (A)
X (X) = $00 (X)
M (M) = $00 (M)
M (M) = $00 (M)
DIR
INH
INH
R R R R
IX1
IX
SP1
30
40
50
60
70
9E60
X (M)
Load X from M
Logical Shift Left

(Same as ASL)
Logical Shift Right
0
b7
b0
C
b7
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
Move
MUL
Unsigned multiply
b0
(M)Destination (M)Source
H:X (H:X) + 1 (IX+D, DIX+)
ff
ee ff
ff
ff
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
2
3
4
4
3
2
4
5
4
1
1
4
3
5
ff
4
1
1
4
3
5
dd dd
dd
ii dd
dd
5
4
4
4
ff
5
dd
4
1
1
4
3
5
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
Negate (Twos Complement)
NOP
No Operation
None
INH
9D
NSA
Nibble Swap A
A (A[3:0]:A[7:4])
INH
62
A (A) | (M)
IMM
DIR
EXT
IX2
0 R R
IX1
IX
SP1
SP2
AA
BA
CA
DA
EA
FA
9EEA
9EDA
ff
ff
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
Inclusive OR A and M
PSHA
Push A onto Stack
Push (A); SP (SP) 1
INH
87
PSHH
Push H onto Stack
Push (H); SP (SP) 1
INH
8B
PSHX
Push X onto Stack
Push (X); SP (SP) 1
INH
89
PULA
Pull A from Stack
SP (SP + 1); Pull (A)
INH
86
ii
dd
hh ll
ee ff
ff
ff
ee ff
2
3
4
4
3
2
4
5

55
V H I N Z C
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
PULH
Pull H from Stack
SP (SP + 1); Pull (H)
INH
8A
PULX
Pull X from Stack
SP (SP + 1); Pull (X)
INH
88
39
49
59
69
79
9E69
dd
DIR
INH
INH
R R R R
IX1
IX
SP1
DIR
INH
INH
R R R R
IX1
IX
SP1
36
46
56
66
76
9E66
dd
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
Rotate Left through Carry
b7
b0
ff
ff
4
1
1
4
3
5
4
1
1
4
3
5
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
Rotate Right through Carry
RSP
Reset Stack Pointer
SP $FF
INH
9C
RTI
Return from Interrupt
SP (SP) + 1; Pull (CCR)

SP (SP) + 1; Pull (A)
SP (SP) + 1; Pull (X)
SP (SP) + 1; Pull (PCH)
SP (SP) + 1; Pull (PCL)
R R R R R R INH
80
RTS
Return from Subroutine
SP SP + 1; Pull (PCH)
SP SP + 1; Pull (PCL)
INH
81
A (A) (M) (C)
IMM
DIR
EXT
IX2
R R R R
IX1
IX
SP1
SP2
A2
B2
C2
D2
E2
F2
9EE2
9ED2
C
b7
b0
ff
ff
ii
dd
hh ll
ee ff
ff
2
3
4
4
3
2
4
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
Subtract with Carry
SEC
Set Carry Bit
C1
1 INH
99
SEI
Set Interrupt Mask
I1
1 INH
9B
M (A)
DIR
EXT
IX2
0 R R IX1
IX
SP1
SP2
B7
C7
D7
E7
F7
9EE7
9ED7
(M:M + 1) (H:X)
0 R R DIR
35
I 0; Stop Oscillator
0 INH
8E
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
STHX opr
Store H:X in M
STOP
Enable IRQ Pin; Stop Oscillator
ff
ee ff
ff
ee ff
3
4
4
3
2
4
5
dd
dd
hh ll
ee ff
ff

56
Opcode Map
V H I N Z C
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
Store X in M
Subtract
M (X)
A (A) (M)
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
3
4
4
3
2
4
5
DIR
EXT
IX2
0 R R IX1
IX
SP1
SP2
BF
CF
DF
EF
FF
9EEF
9EDF
dd
hh ll
ee ff
ff
IMM
DIR
EXT
IX2
R R R R
IX1
IX
SP1
SP2
A0
B0
C0
D0
E0
F0
9EE0
9ED0
ii
dd
hh ll
ee ff
ff
1 INH
83
ff
ee ff
ff
ee ff
2
3
4
4
3
2
4
5
SWI
Software Interrupt
PC (PC) + 1; Push (PCL)

SP (SP) 1; Push (PCH)
SP (SP) 1; Push (X)
SP (SP) 1; Push (A)
SP (SP) 1; Push (CCR)
SP (SP) 1; I 1
PCH Interrupt Vector High Byte
PCL Interrupt Vector Low Byte
TAP
Transfer A to CCR
CCR (A)
R R R R R R INH
84
TAX
Transfer A to X
X (A)
INH
97
TPA
Transfer CCR to A
A (CCR)
INH
85
(A) $00 or (X) $00 or (M) $00
DIR
INH
INH
0 R R
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
H:X (SP) + 1
INH
95
A (X)
INH
9F
(SP) (H:X) 1
INH
94
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
Test for Negative or Zero
TSX
Transfer SP to H:X
TXA
Transfer X to A
TXS
Transfer H:X to SP
dd
ff
ff
3
1
1
3
2
4

57
V H I N Z C
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate source to direct destination addressing mode
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
n
opr
PC
PCH
PCL
REL
rel
rr
SP1
SP2
SP
U
V
X
Z
&
|
()
( )
#
?
:
R
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (twos complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected

58
MSB
Branch
REL
DIR
INH
5
BRSET0
3 DIR
5
BRCLR0
3 DIR
5
BRSET1
3 DIR
5
BRCLR1
3 DIR
5
BRSET2
3 DIR
5
BRCLR2
3 DIR
5
BRSET3
3 DIR
5
BRCLR3
3 DIR
5
BRSET4
3 DIR
5
BRCLR4
3 DIR
5
BRSET5
3 DIR
5
BRCLR5
3 DIR
5
BRSET6
3 DIR
5
BRCLR6
3 DIR
5
BRSET7
3 DIR
5
BRCLR7
3 DIR
4
BSET0
2 DIR
4
BCLR0
2 DIR
4
BSET1
2 DIR
4
BCLR1
2 DIR
4
BSET2
2 DIR
4
BCLR2
2 DIR
4
BSET3
2 DIR
4
BCLR3
2 DIR
4
BSET4
2 DIR
4
BCLR4
2 DIR
4
BSET5
2 DIR
4
BCLR5
2 DIR
4
BSET6
2 DIR
4
BCLR6
2 DIR
4
BSET7
2 DIR
4
BCLR7
2 DIR
3
BRA
REL
3
BRN
2 REL
3
BHI
2 REL
3
BLS
2 REL
3
BCC
2 REL
3
BCS
2 REL
3
BNE
2 REL
3
BEQ
2 REL
3
BHCC
2 REL
3
BHCS
2 REL
3
BPL
2 REL
3
BMI
2 REL
3
BMC
2 REL
3
BMS
2 REL
3
BIL
2 REL
3
BIH
2 REL
Read-Modify-Write
INH
IX1
5
SP1
IX
9E6
Control
INH
INH
8
Register/Memory
IX2
SP2
IMM
DIR
EXT
9ED
4
SUB
EXT
4
CMP
3 EXT
4
SBC
3 EXT
4
CPX
3 EXT
4
AND
3 EXT
4
BIT
3 EXT
4
LDA
3 EXT
4
STA
3 EXT
4
EOR
3 EXT
4
ADC
3 EXT
4
ORA
3 EXT
4
ADD
3 EXT
3
JMP
3 EXT
5
JSR
3 EXT
4
LDX
3 EXT
4
STX
3 EXT
4
SUB
IX2
4
CMP
3 IX2
4
SBC
3 IX2
4
CPX
3 IX2
4
AND
3 IX2
4
BIT
3 IX2
4
LDA
3 IX2
4
STA
3 IX2
4
EOR
3 IX2
4
ADC
3 IX2
4
ORA
3 IX2
4
ADD
3 IX2
4
JMP
3 IX2
6
JSR
3 IX2
4
LDX
3 IX2
4
STX
3 IX2
5
SUB
SP2
5
CMP
4 SP2
5
SBC
4 SP2
5
CPX
4 SP2
5
AND
4 SP2
5
BIT
4 SP2
5
LDA
4 SP2
5
STA
4 SP2
5
EOR
4 SP2
5
ADC
4 SP2
5
ORA
4 SP2
5
ADD
4 SP2
IX1
SP1
IX
9EE
LSB
Table 4-2. Opcode Map

Bit Manipulation
DIR
DIR
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
4
1
NEG
NEGA
DIR 1 INH
5
4
CBEQ CBEQA
3 DIR 3 IMM
5
MUL
1 INH
4
1
COM
COMA
2 DIR 1 INH
4
1
LSR
LSRA
2 DIR 1 INH
4
3
STHX
LDHX
2 DIR 3 IMM
4
1
ROR
RORA
2 DIR 1 INH
4
1
ASR
ASRA
2 DIR 1 INH
4
1
LSL
LSLA
2 DIR 1 INH
4
1
ROL
ROLA
2 DIR 1 INH
4
1
DEC
DECA
2 DIR 1 INH
5
3
DBNZ DBNZA
3 DIR 2 INH
4
1
INC
INCA
2 DIR 1 INH
3
1
TST
TSTA
2 DIR 1 INH
5
MOV
3 DD
3
1
CLR
CLRA
2 DIR 1 INH
2
4
NEG
IX1
5
CBEQ
3 IX1+
3
NSA
1 INH
4
COM
2 IX1
4
LSR
2 IX1
3
CPHX
3 IMM
4
ROR
2 IX1
4
ASR
2 IX1
4
LSL
2 IX1
4
ROL
2 IX1
4
DEC
2 IX1
5
DBNZ
3 IX1
4
INC
2 IX1
3
TST
2 IX1
4
MOV
3 IMD
3
CLR
2 IX1
5
3
NEG
NEG
SP1 1 IX
6
4
CBEQ
CBEQ
4 SP1 2 IX+
2
DAA
1 INH
5
3
COM
COM
3 SP1 1 IX
5
3
LSR
LSR
3 SP1 1 IX
4
CPHX
2 DIR
5
3
ROR
ROR
3 SP1 1 IX
5
3
ASR
ASR
3 SP1 1 IX
5
3
LSL
LSL
3 SP1 1 IX
5
3
ROL
ROL
3 SP1 1 IX
5
3
DEC
DEC
3 SP1 1 IX
6
4
DBNZ
DBNZ
4 SP1 2 IX
5
3
INC
INC
3 SP1 1 IX
4
2
TST
TST
3 SP1 1 IX
4
MOV
2 IX+D
4
2
CLR
CLR
3 SP1 1 IX
SP1 Stack Pointer, 8-Bit Offset

SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
7
3
RTI
BGE
INH 2 REL
4
3
RTS
BLT
1 INH 2 REL
3
BGT
2 REL
9
3
SWI
BLE
1 INH 2 REL
2
2
TAP
TXS
1 INH 1 INH
1
2
TPA
TSX
1 INH 1 INH
2
PULA
1 INH
2
1
PSHA
TAX
1 INH 1 INH
2
1
PULX
CLC
1 INH 1 INH
2
1
PSHX
SEC
1 INH 1 INH
2
2
PULH
CLI
1 INH 1 INH
2
2
PSHH
SEI
1 INH 1 INH
1
1
CLRH
RSP
1 INH 1 INH
1
NOP
1 INH
1
STOP
*
1 INH
1
1
WAIT
TXA
1 INH 1 INH
1
2
SUB
IMM
2
CMP
2 IMM
2
SBC
2 IMM
2
CPX
2 IMM
2
AND
2 IMM
2
BIT
2 IMM
2
LDA
2 IMM
2
AIS
2 IMM
2
EOR
2 IMM
2
ADC
2 IMM
2
ORA
2 IMM
2
ADD
2 IMM
3
SUB
DIR
3
CMP
2 DIR
3
SBC
2 DIR
3
CPX
2 DIR
3
AND
2 DIR
3
BIT
2 DIR
3
LDA
2 DIR
3
STA
2 DIR
3
EOR
2 DIR
3
ADC
2 DIR
3
ORA
2 DIR
3
ADD
2 DIR
2
JMP
2 DIR
4
4
BSR
JSR
2 REL 2 DIR
2
3
LDX
LDX
2 IMM 2 DIR
2
3
AIX
STX
2 IMM 2 DIR
2
MSB
3
SUB
IX1
3
CMP
2 IX1
3
SBC
2 IX1
3
CPX
2 IX1
3
AND
2 IX1
3
BIT
2 IX1
3
LDA
2 IX1
3
STA
2 IX1
3
EOR
2 IX1
3
ADC
2 IX1
3
ORA
2 IX1
3
ADD
2 IX1
3
JMP
2 IX1
5
JSR
2 IX1
5
3
LDX
LDX
4 SP2 2 IX1
5
3
STX
STX
4 SP2 2 IX1
4
4
SUB
SP1
4
CMP
3 SP1
4
SBC
3 SP1
4
CPX
3 SP1
4
AND
3 SP1
4
BIT
3 SP1
4
LDA
3 SP1
4
STA
3 SP1
4
EOR
3 SP1
4
ADC
3 SP1
4
ORA
3 SP1
4
ADD
3 SP1
2
SUB
IX
2
CMP
1 IX
2
SBC
1 IX
2
CPX
1 IX
2
AND
1 IX
2
BIT
1 IX
2
LDA
1 IX
2
STA
1 IX
2
EOR
1 IX
2
ADC
1 IX
2
ORA
1 IX
2
ADD
1 IX
2
JMP
1 IX
4
JSR
1 IX
4
2
LDX
LDX
3 SP1 1 IX
4
2
STX
STX
3 SP1 1 IX
3
High Byte of Opcode in Hexadecimal
LSB
Low Byte of Opcode in Hexadecimal
5
Cycles
BRSET0 Opcode Mnemonic
3 DIR Number of Bytes / Addressing Mode
Opcode Map
59
INH Inherent
REL Relative
IMM Immediate
IX
Indexed, No Offset
DIR Direct
IX1 Indexed, 8-Bit Offset
EXT Extended
IX2 Indexed, 16-Bit Offset
DD Direct-Direct
IMD Immediate-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
1
NEGX
1 INH
4
CBEQX
3 IMM
7
DIV
1 INH
1
COMX
1 INH
1
LSRX
1 INH
4
LDHX
2 DIR
1
RORX
1 INH
1
ASRX
1 INH
1
LSLX
1 INH
1
ROLX
1 INH
1
DECX
1 INH
3
DBNZX
2 INH
1
INCX
1 INH
1
TSTX
1 INH
4
MOV
2 DIX+
1
CLRX
1 INH

60
Chapter 5
5.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM
is shown in Figure 5-1. Figure 5-2 is a summary of the SIM I/O registers. The SIM is a system state
controller that coordinates CPU and exception timing.
The SIM is responsible for:
Bus clock generation and control for CPU and peripherals
Stop/wait/reset/break entry and recovery
Internal clock control
Master reset control, including power-on reset (POR) and COP timeout
Interrupt control:
Acknowledge timing
Arbitration control timing
Vector address generation
CPU enable/disable timing
Modular architecture expandable to 128 interrupt sources
Table 5-1 shows the internal signal names used in this section.
Table 5-1. Signal Name Conventions
Signal Name
ICLK
Description
Internal oscillator clock
OSCOUT
The XTAL or RC frequency divided by two. This signal is again divided by two in the SIM
to generate the internal bus clocks. (Bus clock = OSCOUT 2)
IAB
Internal address bus
IDB
Internal data bus
PORRST
Signal from the power-on reset module to the SIM
IRST
Internal reset signal
R/W
Read/write signal

61

MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO OSCILLATOR)

SIM
COUNTER
COP CLOCK
ICLK (FROM OSCILLATOR)

OSCOUT (FROM OSCILLATOR)
2
VDD
CLOCK
CONTROL
INTERNAL
PULL-UP
RESET
PIN LOGIC
INTERNAL CLOCKS
CLOCK GENERATORS
POR CONTROL
MASTER
RESET
CONTROL
RESET PIN CONTROL

SIM RESET STATUS REGISTER
ILLEGAL OPCODE (FROM CPU)

ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
USB RESET (FROM USB MODULE)
RESET
INTERRUPT SOURCES
INTERRUPT CONTROL
AND PRIORITY DECODE
CPU INTERFACE
Figure 5-1. SIM Block Diagram

Addr.
$FE00
$FE01
$FE02
$FE03
Register Name
Read:
Break Status Register (BSR) Write:
Reset:
Read:
Reset Status Register (RSR) Write:
POR:
Read:
Reserved Write:
Reset:
Break Flag Control Read:
Register Write:
(BFCR) Reset:
Bit 7
Bit 0
1
SBSW
NOTE
0
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
BCFE
R
0
Figure 5-2. SIM I/O Register Summary

62
SIM Bus Clock Control and Generation
$FE04
$FE05
$FE06
Read:
Write:
(INT1)
Reset:
Read:
Write:
(INT2)
Reset:
Read:
Write:
(INT3)
Reset:
IF6
R
0
IF14
R
0
0
R
0
IF5
IF4
R
R
0
0
IF13
IF12
R
R
0
0
0
0
R
R
0
0
= Unimplemented
IF3
R
0
IF11
R
0
0
R
0
0
R
0
0
R
0
0
R
0
R
IF1
R
0
0
R
0
0
R
0
= Reserved
0
R
0
IF8
R
0
0
R
0
0
R
0
IF7
R
0
IF15
R
0
Figure 5-2. SIM I/O Register Summary
5.2 SIM Bus Clock Control and Generation

The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, OSCOUT, as shown in Figure 5-3.
From
OSCILLATOR
ICLK
From
OSCILLATOR
OSCOUT
SIM COUNTER
BUS CLOCK
GENERATORS
OSCOUT is OSC frequency divided by 2

SIM
Figure 5-3. SIM Clock Signals
5.2.1 Bus Timing

In user mode, the internal bus frequency is the oscillator frequency divided by four.
5.2.2 Clock Start-Up from POR or LVI Reset

When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after the 4096 ICLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks
start upon completion of the timeout.
5.2.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt, break, or reset, the SIM allows ICLK to clock the SIM counter.
The CPU and peripheral clocks do not become active until after the stop delay time-out. This time-out is
selectable as 4096 or 32 ICLK cycles. (See 5.6.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules.
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.

63
5.3 Reset and System Initialization

The MCU has these reset sources:
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
All of these resets produce the vector $FFFE$FFFF ($FEFE$FEFF in Monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 5.4 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the reset status register (RSR). (See 5.7 SIM Registers.)
5.3.1 External Pin Reset

The RST pin circuits include an internal pull-up device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the reset status register (RSR) is set as long as RST is held low for a minimum
of 67 ICLK cycles, assuming that the POR was not the source of the reset. See Table 5-2 for details.
Figure 5-4 shows the relative timing.
Table 5-2. PIN Bit Set Timing
Reset Type
Number of Cycles Required to Set PIN
POR
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
ICLK
RST
IAB
VECT H
PC
VECT L
Figure 5-4. External Reset Timing
5.3.2 Active Resets from Internal Sources

All internal reset sources actively pull the RST pin low for 32 ICLK cycles to allow resetting of external
peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
(Figure 5-5). An internal reset can be caused by an illegal address, illegal opcode, COP time-out, or POR.
(See Figure 5-6 . Sources of Internal Reset.) Note that for POR resets, the SIM cycles through 4096 ICLK
cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence
from the falling edge of RST shown in Figure 5-5.

64
Reset and System Initialization

IRST
RST
RST PULLED LOW BY MCU

32 CYCLES
32 CYCLES
ICLK
IAB
VECTOR HIGH
Figure 5-5. Internal Reset Timing

The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
INTERNAL RESET
LVI
Figure 5-6. Sources of Internal Reset

The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
5.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 ICLK cycles. Sixty-four ICLK cycles later, the CPU and memories are released from reset to allow
the reset vector sequence to occur.
At power-on, the following events occur:
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables OSCOUT.
Internal clocks to the CPU and modules are held inactive for 4096 ICLK cycles to allow stabilization
of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared.

65
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
ICLK
OSCOUT
RST
IAB
$FFFE
$FFFF
Figure 5-7. POR Recovery

5.3.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an
internal reset and sets the COP bit in the reset status register (RSR). The SIM actively pulls down the
RST pin for all internal reset sources.
To prevent a COP module time-out, write any value to location $FFFF. Writing to location $FFFF clears
the COP counter and stages 12 through 5 of the SIM counter. The SIM counter output, which occurs at
least every (212 24) ICLK cycles, drives the COP counter. The COP should be serviced as soon as
possible out of reset to guarantee the maximum amount of time before the first time-out.
The COP module is disabled if the RST pin or the IRQ pin is held at VTST while the MCU is in monitor
mode. The COP module can be disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of
external noise. During a break state, VTST on the RST pin disables the COP module.
5.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the reset status register (RSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is logic zero, the SIM treats the STOP instruction
as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
5.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the reset status register (RSR) and resetting
the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down
the RST pin for all internal reset sources.
5.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVI
trip voltage VTRIP. The LVI bit in the reset status register (RSR) is set, and the external reset pin (RST) is
66
SIM Counter
held low while the SIM counter counts out 4096 ICLK cycles. Sixty-four ICLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls
down the RST pin for all internal reset sources.
5.4 SIM Counter

The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for
counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of ICLK.
5.4.1 SIM Counter During Power-On Reset

The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock
state machine.
5.4.2 SIM Counter During Stop Mode Recovery

The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay
of 4096 ICLK cycles down to 32 ICLK cycles. This is ideal for applications using canned oscillators that
do not require long start-up times from stop mode. External crystal applications should use the full stop
recovery time, that is, with SSREC cleared in the configuration register 1 (CONFIG1).
5.4.3 SIM Counter and Reset States

External reset has no effect on the SIM counter. (See 5.6.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. (See 5.3.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
5.5 Exception Control

Normal, sequential program execution can be changed in three different ways:
Interrupts
Maskable hardware CPU interrupts
Non-maskable software interrupt instruction (SWI)
Reset
Break interrupts
5.5.1 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event.
Figure 5-8 flow charts the handling of system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
67

FROM RESET
BREAK
INTERRUPT?
I BIT
SET?
YES
NO
YES
I BIT SET?
NO
IRQ
INTERRUPT?
YES
NO
TIMER 1
INTERRUPT?
YES
NO
STACK CPU REGISTERS.

SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
(As many interrupts as exist on chip)
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CPU REGISTERS.
NO
EXECUTE INSTRUCTION.
Figure 5-8. Interrupt Processing

68
Exception Control
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 5-9 shows
interrupt entry timing.
Figure 5-10 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
IAB
DUMMY
IDB
SP
DUMMY
SP 1
SP 2
PC 1[7:0] PC 1[15:8]
SP 3
SP 4
VECT H
CCR
VECT L
V DATA H
START ADDR
V DATA L
OPCODE
R/W
Figure 5-9. Interrupt Entry

MODULE
INTERRUPT
I BIT
IAB
SP 4
IDB
SP 3
CCR
SP 2
SP 1
SP
PC
PC 1[15:8] PC 1[7:0]
PC + 1
OPCODE
OPERAND
R/W
Figure 5-10. Interrupt Recovery

5.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first. Figure 5-11 demonstrates what happens when two interrupts are pending. If an interrupt is
pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.

69

CLI
LDA #$FF
INT1
BACKGROUND ROUTINE
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 5-11. Interrupt Recognition Example

The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
5.5.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC 1, as a hardware interrupt does.
5.5.2 Interrupt Status Registers

The flags in the interrupt status registers identify maskable interrupt sources. Table 5-3 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.

70
Exception Control
Table 5-3. Interrupt Sources

Flag
Mask (1)
INT Flag
Vector Address
Reset
$FFFE$FFFF
SWI Instruction
$FFFC$FFFD
IRQ Pin
IRQF
IMASK
IF1
$FFFA$FFFB
Timer 1 Channel 0 Interrupt
CH0F
CH0IE
IF3
$FFF6$FFF7
CH1F
CH1IE
IF4
$FFF4$FFF5
TOF
TOIE
IF5
$FFF2$FFF3
CH0F
CH0IE
IF6
$FFF0$FFF1
CH1F
CH1IE
IF7
$FFEE$FFEF
Timer 2 Overflow Interrupt
TOF
TOIE
IF8
$FFEC$FFED
SCI Error
OR
NF
FE
PE
ORIE
NEIE
FEIE
PEIE
IF11
$FFE6$FFE7
SCI Receive
SCRF
IDLE
SCRIE
ILIE
IF12
$FFE4$FFE5
SCI Transmit
SCTE
TC
SCTIE
TCIE
IF13
$FFE2$FFE3
Keyboard Interrupt
KEYF
IMASKK
IF14
$FFE0$FFE1
ADC Conversion Complete Interrupt
COCO
AIEN
IF15
$FFDE$FFDF
Priority
Highest
Source
Timer 1 Overflow Interrupt
Lowest
1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction.
5.5.2.1 Interrupt Status Register 1

Address:
$FE04
Bit 7
Bit 0
Read:
IF6
IF5
IF4
IF3
IF1
Write:
Reset:
= Reserved
Figure 5-12. Interrupt Status Register 1 (INT1)

IF1, IF3 to IF6 Interrupt Flags
These flags indicate the presence of interrupt requests from the sources shown in Table 5-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0, 1, and 3 Always read 0

71

Address:
$FE05
Bit 7
Bit 0
Read:
IF14
IF13
IF12
IF11
IF8
IF7
Write:
Reset:
= Reserved

IF7, IF8, IF11 to F14 Interrupt Flags
This flag indicates the presence of interrupt requests from the sources shown in Table 5-3.
Bit 2 and 3 Always read 0
Address:
$FE06
Bit 7
Bit 0
Read:
IF15
Write:
= Reserved
Reset:

IF15 Interrupt Flags
These flags indicate the presence of interrupt requests from the sources shown in Table 5-3.
Bit 1 to 7 Always read 0
5.5.3 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
5.5.4 Break Interrupts

The break module can stop normal program flow at a software-programmable break point by asserting its
break interrupt output. (See Chapter 16 Break Module (BREAK).) The SIM puts the CPU into the break
state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to
see how each module is affected by the break state.

72
Low-Power Modes
5.5.5 Status Flag Protection in Break Mode

The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This
protection allows registers to be freely read and written during break mode without losing status flag
information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains
cleared even when break mode is exited. Status flags with a two-step clearing mechanism for example,
a read of one register followed by the read or write of another are protected, even when the first step
is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step
will clear the flag as normal.
5.6 Low-Power Modes

Executing the WAIT or STOP instruction puts the MCU in a low-power-consumption mode for standby
situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is
described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing
interrupts to occur.
5.6.1 Wait Mode

In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 5-15 shows
the timing for wait mode entry.
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break
stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD, in the mask option
register is logic zero, then the computer operating properly module (COP) is enabled and remains active
in wait mode.
IAB
IDB
WAIT ADDR
WAIT ADDR + 1
PREVIOUS DATA
SAME
NEXT OPCODE
SAME
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 5-15. Wait Mode Entry Timing

Figure 5-16 and Figure 5-17 show the timing for WAIT recovery.

73

IAB
$6E0B
IDB
$A6
$6E0C
$A6
$A6
$01
$00FF
$0B
$00FE
$00FD
$00FC
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 5-16. Wait Recovery from Interrupt or Break

32
Cycles
$6E0B
IAB
IDB
$A6
$A6
32
Cycles
RST VCTH
RSTVCTL
$A6
RST
ICLK
Figure 5-17. Wait Recovery from Internal Reset
5.6.2 Stop Mode

In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (OSCOUT) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the SSREC bit in the configuration register 1 (CONFIG1). If SSREC is
set, stop recovery is reduced from the normal delay of 4096 ICLK cycles down to 32. This is ideal for
applications using canned oscillators that do not require long start-up times from stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the break status register
(BSR).
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 5-18 shows stop mode entry timing.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.

74
SIM Registers
CPUSTOP
IAB
STOP ADDR
IDB
STOP ADDR + 1
PREVIOUS DATA
SAME
SAME
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 5-18. Stop Mode Entry Timing
STOP RECOVERY PERIOD

ICLK
INT/BREAK
IAB
STOP + 2
STOP +1
STOP + 2
SP
SP 1
SP 2
SP 3
Figure 5-19. Stop Mode Recovery from Interrupt or Break
5.7 SIM Registers

The SIM has three memory mapped registers.
Break Status Register (BSR)
Reset Status Register (RSR)
Break Flag Control Register (BFCR)
5.7.1 Break Status Register (BSR)

The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.
Address:
Read:
Write:
Reset:
$FE00
Bit 7
= Reserved
Bit 0
SBSW
Note(1)
0
R
0
1. Writing a logic zero clears SBSW.
Figure 5-20. Break Status Register (BSR)

75
SBSW SIM Break Stop/Wait

This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break
interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it. The following code is an example of this. Writing zero to the SBSW bit
clears it.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE
EQU
LOBYTE
EQU
If not SBSW, do RTI

BRCLR
SBSW,BSR, RETURN
; See if wait mode or stop mode was exited

; by break.
TST
LOBYTE,SP
; If RETURNLO is not zero,
BNE
DOLO
; then just decrement low byte.
DEC
HIBYTE,SP
; Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN
PULH
RTI
; Restore H register.
5.7.2 Reset Status Register (RSR)

This register contains six flags that show the source of the last reset. Clear the SIM reset status register
by reading it. A power-on reset sets the POR bit and clears all other bits in the register.
Address:
Read:
$FE01
Bit 7
Bit 0
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
Write:
POR:
= Unimplemented
Figure 5-21. Reset Status Register (RSR)

POR Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of RSR

76
SIM Registers
PIN External Reset Bit

1 = Last reset caused by external reset pin (RST)
0 = POR or read of RSR
COP Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
ILOP Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
ILAD Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
MODRST Monitor Mode Entry Module Reset bit
1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after
POR while IRQ = VDD
LVI Low Voltage Inhibit Reset bit
1 = Last reset caused by LVI circuit
5.7.3 Break Flag Control Register (BFCR)

The break control register contains a bit that enables software to clear status bits while the MCU is in a
break state.
Address:
Read:
Write:
Reset:
$FE03
Bit 7
Bit 0
BCFE
0
R
= Reserved
Figure 5-22. Break Flag Control Register (BFCR)

BCFE Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break

77

78
Chapter 6
Oscillator (OSC)
6.1 Introduction
The oscillator module provides the reference clocks for the MCU system and bus. Two oscillators are
running on the device:
Selectable oscillator for bus clock
Crystal oscillator (XTAL) built-in oscillator that requires an external crystal or ceramic-resonator.
This option also allows an external clock that can be driven directly into OSC1.
RC oscillator (RC) built-in oscillator that requires an external resistor-capacitor connection only.
The selected oscillator is used to drive the bus clock, the SIM, and other modules on the MCU. The
oscillator type is selected by programming a bit FLASH memory. The RC and crystal oscillator cannot run
concurrently; one is disabled while the other is selected; because the RC and XTAL circuits share the
same OSC1 pin.
Non-selectable oscillator for COP
Internal oscillator built-in RC oscillator that requires no external components.
This internal oscillator is used to drive the computer operating properly (COP) module and the SIM. The
internal oscillator runs continuously after a POR or reset, and is always available.
6.2 Oscillator Selection

The oscillator type is selected by programming a bit in a FLASH memory location; the mask option register
(MOR), at $FFD0.
(See 3.5 Mask Option Register (MOR).)
NOTE
On the ROM device, the oscillator is selected by a ROM-mask layer at
factory.
Address:
Read:
Write:
Erased:
$FFD0
Bit 7
Bit 0
OSCSEL
Reset:
Unaffected by reset

R
= Reserved
Figure 6-1. Mask Option Register (MOR)

79
Oscillator (OSC)
OSCSEL Oscillator Select Bit

OSCSEL selects the oscillator type for the MCU. The erased or unprogrammed state of this bit is
logic 1, selecting the crystal oscillator option. This bit is unaffected by reset.
1 = Crystal oscillator
0 = RC oscillator
Bits 60 Should be left as logic 1s.
NOTE
When Crystal oscillator is selected, the OSC2/RCCLK/PTA6/KBI6 pin is
used as OSC2; other functions such as PTA6/KBI6 will not be available.
6.2.1 XTAL Oscillator

The XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide
accurate clock source.
In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator configuration, as shown
in Figure 6-2. This figure shows only the logical representation of the internal components and may not
represent actual circuitry. The oscillator configuration uses five components:
Crystal, X1
Fixed capacitor, C1
Tuning capacitor, C2 (can also be a fixed capacitor)
Feedback resistor, RB
Series resistor, RS (optional)
From SIM
To SIM
2OSCOUT
XTALCLK
To SIM
OSCOUT
SIMOSCEN
MCU
OSC1
RB
OSC2
RS*
X1
*RS can be zero (shorted) when used with higher-frequency crystals.

Refer to manufacturers data.
See Chapter 17 for component value requirements.
C1
C2
Figure 6-2. XTAL Oscillator External Connections

The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not
be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal
manufacturers data for more information.
80
Internal Oscillator
6.2.2 RC Oscillator
The RC oscillator circuit is designed for use with external resistor and capacitor to provide a clock source
with tolerance less than 10%.
In its typical configuration, the RC oscillator requires two external components, one R and one C.
Component values should have a tolerance of 1% or less, to obtain a clock source with less than 10%
tolerance. The oscillator configuration uses two components:
CEXT
REXT
To SIM
From SIM
2OSCOUT
SIMOSCEN
EN
EXT-RC
OSCILLATOR
To SIM
OSCOUT
RCCLK
0
PTA6
I/O
PTA6
PTA6EN
MCU
RCCLK/PTA6 (OSC2)
OSC1
VDD
REXT
CEXT
See Chapter 17 for component value requirements.
Figure 6-3. RC Oscillator External Connections
6.3 Internal Oscillator

The internal oscillator clock (ICLK) is a free running 50-kHz clock that requires no external components.
It is used as the reference clock input to the computer operating properly (COP) module and the SIM.
The internal oscillator by default is always available and is free running after POR or reset. It can be
stopped in stop mode by setting the STOP_ICLKDIS bit before executing the STOP instruction.
Figure 6-4 shows the logical representation of components of the internal oscillator circuitry.
From SIM
To SIM and COP
SIMOSCEN
ICLK
CONFIG2
STOP_ICLKDIS
EN
INTERNAL
OSCILLATOR
Figure 6-4. Internal Oscillator

81
Oscillator (OSC)
NOTE
The internal oscillator is a free running oscillator and is available after each
POR or reset. It is turned-off in stop mode by setting the STOP_ICLKDIS
bit in CONFIG2 (see 3.4 Configuration Register 2 (CONFIG2)).
6.4 I/O Signals

The following paragraphs describe the oscillator I/O signals.
6.4.1 Crystal Amplifier Input Pin (OSC1)

OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit.
6.4.2 Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6)

For the XTAL oscillator, OSC2 pin is the output of the crystal oscillator inverting amplifier.
For the RC oscillator, OSC2 pin can be configured as a general purpose I/O pin PTA6, or the output of
the RC oscillator, RCCLK.
Oscillator
OSC2 pin function
XTAL
Inverting OSC1
RC
Controlled by PTA6EN bit in PTAPUE ($000D)

PTA6EN = 0: RCCLK output
PTA6EN = 1: PTA6/KBI6
6.4.3 Oscillator Enable Signal (SIMOSCEN)

The SIMOSCEN signal comes from the system integration module (SIM) and enables/disables the XTAL
oscillator circuit or the RC-oscillator.
6.4.4 XTAL Oscillator Clock (XTALCLK)

XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes
directly from the crystal oscillator circuit. Figure 6-2 shows only the logical relation of XTALCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude of XTALCLK can be
unstable at start-up.
6.4.5 RC Oscillator Clock (RCCLK)

RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of the
external R and C. Figure 6-3 shows only the logical relation of RCCLK to OSC1 and may not represent
the actual circuitry.
6.4.6 Oscillator Out 2 (2OSCOUT)

2OSCOUT is same as the input clock (XTALCLK or RCCLK). This signal is driven to the SIM module.

82
Low Power Modes
6.4.7 Oscillator Out (OSCOUT)

The frequency of this signal is equal to half of the 2OSCOUT, this signal is driven to the SIM for generation
of the bus clocks used by the CPU and other modules on the MCU. OSCOUT will be divided again in the
SIM and results in the internal bus frequency being one fourth of the XTALCLK or RCCLK frequency.
6.4.8 Internal Oscillator Clock (ICLK)

ICLK is the internal oscillator output signal (typically 50-kHz), for the COP module and the SIM. Its
frequency depends on the VDD voltage. (See Chapter 17 Electrical Specifications for ICLK parameters.)
6.5 Low Power Modes

The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
6.5.1 Wait Mode

The WAIT instruction has no effect on the oscillator logic. OSCOUT, 2OSCOUT, and ICLK continues to
drive to the SIM module.
6.5.2 Stop Mode

The STOP instruction disables the XTALCLK or the RCCLK output, hence, OSCOUT and 2OSCOUT are
disabled.
The STOP instruction also turns off the ICLK input to the COP module if the STOP_ICLKDIS bit is set in
configuration register 2 (CONFIG2). After reset, the STOP_ICLKDIS bit is clear by default and ICLK is
enabled during stop mode.
6.6 Oscillator During Break Mode

The OSCOUT, 2OSCOUT, and ICLK clocks continue to be driven out when the device enters the break
state.

83
Oscillator (OSC)

84
Chapter 7
Monitor ROM (MON)
7.1 Introduction
This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM
allows complete testing of the MCU through a single-wire interface with a host computer. This mode is
also used for programming and erasing of FLASH memory in the MCU. Monitor mode entry can be
achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are
blank, thus reducing the hardware requirements for in-circuit programming.
7.2 Features
Features of the monitor ROM include the following:
Normal user-mode pin functionality
One pin dedicated to serial communication between monitor ROM and host computer
Standard mark/space non-return-to-zero (NRZ) communication with host computer
Execution of code in RAM or FLASH
FLASH memory security feature(1)
FLASH memory programming interface
959 bytes monitor ROM code size
Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain
$FF)
Standard monitor mode entry if high voltage, VTST, is applied to IRQ
Resident routines for FLASH programming and EEPROM emulation

The monitor ROM receives and executes commands from a host computer. Figure 7-1 shows a example
circuit used to enter monitor mode and communicate with a host computer via a standard RS-232
interface.
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute
host-computer code in RAM while most MCU pins retain normal operating mode functions. All
communication between the host computer and the MCU is through the PTB0 pin. A level-shifting and
multiplexing interface is required between PTB0 and the host computer. PTB0 is used in a wired-OR
configuration and requires a pull-up resistor.
unauthorized users.
85
Monitor ROM (MON)
RST
0.1 F
HC908JL8
VDD
VDD
VDD
EXT OSC (50% DUTY)

0.1 F
OSC1
VSS
EXT OSC CONNECTION TO OSC1, WITH OSC2

UNCONNECTED, CAN REPLACE XTAL CIRCUIT.
9.8304MHz
10M
OSC1
20 pF
OSC2
20 pF
MAX232
1
1 F
+
3
4
1 F
C1+
VDD
VCC
C1
GND
C2+
V+
16
+
XTAL CIRCUIT
1 F
15
1 F
+
VDD
+
5 C2
6
1 F
3
5
10
(SEE NOTE 1)
IRQ
VDD
10 k
10 k
74HC125
5
6
DB9
7
SW1
1k
8.5 V
+
2
VTST
74HC125
3
2
PTB0
VDD
VDD
1
10 k
10 k
C
PTB1
SW2
PTB3
(SEE NOTE 2)
NOTES:
1. Monitor mode entry method:
SW1: Position A High voltage entry (VTST)
Bus clock depends on SW2.
SW1: Position B Reset vector must be blank ($FFFE = $FFFF = $FF)
Bus clock = OSC1 4.
2. Affects high voltage entry to monitor mode only (SW1 at position A):
SW2: Position C Bus clock = OSC1 4
SW2: Position D Bus clock = OSC1 2
5. See Table 17-4 for VTST voltage level requirements.
D
10 k
PTB2
10 k
Figure 7-1. Monitor Mode Circuit

86
Functional Description
7.3.1 Entering Monitor Mode

Table 7-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a POR.
Communication at 9600 baud will be established provided one of the following sets of conditions is met:
1. If IRQ = VTST:
Clock on OSC1 is 4.9125MHz
PTB3 = low
2. If IRQ = VTST:
PTB3 = high
3. If $FFFE and $FFFF are blank (contain $FF):
IRQ = VDD
PTB2
VTST(2)
VTST(1)
VDD
BLANK
(contain
$FF)
9.8304MHz
2.4576MHz
VDD
NOT
BLANK
OSC1 4
PTB0
$FFFE
and
$FFFF
PTB1
IRQ
PTB3
Table 7-1. Monitor Mode Entry Requirements and Options

OSC1 Clock(1)
Bus Frequency
Comments
4.9152MHz
2.4576MHz
9.8304MHz
2.4576MHz
High voltage entry to monitor

mode.
9600 baud communication on
PTB0. COP disabled.
Blank reset vector
(low-voltage) entry to monitor
mode.
9600 baud communication on
PTB0. COP disabled.
Enters User mode.
1. RC oscillator cannot be used for monitor mode; must use either external oscillator or XTAL oscillator circuit.
2. See Table 17-4 for VTST voltage level requirements.
If VTST is applied to IRQ and PTB3 is low upon monitor mode entry (Table 7-1 condition set 1), the bus
frequency is a divide-by-two of the clock input to OSC1. If PTB3 is high with VTST applied to IRQ upon
monitor mode entry (Table 7-1 condition set 2), the bus frequency is a divide-by-four of the clock input to
OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two stage
at the oscillator only if VTST is applied to IRQ. In this event, the OSCOUT frequency is equal to the
2OSCOUT frequency, and OSC1 input directly generates internal bus clocks. In this case, the OSC1
signal must have a 50% duty cycle at maximum bus frequency.
Entering monitor mode with VTST on IRQ, the COP is disabled as long as VTST is applied to either IRQ or
RST. (See Chapter 5 System Integration Module (SIM) for more information on modes of operation.)
If entering monitor mode without high voltage on IRQ and reset vector being blank ($FFFE and $FFFF)
(Table 7-1 condition set 3, where applied voltage is VDD), then all port B pin requirements and conditions,
87
Monitor ROM (MON)
including the PTB3 frequency divisor selection, are not in effect. This is to reduce circuit requirements
when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is always disabled regardless of the
state of IRQ or the RST.
Figure 7-2. shows a simplified diagram of the monitor mode entry when the reset vector is blank and IRQ
= VDD. An OSC1 frequency of 9.8304MHz is required for a baud rate of 9600.
POR RESET
IS VECTOR
BLANK?
NO
NORMAL USER
MODE
YES
MONITOR MODE
EXECUTE
MONITOR
CODE
POR
TRIGGERED?
NO
YES
Figure 7-2. Low-Voltage Monitor Mode Entry Flowchart

Enter monitor mode with the pin configuration shown above by pulling RST low and then high. The rising
edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can
change.
Once out of reset, the MCU waits for the host to send eight security bytes. (See 7.4 Security.) After the
security bytes, the MCU sends a break signal (10 consecutive logic zeros) to the host, indicating that it is
ready to receive a command. The break signal also provides a timing reference to allow the host to
determine the necessary baud rate.
In monitor mode, the MCU uses different vectors for reset, SWI, and break interrupt. The alternate vectors
are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware
instead of user code.
Table 7-2 is a summary of the vector differences between user mode and monitor mode.

88
Table 7-2. Monitor Mode Vector Differences

Functions
Modes
COP
Reset
Vector
High
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
User
Enabled
$FFFE
$FFFF
$FFFC
$FFFD
$FFFC
$FFFD
Monitor
Disabled(1)
$FEFE
$FEFF
$FEFC
$FEFD
$FEFC
$FEFD
Notes:
1. If the high voltage (VTST) is removed from the IRQ pin or the RST pin, the SIM asserts
its COP enable output. The COP is a mask option enabled or disabled by the COPD bit
in the configuration register.
When the host computer has completed downloading code into the MCU RAM, the host then sends a
RUN command, which executes an RTI, which sends control to the address on the stack pointer.
7.3.2 Baud Rate

The communication baud rate is dependant on oscillator frequency. The state of PTB3 also affects baud
rate if entry to monitor mode is by IRQ = VTST. When PTB3 is high, the divide by ratio is 1024. If the PTB3
pin is at logic zero upon entry into monitor mode, the divide by ratio is 512.
Table 7-3. Monitor Baud Rate Selection
Monitor Mode
Entry By:
IRQ = VTST
Blank reset vector,

IRQ = VDD
OSC1 Clock
Frequency
PTB3
Baud Rate
4.9152 MHz
9600 bps
9.8304 MHz
9600 bps
4.9152 MHz
4800 bps
9.8304 MHz
9600 bps
4.9152 MHz
4800 bps
7.3.3 Data Format

Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
(See Figure 7-3 and Figure 7-4.)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
NEXT
START
BIT
Figure 7-3. Monitor Data Format

$A5
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BREAK
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP
BIT
STOP
BIT
NEXT
START
BIT
NEXT
START
BIT
Figure 7-4. Sample Monitor Waveforms

89
Monitor ROM (MON)
The data transmit and receive rate can be anywhere from 4800 baud to 28.8k-baud. Transmit and receive
baud rates must be identical.
7.3.4 Echoing
As shown in Figure 7-5, the monitor ROM immediately echoes each received byte back to the PTB0 pin
for error checking.
SENT TO
MONITOR
READ
READ
ADDR. HIGH ADDR. HIGH
ADDR. LOW
ADDR. LOW
ECHO
DATA
RESULT
Figure 7-5. Read Transaction

Any result of a command appears after the echo of the last byte of the command.
7.3.5 Break Signal

A start bit followed by nine low bits is a break signal. (See Figure 7-6.) When the monitor receives a break
signal, it drives the PTB0 pin high for the duration of two bits before echoing the break signal.
MISSING STOP BIT

TWO-STOP-BIT DELAY BEFORE ZERO ECHO
Figure 7-6. Break Transaction
7.3.6 Commands
The monitor ROM uses the following commands:
READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer)
RUN (run user program)

90
Table 7-4. READ (Read Memory) Command

Description
Read byte from memory
Operand
Specifies 2-byte address in high byte:low byte order
Data Returned
Returns contents of specified address
Opcode
$4A
Command Sequence
SENT TO
MONITOR
READ
READ
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
ECHO
DATA
RESULT
Table 7-5. WRITE (Write Memory) Command

Description
Write byte to memory
Operand
Specifies 2-byte address in high byte:low byte order; low byte followed by data byte
Data Returned
None
Opcode
$49
Command Sequence
SENT TO
MONITOR
WRITE
WRITE
ADDR. HIGH
ADDR. HIGH
ADDR. LOW
ADDR. LOW
DATA
DATA
ECHO

91
Monitor ROM (MON)
Table 7-6. IREAD (Indexed Read) Command

Description
Read next 2 bytes in memory from last address accessed
Operand
Specifies 2-byte address in high byte:low byte order
Data Returned
Returns contents of next two addresses
Opcode
$1A
Command Sequence
SENT TO
MONITOR
IREAD
IREAD
DATA
DATA
RESULT
ECHO
Table 7-7. IWRITE (Indexed Write) Command

Description
Write to last address accessed + 1
Operand
Specifies single data byte
Data Returned
None
Opcode
$19
Command Sequence
SENT TO
MONITOR
IWRITE
IWRITE
DATA
DATA
ECHO
NOTE
A sequence of IREAD or IWRITE commands can sequentially access a
block of memory over the full 64-Kbyte memory map.

92
Security
Table 7-8. READSP (Read Stack Pointer) Command

Description
Reads stack pointer
Operand
None
Data Returned
Returns stack pointer in high byte:low byte order
Opcode
$0C
Command Sequence
SENT TO
MONITOR
READSP
READSP
SP HIGH
SP LOW
RESULT
ECHO
Table 7-9. RUN (Run User Program) Command

Description
Executes RTI instruction
Operand
None
Data Returned
None
Opcode
$28
Command Sequence
SENT TO
MONITOR
RUN
RUN
ECHO
7.4 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host
can bypass the security feature at monitor mode entry by sending eight security bytes that match the
bytes at locations $FFF6$FFFD. Locations $FFF6$FFFD contain user-defined data.
NOTE
Do not leave locations $FFF6$FFFD blank. For security reasons, program
locations $FFF6$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security
bytes on pin PTB0. If the received bytes match those at locations $FFF6$FFFD, the host bypasses the
security feature and can read all FLASH locations and execute code from FLASH. Security remains
bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed
and security code entry is not required. (See Figure 7-7.)
93
Monitor ROM (MON)
VDD
4096 + 32 ICLK CYCLES
RST
COMMAND
BYTE 8
BYTE 2
BYTE 1
24 BUS CYCLES
FROM HOST
PTB0
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
1
COMMAND ECHO
BREAK
1
BYTE 8 ECHO
1
BYTE 2 ECHO
FROM MCU
4
BYTE 1 ECHO
Figure 7-7. Monitor Mode Entry Timing

Upon power-on reset, if the received bytes of the security code do not match the data at locations
$FFF6$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but
reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an
illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break
character, signifying that it is ready to receive a command.
NOTE
The MCU does not transmit a break character until after the host sends the
eight security bytes.
To determine whether the security code entered is correct, check to see if bit 6 of RAM address $60 is
set. If it is, then the correct security code has been entered and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor
mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass
erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation
clears the security code locations so that all eight security bytes become $FF (blank).
7.5 ROM-Resident Routines

Eight routines stored in the monitor ROM area (thus ROM-resident) are provided for FLASH memory
manipulation. Six of the eight routines are intended to simplify FLASH program, erase, and load
operations. The other two routines are intended to simplify the use of the FLASH memory as EEPROM.
Table 7-10 shows a summary of the ROM-resident routines.

94
ROM-Resident Routines
Table 7-10. Summary of ROM-Resident Routines

Routine Name
Routine Description
Call Address
Stack Used(1)
(bytes)
PRGRNGE
Program a range of locations
$FC06
15
ERARNGE
Erase a page or the entire array
$FCBE
Loads data from a range of locations
$FF30
MON_PRGRNGE
Program a range of locations in monitor

mode
$FF28
17
MON_ERARNGE
Erase a page or the entire array in monitor

mode
$FF2C
11
Loads data from a range of locations in

monitor mode
$FF24
11
EE_WRITE
Emulated EEPROM write. Data size ranges

from 2 to 15 bytes at a time.
$FD3F
24
EE_READ
Emulated EEPROM read. Data size ranges

from 2 to 15 bytes at a time.
$FDD0
16
LDRNGE
MON_LDRNGE
1. The listed stack size excludes the 2 bytes used by the calling instruction, JSR.
The routines are designed to be called as stand-alone subroutines in the user program or monitor mode.
The parameters that are passed to a routine are in the form of a contiguous data block, stored in RAM.
The index register (H:X) is loaded with the address of the first byte of the data block (acting as a pointer),
and the subroutine is called (JSR). Using the start address as a pointer, multiple data blocks can be used,
any area of RAM be used. A data block has the control and data bytes in a defined order, as shown in
Figure 7-8.
During the software execution, it does not consume any dedicated RAM location, the run-time heap will
extend the system stack, all other RAM location will not be affected.
FILE_PTR
$XXXX
ADDRESS AS POINTER
BUS SPEED (BUS_SPD)

DATA SIZE (DATASIZE)
START ADDRESS HIGH (ADDRH)
START ADDRESS LOW (ADDRL)
DATA 0
DATA 1
DATA
BLOCK
DATA
ARRAY
DATA N
Figure 7-8. Data Block Format for ROM-Resident Routines

95
Monitor ROM (MON)
The control and data bytes are described below.

Bus speed This one byte indicates the operating bus speed of the MCU. The value of this byte
should be equal to 4 times the bus speed, and should not be set to less than 4 (i.e. minimum bus
speed is 1MHz).
Data size This one byte indicates the number of bytes in the data array that are to be
manipulated. The maximum data array size is 128. Routines EE_WRITE and EE_READ are
restricted to manipulate a data array between 2 to 15 bytes. Whereas routines ERARNGE and
MON_ERARNGE do not manipulate a data array, thus, this data size byte has no meaning.
Start address These two bytes, high byte followed by low byte, indicate the start address of the
FLASH memory to be manipulated.
Data array This data array contains data that are to be manipulated. Data in this array are
programmed to FLASH memory by the programming routines: PRGRNGE, MON_PRGRNGE,
EE_WRITE. For the read routines: LDRNGE, MON_LDRNGE, and EE_READ, data is read from
FLASH and stored in this array.
7.5.1 PRGRNGE
PRGRNGE is used to program a range of FLASH locations with data loaded into the data array.
Table 7-11. PRGRNGE Routine
Routine Name
PRGRNGE
Routine Description
Program a range of locations
Calling Address
$FC06
Stack Used
15 bytes
Data Block Format
Bus speed (BUS_SPD)

Data size (DATASIZE)
Start address high (ADDRH)
Start address (ADDRL)
Data 1 (DATA1)
:
Data N (DATAN)
The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the
number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can be
programmed in one routine call is 128 bytes (max. DATASIZE is 128).
ADDRH:ADDRL do not need to be at a page boundary, the routine handles any boundary misalignment
during programming. A check to see that all bytes in the specified range are erased is not performed by
this routine prior programming. Nor does this routine do a verification after programming, so there is no
return confirmation that programming was successful. User must assure that the range specified is first
erased.
The coding example below is to program 32 bytes of data starting at FLASH location $EF00, with a bus
speed of 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address
pointer, FILE_PTR, pointing to the first byte of the data block.

96
ORG
RAM
:
FILE_PTR:
BUS_SPD
DATASIZE
START_ADDR
DATAARRAY
DS.B
DS.B
DS.W
DS.B
1; Indicates 4x bus frequency

1; Data size to be programmed
1; FLASH start address
32; Reserved data array
PRGRNGE
FLASH_START
EQU
EQU
$FC06
$EF00
ORG
FLASH
INITIALISATION:
MOV
#20,
BUS_SPD
MOV
#32,
DATASIZE
LDHX
#FLASH_START
STHX
START_ADDR
RTS
MAIN:
BSR
INITIALISATION
:
:
LDHX
#FILE_PTR
JSR
PRGRNGE
7.5.2 ERARNGE
ERARNGE is used to erase a range of locations in FLASH.
Table 7-12. ERARNGE Routine
Routine Name
ERARNGE
Routine Description
Erase a page or the entire array
Calling Address
$FCBE
Stack Used
9 bytes
Data Block Format
Bus speed (BUS_SPD)

Starting address (ADDRH)
Starting address (ADDRL)
There are two sizes of erase ranges: a page or the entire array. The ERARNGE will erase the page (64
consecutive bytes) in FLASH specified by the address ADDRH:ADDRL. This address can be any address
within the page. Calling ERARNGE with ADDRH:ADDRL equal to $FFFF will erase the entire FLASH
array (mass erase). Therefore, care must be taken when calling this routine to prevent an accidental mass
erase. To avoid undesirable routine return addresses after a mass erase, the ERARNGE routine should
not be called from code executed from FLASH memory. Load the code into an area of RAM before calling
the ERARNGE routine.
The ERARNGE routine do not use a data array. The DATASIZE byte is a dummy byte that is also not
used.
97
Monitor ROM (MON)
The coding example below is to perform a page erase, from $EF00$EF3F. The Initialization subroutine
is the same as the coding example for PRGRNGE (see 7.5.1 PRGRNGE).
ERARNGE
MAIN:
EQU
BSR
:
:
LDHX
JSR
:
$FCBE
INITIALISATION
#FILE_PTR
ERARNGE
7.5.3 LDRNGE
LDRNGE is used to load the data array in RAM with data from a range of FLASH locations.
Table 7-13. LDRNGE Routine
Routine Name
LDRNGE
Routine Description
Loads data from a range of locations
Calling Address
$FF30
Stack Used
9 bytes
Data Block Format
Bus speed (BUS_SPD)

Starting address (ADDRH)
Starting address (ADDRL)
Data 1
:
Data N
The start location of FLASH from where data is retrieved is specified by the address ADDRH:ADDRL and
the number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can
be retrieved in one routine call is 128 bytes. The data retrieved from FLASH is loaded into the data array
in RAM. Previous data in the data array will be overwritten. User can use this routine to retrieve data from
FLASH that was previously programmed.
The coding example below is to retrieve 32 bytes of data starting from $EF00 in FLASH. The Initialization
subroutine is the same as the coding example for PRGRNGE (see 7.5.1 PRGRNGE).
LDRNGE
MAIN:
EQU
BSR
:
:
LDHX
JSR
:
$FF30
INITIALIZATION
#FILE_PTR
LDRNGE

98
7.5.4 MON_PRGRNGE
In monitor mode, MON_PRGRNGE is used to program a range of FLASH locations with data loaded into
the data array.
Table 7-14. MON_PRGRNGE Routine
Routine Name
MON_PRGRNGE
Routine Description
Program a range of locations, in monitor mode
Calling Address
$FC28
Stack Used
17 bytes
Data Block Format
Bus speed
Data size
Starting address (high byte)
Starting address (low byte)
Data 1
:
Data N
The MON_PRGRNGE routine is designed to be used in monitor mode. It performs the same function as
the PRGRNGE routine (see 7.5.1 PRGRNGE), except that MON_PRGRNGE returns to the main program
via an SWI instruction. After a MON_PRGRNGE call, the SWI instruction will return the control back to
the monitor code.
7.5.5 MON_ERARNGE
In monitor mode, ERARNGE is used to erase a range of locations in FLASH.
Table 7-15. MON_ERARNGE Routine
Routine Name
MON_ERARNGE
Routine Description
Erase a page or the entire array, in monitor mode
Calling Address
$FF2C
Stack Used
11 bytes
Data Block Format
Bus speed
Data size
The MON_ERARNGE routine is designed to be used in monitor mode. It performs the same function as
the ERARNGE routine (see 7.5.2 ERARNGE), except that MON_ERARNGE returns to the main program
via an SWI instruction. After a MON_ERARNGE call, the SWI instruction will return the control back to the
monitor code.

99
Monitor ROM (MON)
7.5.6 MON_LDRNGE
In monitor mode, LDRNGE is used to load the data array in RAM with data from a range of FLASH
locations.
Table 7-16. ICP_LDRNGE Routine
Routine Name
MON_LDRNGE
Routine Description
Loads data from a range of locations, in monitor mode
Calling Address
$FF24
Stack Used
11 bytes
Data Block Format
Bus speed
Data size
Data 1
:
Data N
The MON_LDRNGE routine is designed to be used in monitor mode. It performs the same function as the
LDRNGE routine (see 7.5.3 LDRNGE), except that MON_LDRNGE returns to the main program via an
SWI instruction. After a MON_LDRNGE call, the SWI instruction will return the control back to the monitor
code.
7.5.7 EE_WRITE
EE_WRITE is used to write a set of data from the data array to FLASH.
Table 7-17. EE_WRITE Routine
Routine Name
EE_WRITE
Routine Description
Emulated EEPROM write. Data size ranges from 2 to 15 bytes at

a time.
Calling Address
$FD3F
Stack Used
24 bytes
Data Block Format
Bus speed (BUS_SPD)

Data size (DATASIZE)(1)
Starting address (ADDRH)(2)
Starting address (ADDRL)(1)
Data 1
:
Data N
1. The minimum data size is 2 bytes. The maximum data size is 15 bytes.
2. The start address must be a page boundary start address: $xx00, $xx40, $xx80, or $00C0.
The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the
number of bytes in the data array is specified by DATASIZE. The minimum number of bytes that can be
100
programmed in one routine call is 2 bytes, the maximum is 15 bytes. ADDRH:ADDRL must always be the
start of boundary address (the page start address: $XX00, $XX40, $XX80, or $00C0) and DATASIZE
must be the same size when accessing the same page.
In some applications, the user may want to repeatedly store and read a set of data from an area of
non-volatile memory. This is easily possible when using an EEPROM array. As the write and erase
operations can be executed on a byte basis. For FLASH memory, the minimum erase size is the page
64 bytes per page for MC68HC908JL8. If the data array size is less than the page size, writing and erasing
to the same page cannot fully utilize the page. Unused locations in the page will be wasted. The
EE_WRITE routine is designed to emulate the properties similar to the EEPROM. Allowing a more
efficient use of the FLASH page for data storage.
When the user dedicates a page of FLASH for data storage, and the size of the data array defined, each
call of the EE_WRTIE routine will automatically transfer the data in the data array (in RAM) to the next
blank block of locations in the FLASH page. Once a page is filled up, the EE_WRITE routine automatically
erases the page, and starts to reuse the page again. In the 64-byte page, an 4-byte control block is used
by the routine to monitor the utilization of the page. In effect, only 60 bytes are used for data storage. (see
Figure 7-9). The page control operations are transparent to the user.
F L A S H
PAGE BOUNDARY
CONTROL: 8 BYTES
$XX00, $XX40, $XX80, OR $XXC0
DATA ARRAY
DATA ARRAY
DATA ARRAY
ONE PAGE = 64 BYTES
PAGE BOUNDARY
Figure 7-9. EE_WRITE FLASH Memory Usage

When using this routine to store a 3-byte data array, the FLASH page can be programmed 20 times before
the an erase is required. In effect, the write/erase endurance is increased by 20 times. When a 15-byte
data array is used, the write/erase endurance is increased by 5 times. Due to the FLASH page size
limitation, the data array is limited from 2 bytes to 15 bytes.
The coding example below uses the $EF00$EE3F page for data storage. The data array size is 15 bytes,
and the bus speed is 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the
address pointer, FILE_PTR, pointing to the first byte of the data block.

101
Monitor ROM (MON)
ORG
RAM
:
FILE_PTR:
BUS_SPD
DATASIZE
START_ADDR
DATAARRAY
DS.B
DS.B
DS.W
DS.B
1; Indicates 4x bus frequency

1; Data size to be programmed
1; FLASH starting address
15; Reserved data array
EE_WRITE
FLASH_START
EQU
EQU
$FD3F
$EF00
ORG
FLASH
INITIALISATION:
MOV
#20,
BUS_SPD
MOV
#15,
DATASIZE
LDHX
#FLASH_START
STHX
START_ADDR
RTS
MAIN:
BSR
INITIALISATION
:
:
LHDX
#FILE_PTR
JSR
EE_WRITE
NOTE
The EE_WRITE routine is unable to check for incorrect data blocks, such
as the FLASH page boundary address and data size. It is the responsibility
of the user to ensure the starting address indicated in the data block is at
the FLASH page boundary and the data size is 2 to 15. If the FLASH page
is already programmed with a data array with a different size, the
EE_WRITE call will be ignored.

102
7.5.8 EE_READ
EE_READ is used to load the data array in RAM with a set of data from FLASH.
Table 7-18. EE_READ Routine
Routine Name
EE_READ
Routine Description
Emulated EEPROM read. Data size ranges from 2 to 15 bytes at

a time.
Calling Address
$FDD0
Stack Used
16 bytes
Data Block Format
Bus speed (BUS_SPD)

Starting address (ADDRH)(1)
Starting address (ADDRL)(1)
Data 1
:
Data N
1. The start address must be a page boundary start address: $xx00, $xx40, $xx80, or $00C0.
The EE_READ routine reads data stored by the EE_WRITE routine. An EE_READ call will retrieve the
last data written to a FLASH page and loaded into the data array in RAM. Same as EE_WRITE, the data
size indicated by DATASIZE is 2 to 15, and the start address ADDRH:ADDRL must the FLASH page
boundary address.
The coding example below uses the data stored by the EE_WRITE coding example (see 7.5.7
EE_WRITE). It loads the 15-byte data set stored in the $EF00$EE7F page to the data array in RAM. The
initialization subroutine is the same as the coding example for EE_WRITE (see 7.5.7 EE_WRITE).
EE_READ
EQU
$FDD0
MAIN:
BSR
:
:
LDHX
JSR
:
INITIALIZATION
FILE_PTR
EE_READ
NOTE
The EE_READ routine is unable to check for incorrect data blocks, such as
the FLASH page boundary address and data size. It is the responsibility of
the user to ensure the starting address indicated in the data block is at the
FLASH page boundary and the data size is 2 to 15. If the FLASH page is
programmed with a data array with a different size, the EE_READ call will
be ignored.

103
Monitor ROM (MON)

104
Chapter 8
8.1 Introduction
This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a
timing reference with Input capture, output compare, and pulse-width-modulation functions. Figure 8-1 is
a block diagram of the TIM.
This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
8.2 Features
Features of the TIM include:
Two input capture/output compare channels:
Rising-edge, falling-edge, or any-edge input capture trigger
Set, clear, or toggle output compare action
Buffered and unbuffered pulse-width-modulation (PWM) signal generation
Programmable TIM clock input
7-frequency internal bus clock prescaler selection
External clock input on timer 2 (bus frequency 2 maximum)
Free-running or modulo up-count operation
Toggle any channel pin on overflow
TIM counter stop and reset bits
8.3 Pin Name Conventions

The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are
T[1,2]CH0 (timer channel 0) and T[1,2]CH1 (timer channel 1), where 1 is used to indicate TIM1 and 2
is used to indicate TIM2. The two TIMs share four I/O pins with four I/O port pins. The external clock input
for TIM2 is shared with the an ADC channel pin. The full names of the TIM I/O pins are listed in Table 8-1.
The generic pin names appear in the text that follows.
Table 8-1. Pin Name Conventions
TIM Generic Pin Names:
Full TIM
Pin Names:
T[1,2]CH0
T[1,2]CH1
T2CLK
TIM1
PTD4/T1CH0
PTD5/T1CH1
TIM2
PTE0/T2CH0
PTE1/T2CH1
ADC12/T2CLK
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TCH0 may refer generically to
T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1.
105

Figure 8-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter
that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM counter modulo registers,
TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value
at any time without affecting the counting sequence.
The two TIM channels (per timer) are programmable independently as input capture or output compare
channels.
T2CLK
(FOR TIM2 ONLY)
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
PS2
TRST
PS1
PS0
16-BIT COUNTER
TOF
TOIE
INTERRUPT
LOGIC
16-BIT COMPARATOR
TMODH:TMODL
TOV0
CHANNEL 0
ELS0B
ELS0A
CH0MAX
16-BIT COMPARATOR
PORT
LOGIC
T[1,2]CH0
CH0F
TCH0H:TCH0L
16-BIT LATCH
MS0A
CH0IE
INTERRUPT
LOGIC
MS0B
INTERNAL BUS
TOV1
CHANNEL 1
ELS0B
ELS0A
CH1MAX
PORT
LOGIC
CH01IE
INTERRUPT
LOGIC
T[1,2]CH1
16-BIT COMPARATOR
CH1F
TCH1H:TCH1L
16-BIT LATCH
MS0A
CH1IE
Figure 8-1. TIM Block Diagram

Figure 8-2 summarizes the timer registers.
NOTE
omitting the timer number. For example, TSC may generically refer to both
T1SC and T2SC.

106
Addr.
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$0030
$0031
$0032
$0033
Register Name
TIM1 Status and Control

Register
(T1SC)
TIM1 Counter Register
High
(T1CNTH)
Low
(T1CNTL)
TIM Counter Modulo
Register High
(TMODH)
TIM1 Counter Modulo
Register Low
(T1MODL)
TIM1 Channel 0 Status
and Control Register
(T1SC0)
TIM1 Channel 0
Register High
(T1CH0H)
TIM1 Channel 0
Register Low
(T1CH0L)
(T1SC1)
TIM1 Channel 1
Register High
(T1CH1H)
TIM1 Channel 1
Register Low
(T1CH1L)
TIM2 Status and Control
Register
(T2SC)
High
(T2CNTH)
Low
(T2CNTL)
TIM2 Counter Modulo
Register High
(T2MODH)
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
TOF
0
0
Bit 15
1
13
4
0
TRST
0
12
TOIE
TSTOP
0
14
0
Bit 7
0
6
0
5
Bit 15
3
0
Bit 0
PS2
PS1
PS0
0
11
0
10
0
9
0
Bit 8
0
4
0
3
0
2
0
1
0
Bit 0
14
13
12
11
10
Bit 8
Bit 7
Bit 0
1
CH0F
0
0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Bit 15
14
13
12
11
10
Bit 8
Bit 0

Bit 7

CH1F
0
0
Bit 15
CH1IE
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
14
13
12
11
10
Bit 8
Bit 0
PS2
PS1
PS0
0
10
0
9
0
Bit 8

Bit 7
TOF
0
0
Bit 15

0
0
TRST
0
0
12
11
TOIE
TSTOP
0
14
1
13
0
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
Bit 15
14
13
12
11
10
Bit 8
1
1
= Unimplemented
Figure 8-2. TIM I/O Register Summary (Sheet 1 of 2)

107

Addr.
$0034
$0035
$0036
$0037
$0038
$0039
$003A
Register Name
TIM2 Counter Modulo

Register Low
(T2MODL)
(T2SC0)
TIM2 Channel 0
Register High
(T2CH0H)
TIM2 Channel 0
Register Low
(T2CH0L)
(T2SC1)
TIM2 Channel 1
Register High
(T2CH1H)
TIM2 Channel 1
Register Low
(T2CH1L)
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
Bit 0
Bit 7
Bit 0
1
CH0F
0
0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Bit 15
14
13
12
11
10
Bit 8
Bit 0

Bit 7

CH1F
0
0
Bit 15
CH1IE
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
14
13
12
11
10
Bit 8
Bit 0

Bit 7

= Unimplemented
Figure 8-2. TIM I/O Register Summary (Sheet 2 of 2)

8.4.1 TIM Counter Prescaler
The TIM1 clock source can be one of the seven prescaler outputs; TIM2 clock source can be one of the
seven prescaler outputs or the TIM2 clock pin, T2CLK. The prescaler generates seven clock rates from
the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register select the
TIM clock source.
8.4.2 Input Capture

With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
8.4.3 Output Compare

With the output compare function, the TIM can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU
interrupt requests.

108
8.4.3.1 Unbuffered Output Compare

Any output compare channel can generate unbuffered output compare pulses as described in 8.4.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
When changing to a larger output compare value, enable TIM overflow interrupts and write the new
value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the
current counter overflow period. Writing a larger value in an output compare interrupt routine (at
the end of the current pulse) could cause two output compares to occur in the same counter
overflow period.
8.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
TCH0 pin. The TIM channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin.
Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the
output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that
control the output are the ones written to last. TSC0 controls and monitors the buffered output compare
function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the
channel 1 pin, TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
8.4.4 Pulse Width Modulation (PWM)

By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM
signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The
channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time
between overflows is the period of the PWM signal.
As Figure 8-3 shows, the output compare value in the TIM channel registers determines the pulse width
of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM

109
to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to
set the pin if the state of the PWM pulse is logic 0.
The value in the TIM counter modulo registers and the selected prescaler output determines the
frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus
clock period if the prescaler select value is $000. See 8.9.1 TIM Status and Control Register.
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 8-3. PWM Period and Pulse Width

The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of
an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers
produces a duty cycle of 128/256 or 50%.
8.4.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as described in 8.4.4 Pulse Width
Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect
operation for up to two PWM periods. For example, writing a new value before the counter reaches the
old value but after the counter reaches the new value prevents any compare during that PWM period.
Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the
compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:
When changing to a shorter pulse width, enable channel x output compare interrupts and write the
new value in the output compare interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the PWM period to write the new
value.
When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in
the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM
period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same PWM period.

110
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare also can
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
8.4.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin.
The TIM channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel
1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning
of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM
channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
NOTE
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
8.4.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM
period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 8-3.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level
select bits, ELSxB:ELSxA. The output action on compare must force the output to the
complement of the pulse width level. (See Table 8-3.)
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
111
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel
0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0
(TSCR0) controls and monitors the PWM signal from the linked channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. (See 8.9.4 TIM Channel Status and Control Registers.)
8.5 Interrupts
The following TIM sources can generate interrupt requests:
TIM overflow flag (TOF) The TOF bit is set when the TIM counter reaches the modulo value
programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control
register.
TIM channel flags (CH1F:CH0F) The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1.
CHxF and CHxIE are in the TIM channel x status and control register.
8.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
8.6.1 Wait Mode

The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not
accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait
mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
8.6.2 Stop Mode

The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode
after an external interrupt.

112
TIM During Break Interrupts
8.7 TIM During Break Interrupts

A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. (See 5.7.3 Break Flag Control Register (BFCR).)
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
8.8 I/O Signals

Port D shares two of its pins with TIM1 and port E shares two of its pins with TIM2. The ADC12/T2CLK
pin is an external clock input to TIM2. The four TIM channel I/O pins are T1CH0, T1CH1, T2CH0, and
T2CH1.
8.8.1 TIM Clock Pin (ADC12/T2CLK)

ADC12/T2CLK is an external clock input that can be the clock source for the TIM2 counter instead of the
prescaled internal bus clock. Select the ADC12/T2CLK input by writing logic 1s to the three prescaler
select bits, PS[2:0]. (See 8.9.1 TIM Status and Control Register.) The minimum T2CLK pulse width,
T2CLKLMIN or T2CLKHMIN, is:
1
------------------------------------- + t
bus frequency SU
The maximum T2CLK frequency is:
bus frequency 2
ADC12/T2CLK is available as a ADC input channel pin when not used as the TIM2 clock input.
8.8.2 TIM Channel I/O Pins (PTD4/T1CH0, PTD5/T1CH1, PTE0/T2CH0, PTE1/T2CH1)

Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins.

113
8.9 I/O Registers

NOTE
omitting the timer number. For example, TSC may generically refer to both
T1SC AND T2SC.
These I/O registers control and monitor operation of the TIM:
TIM status and control register (TSC)
TIM counter registers (TCNTH:TCNTL)
TIM counter modulo registers (TMODH:TMODL)
TIM channel status and control registers (TSC0, TSC1)
TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
8.9.1 TIM Status and Control Register

The TIM status and control register (TSC):
Enables TIM overflow interrupts
Flags TIM overflows
Stops the TIM counter
Resets the TIM counter
Prescales the TIM counter clock
Address: T1SC, $0020 and T2SC, $0030
Bit 7
Read:
TOF
Write:
Reset:
TOIE
TSTOP
TRST
0
Bit 0
PS2
PS1
PS0
= Unimplemented
Figure 8-4. TIM Status and Control Register (TSC)

TOF TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM
counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set
and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is
complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost
due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the
TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled

114
I/O Registers
TSTOP TIM Stop Bit

This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the
TSTOP bit, stopping the TIM counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on
any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM
counter is reset and always reads as logic 0. Reset clears the TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at
a value of $0000.
PS[2:0] Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as
Table 8-2 shows. Reset clears the PS[2:0] bits.
Table 8-2. Prescaler Selection
PS2
PS1
PS0
TIM Clock Source
Internal bus clock 1
T2CLK (for TIM2 only)
8.9.2 TIM Counter Registers

The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.

115
Address: T1CNTH, $0021 and T2CNTH, $0031

Read:
Bit 7
Bit 0
Bit 15
14
13
12
11
10
Bit 8
Write:
Reset:
= Unimplemented
Figure 8-5. TIM Counter Registers High (TCNTH)

Address: T1CNTL, $0022 and T2CNTL, $0032
Read:
Bit 7
Bit 0
Bit 7
Bit 0
Write:
Reset:
= Unimplemented
Figure 8-6. TIM Counter Registers Low (TCNTL)
8.9.3 TIM Counter Modulo Registers

The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter
reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow
interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: T1MODH, $0023 and T2MODH, $0033
Read:
Write:
Reset:
Bit 7
Bit 0
Bit 15
14
13
12
11
10
Bit 8
Figure 8-7. TIM Counter Modulo Register High (TMODH)

Address: T1MODL, $0024 and T2MODL, $0034
Read:
Write:
Reset:
Bit 7
Bit 0
Bit 7
Bit 0
Figure 8-8. TIM Counter Modulo Register Low (TMODL)

NOTE
Reset the TIM counter before writing to the TIM counter modulo registers.

116
I/O Registers
8.9.4 TIM Channel Status and Control Registers

Each of the TIM channel status and control registers:
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input capture trigger
Selects output toggling on TIM overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0035
Bit 7
Read:
CH0F
Write:
Reset:
Bit 0
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Figure 8-9. TIM Channel 0 Status and Control Register (TSC0)

Address: T1SC1, $0028 and T2SC1, $0038
Bit 7
Read:
CH1F
Write:
Reset:
6
CH1IE
0
5
0
0
Bit 0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Figure 8-10. TIM Channel 1 Status and Control Register (TSC1)

CHxF Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x
status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore,
an interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1
channel 0 and TIM2 channel 0 status and control registers.

117
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA Mode Select Bit A
When ELSxB:ELSxA 0:0, this read/write bit selects either input capture operation or unbuffered
output compare/PWM operation.
See Table 8-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. See
Table 8-3. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
ELSxB and ELSxA Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is
available as a general-purpose I/O pin. Table 8-3 shows how ELSxB and ELSxA work. Reset clears
the ELSxB and ELSxA bits.
Table 8-3. Mode, Edge, and Level Selection
MSxB:MSxA
ELSxB:ELSxA
Mode
Configuration
X0
00
X1
00
Pin under port control;

initial output level low
00
01
Capture on rising edge only
00
10
00
11
01
01
Pin under port control;

initial output level high
Output preset
01
10
01
11
1X
01
1X
10
1X
11
Input capture
Capture on falling edge only

Capture on rising or
falling edge
Toggle output on compare
Output compare
or PWM
Clear output on compare

Set output on compare
Buffered output
compare or
buffered PWM
Toggle output on compare

Clear output on compare
Set output on compare

118
I/O Registers
NOTE
Before enabling a TIM channel register for input capture operation, make
sure that the TCHx pin is stable for at least two bus clocks.
TOVx Toggle On Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect.
Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow
0 = Channel x pin does not toggle on TIM counter overflow
NOTE
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and
unbuffered PWM signals to 100%. As Figure 8-11 shows, the CHxMAX bit takes effect in the cycle
after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is
cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 8-11. CHxMAX Latency
8.9.5 TIM Channel Registers

These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.

119
Address: T1CH0H, $0026 and T2CH0H, $0036

Read:
Write:
Bit 7
Bit 0
Bit 15
14
13
12
11
10
Bit 8
Reset:
Figure 8-12. TIM Channel 0 Register High (TCH0H)

Address: T1CH0L, $0027 and T2CH0L $0037
Read:
Write:
Bit 7
Bit 0
Bit 7
Bit 0
Reset:
Figure 8-13. TIM Channel 0 Register Low (TCH0L)

Address: T1CH1H, $0029 and T2CH1H, $0039
Read:
Write:
Bit 7
Bit 0
Bit 15
14
13
12
11
10
Bit 8
Reset:
Figure 8-14. TIM Channel 1 Register High (TCH1H)

Address: T1CH1L, $002A and T2CH1L, $003A
Read:
Write:
Reset:
Bit 7
Bit 0
Bit 7
Bit 0
Figure 8-15. TIM Channel 1 Register Low (TCH1L)

120
Chapter 9
9.1 Introduction
This section describes the serial communications interface (SCI) module, which allows high-speed
asynchronous communications with peripheral devices and other MCUs.
9.2 Features
Features of the SCI module include the following:
Full-duplex operation
Standard mark/space non-return-to-zero (NRZ) format
32 programmable baud rates
Programmable 8-bit or 9-bit character length
Separately enabled transmitter and receiver
Separate receiver and transmitter CPU interrupt requests
Programmable transmitter output polarity
Two receiver wakeup methods:
Idle line wakeup
Address mark wakeup
Interrupt-driven operation with eight interrupt flags:
Transmitter empty
Transmission complete
Receiver full
Idle receiver input
Receiver overrun
Noise error
Framing error
Parity error
Receiver framing error detection
Hardware parity checking
1/16 bit-time noise detection
Bus clock as baud rate clock source
9.3 Pin Name Conventions

The generic names of the SCI I/O pins are:
RxD (receive data)
TxD (transmit data)
The SCI I/O (input/output) lines are dedicated pins for the SCI module. Table 9-1 shows the full names
and the generic names of the SCI I/O pins.
121
The generic pin names appear in the text of this section.

Generic Pin Names:
RxD
TxD
Full Pin Names:
PTD7/RxD
PTD6/TxD
INTERNAL BUS
SCI DATA
REGISTER
ERROR
INTERRUPT
CONTROL
RECEIVER
INTERRUPT
CONTROL
DMA
INTERRUPT
CONTROL
RECEIVE
SHIFT REGISTER
RxD
TRANSMITTER
INTERRUPT
CONTROL
SCI DATA
REGISTER
TRANSMIT
SHIFT REGISTER
TxD
TXINV
SCTIE
R8
TCIE
T8
SCRIE
ILIE
DMARE
TE
SCTE
RE
DMATE
TC
RWU
SBK
SCRF
OR
ORIE
IDLE
NF
NEIE
FE
FEIE
PE
PEIE
LOOPS
LOOPS
WAKEUP
CONTROL
FLAG
CONTROL
RECEIVE
CONTROL
ENSCI
ENSCI
TRANSMIT
CONTROL
BKF
RPF
WAKE
ILTY
BUS CLOCK
PRESCALER
BAUD
DIVIDER
16
PEN
PTY
DATA SELECTION
CONTROL
Figure 9-1. SCI Module Block Diagram

122
Addr.
$0013
$0014
$0015
Register Name
(SCC1)
(SCC2)
(SCC3)
$0018
SCI Data Register

(SCDR)
$0019
SCI Baud Rate Register

(SCBR)
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
Bit 0
LOOPS
ENSCI
TXINV
WAKE
ILTY
PEN
PTY
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
0
R8
T8
DMARE
DMATE
ORIE
NEIE
FEIE
PEIE
U
SCTE
U
TC
0
SCRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
BKF
0
RPF
0
R7
T7
0
R6
T6
0
R5
T5
0
R2
T2
0
R1
T1
0
R0
T0
SCR2
SCR1
SCR0
0
0
R4
R3
T4
T3
Unaffected by reset
SCP1
0
0
= Unimplemented
SCP0
0
R = Reserved
0
U = Unaffected
Figure 9-2. SCI I/O Register Summary

Figure 9-1 shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial
communication among the MCU and remote devices, including other MCUs. The transmitter and receiver
of the SCI operate independently, although they use the same baud rate generator. During normal
operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes
received data. The baud rate clock source for the SCI is the bus clock.
9.4.1 Data Format

The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 9-3.
8-BIT DATA FORMAT
BIT M IN SCC1 CLEAR
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
PARITY
BIT
BIT 6
BIT 7
9-BIT DATA FORMAT

BIT M IN SCC1 SET
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
STOP
BIT
NEXT
START
BIT
PARITY
BIT
BIT 6
BIT 7
BIT 8
STOP
BIT
NEXT
START
BIT
Figure 9-3. SCI Data Formats

123
9.4.2 Transmitter
Figure 9-4 shows the structure of the SCI transmitter.
The baud rate clock source for the SCI is the bus clock.
INTERNAL BUS
PRESCALER
BAUD
DIVIDER
16
SCI DATA REGISTER
SCP1
11-BIT
TRANSMIT
SHIFT REGISTER
STOP
SCP0
SCR1
SCR2
START
BUS CLOCK
TxD
MSB
TXINV
PARITY
GENERATION
T8
DMATE
DMATE
SCTIE
SCTE
DMATE
SCTE
SCTIE
TC
TCIE
BREAK
ALL 0s
PTY
PREAMBLE
ALL 1s
PEN
SHIFT ENABLE
M
LOAD FROM SCDR
TRANSMITTER DMA SERVICE REQUEST
TRANSMITTER CPU INTERRUPT REQUEST
SCR0
TRANSMITTER
CONTROL LOGIC
SCTE
SBK
LOOPS
SCTIE
ENSCI
TC
TE
TCIE
Figure 9-4. SCI Transmitter

9.4.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register
1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3
(SCC3) is the ninth bit (bit 8).
9.4.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character out to the TxD pin. The SCI data
register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To
initiate an SCI transmission:
124
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1).
2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in SCI control register
2 (SCC2).
3. Clear the SCI transmitter empty bit by first reading SCI status register 1 (SCS1) and then writing
to the SCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically loads the transmit shift register with
a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the
transmit shift register. A logic 1 stop bit goes into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the
transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data
bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a
transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic
1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and
receiver relinquish control of the port pin.
9.4.2.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break
character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character
length depends on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic continuously loads
break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes
transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the
end of a break character guarantees the recognition of the start bit of the next character.
The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a
logic 0 where the stop bit should be.
Receiving a break character has these effects on SCI registers:
Sets the framing error bit (FE) in SCS1
Sets the SCI receiver full bit (SCRF) in SCS1
Clears the SCI data register (SCDR)
Clears the R8 bit in SCC3
Sets the break flag bit (BKF) in SCS2
May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits
9.4.2.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends
on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission.
If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the character currently being transmitted.

125
NOTE
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current character shifts out to the TxD pin. Setting TE after the stop
bit appears on TxD causes data previously written to the SCDR to be lost.
Toggle the TE bit for a queued idle character when the SCTE bit becomes
set and just before writing the next byte to the SCDR.
9.4.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted
data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at logic
1. (See 9.8.1 SCI Control Register 1.)
9.4.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the SCI transmitter:
SCI transmitter empty (SCTE) The SCTE bit in SCS1 indicates that the SCDR has transferred
a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate
transmitter CPU interrupt requests.
Transmission complete (TC) The TC bit in SCS1 indicates that the transmit shift register and the
SCDR are empty and that no break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU
interrupt requests.
9.4.3 Receiver
Figure 9-5 shows the structure of the SCI receiver.
9.4.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1
(SCC1) determines character length. When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2)
is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7).
9.4.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data
register (SCDR) is the read-only buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of the character transfers
to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that
the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the
SCRF bit generates a receiver CPU interrupt request.

126
INTERNAL BUS
SCR1
SCR2
SCP0
SCR0
BAUD
DIVIDER
16
DATA
RECOVERY
RxD
CPU INTERRUPT REQUEST
11-BIT
RECEIVE SHIFT REGISTER
8
M
WAKE
ILTY
PEN
PTY
ALL 0s
RPF
ERROR CPU INTERRUPT REQUEST
DMA SERVICE REQUEST
ALL 1s
BKF
STOP
PRESCALER
MSB
BUS CLOCK
SCI DATA REGISTER
START
SCP1
SCRF
WAKEUP
LOGIC
PARITY
CHECKING
IDLE
ILIE
DMARE
SCRF
SCRIE
DMARE
SCRF
SCRIE
DMARE
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
RWU
IDLE
R8
ILIE
SCRIE
DMARE
OR
ORIE
NF
NEIE
FE
FEIE
PE
PEIE
Figure 9-5. SCI Receiver Block Diagram

127
9.4.3.3 Data Sampling

The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency
16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at the following
times (see Figure 9-6):
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three
logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
START BIT
LSB
START BIT
VERIFICATION
DATA
SAMPLING
RT8
START BIT
QUALIFICATION
SAMPLES
RT3
RxD
RT4
RT3
RT2
RT1
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT7
RT6
RT5
RT4
RT2
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT CLOCK
STATE
RT1
RT
CLOCK
RT CLOCK
RESET
Figure 9-6. Receiver Data Sampling

To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 9-2 summarizes the results of the start bit verification samples.
Table 9-2. Start Bit Verification
RT3, RT5, and RT7
Samples
Start Bit
Verification
Noise Flag
000
Yes
001
Yes
010
Yes
011
No
100
Yes
101
No
110
No
111
No
Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit
verification is not successful, the RT clock is reset and a new search for a start bit begins.
128
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and
RT10. Table 9-3 summarizes the results of the data bit samples.
Table 9-3. Data Bit Recovery
RT8, RT9, and RT10
Samples
Data Bit
Determination
Noise Flag
000
001
010
011
100
101
110
111
NOTE
The RT8, RT9, and RT10 samples do not affect start bit verification. If any
or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a
successful start bit verification, the noise flag (NF) is set and the receiver
assumes that the bit is a start bit.
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 9-4
summarizes the results of the stop bit samples.
Table 9-4. Stop Bit Recovery
RT8, RT9, and RT10
Samples
Framing
Error Flag
Noise Flag
000
001
010
011
100
101
110
111
9.4.3.4 Framing Errors

If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character,
it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character
has no stop bit. The FE bit is set at the same time that the SCRF bit is set.

129
9.4.3.5 Baud Rate Tolerance

A transmitting device may be operating at a baud rate below or above the receiver baud rate.
Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the
actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing
error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment
that is likely to occur.
As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge
within the character. Resynchronization within characters corrects misalignments between transmitter bit
times and receiver bit times.
Slow Data Tolerance
Figure 9-7 shows how much a slow received character can be misaligned without causing a noise error
or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
RT6
STOP
RT5
RT4
RT3
RT2
RECEIVER
RT CLOCK
RT1
MSB
DATA
SAMPLES
Figure 9-7. Slow Data

For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 9-7, the receiver counts 154 RT cycles at the point when
the count of the transmitting device is
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit
character with no errors is
154 147 100 = 4.54%
-------------------------154
For a 9-bit character, data sampling of the stop bit takes the receiver
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
170 163 100 = 4.12%
-------------------------170

130
Fast Data Tolerance

Figure 9-8 shows how much a fast received character can be misaligned without causing a noise error or
a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data
samples at RT8, RT9, and RT10.
RT16
RT15
RT14
RT13
RT12
RT11
RT10
RT9
RT8
RT7
IDLE OR NEXT CHARACTER
RT6
RT5
RT4
RT3
RT2
RECEIVER
RT CLOCK
RT1
STOP
DATA
SAMPLES
Figure 9-8. Fast Data

For an 8-bit character, data sampling of the stop bit takes the receiver
10 bit times 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
154 160 100 = 3.90%

-------------------------154
For a 9-bit character, data sampling of the stop bit takes the receiver
11 bit times 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
170 176 100 = 3.53%
-------------------------170
9.4.3.6 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems,
the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are disabled.
Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the
receiver out of the standby state:

131
Address mark An address mark is a logic 1 in the most significant bit position of a received
character. When the WAKE bit is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can
then compare the character containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and processes the characters that
follow. If they are not the same, software can set the RWU bit and put the receiver back into the
standby state.
Idle input line condition When the WAKE bit is clear, an idle character on the RxD pin wakes the
receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver
does not set the receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type bit,
ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start
bit or after the stop bit.
NOTE
With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.
9.4.3.7 Receiver Interrupts

The following sources can generate CPU interrupt requests from the SCI receiver:
SCI receiver full (SCRF) The SCRF bit in SCS1 indicates that the receive shift register has
transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting
the SCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver
CPU interrupts.
Idle input (IDLE) The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in
from the RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate
CPU interrupt requests.
9.4.3.8 Error Interrupts
The following receiver error flags in SCS1 can generate CPU interrupt requests:
Receiver overrun (OR) The OR bit indicates that the receive shift register shifted in a new
character before the previous character was read from the SCDR. The previous character remains
in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3
enables OR to generate SCI error CPU interrupt requests.
Noise flag (NF) The NF bit is set when the SCI detects noise on incoming data or break
characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3
enables NF to generate SCI error CPU interrupt requests.
Framing error (FE) The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects
a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error
CPU interrupt requests.
Parity error (PE) The PE bit in SCS1 is set when the SCI detects a parity error in incoming data.
The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt
requests.

132
Low-Power Modes
9.5 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
9.5.1 Wait Mode

The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.
If SCI module functions are not required during wait mode, reduce power consumption by disabling the
module before executing the WAIT instruction.
Refer to 5.6 Low-Power Modes for information on exiting wait mode.
9.5.2 Stop Mode

The SCI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect SCI register states. SCI module operation resumes after an external interrupt.
Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission
or reception results in invalid data.
Refer to 5.6 Low-Power Modes for information on exiting stop mode.
9.6 SCI During Break Module Interrupts

The system integration module (SIM) controls whether status bits in other modules can be cleared during
bits during the break state.
To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status
bit is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), software can read and write I/O registers during the break state without affecting status bits.
Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit
before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the
break, doing the second step clears the status bit.
9.7 I/O Signals

The two SCI I/O pins are:
PTD6/TxD Transmit data
PTD7/RxD Receive data
9.7.1 TxD (Transmit Data)

The PTD6/TxD pin is the serial data output from the SCI transmitter.
9.7.2 RxD (Receive Data)

The PTD7/RxD pin is the serial data input to the SCI receiver.
133
9.8 I/O Registers

These I/O registers control and monitor SCI operation:
SCI control register 1 (SCC1)
SCI status register 1 (SCS1)
SCI status register 2 (SCS2)
SCI data register (SCDR)
SCI baud rate register (SCBR)
9.8.1 SCI Control Register 1

SCI control register 1:
Enables loop mode operation
Enables the SCI
Controls output polarity
Controls character length
Controls SCI wakeup method
Controls idle character detection
Enables parity function
Controls parity type
Address:
Read:
Write:
Reset:
$0013
Bit 7
Bit 0
LOOPS
ENSCI
TXINV
WAKE
ILTY
PEN
PTY
Figure 9-9. SCI Control Register 1 (SCC1)

LOOPS Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the
SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must
be enabled to use loop mode. Reset clears the LOOPS bit.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI Enable SCI Bit
This read/write bit enables the SCI and the SCI baud rate generator. Clearing ENSCI sets the SCTE
and TC bits in SCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit.
1 = SCI enabled
0 = SCI disabled
TXINV Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE
Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
134
I/O Registers
M Mode (Character Length) Bit

This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 9-5.) The
ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the
M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE Wakeup Condition Bit
This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most
significant bit position of a received character or an idle condition on the RxD pin. Reset clears the
WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
ILTY Idle Line Type Bit
This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The counting
begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string
of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count
after the stop bit avoids false idle character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.
1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit
PEN Parity Enable Bit
This read/write bit enables the SCI parity function. (See Table 9-5.) When enabled, the parity function
inserts a parity bit in the most significant bit position. (See Figure 9-3.) Reset clears the PEN bit.
1 = Parity function enabled
0 = Parity function disabled
PTY Parity Bit
This read/write bit determines whether the SCI generates and checks for odd parity or even parity.
(See Table 9-5.) Reset clears the PTY bit.
1 = Odd parity
0 = Even parity
NOTE
Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 9-5. Character Format Selection
Control Bits
Character Format
PEN and PTY
Start
Bits
Data
Bits
Parity
Stop
Bits
Character
Length
0X
None
10 bits
0X
None
11 bits
10
Even
10 bits
11
Odd
10 bits
10
Even
11 bits
11
Odd
11 bits

135

Enables the following CPU interrupt requests:
Enables the SCTE bit to generate transmitter CPU interrupt requests
Enables the TC bit to generate transmitter CPU interrupt requests
Enables the SCRF bit to generate receiver CPU interrupt requests
Enables the IDLE bit to generate receiver CPU interrupt requests
Enables the transmitter
Enables the receiver
Enables SCI wakeup
Transmits SCI break characters
Address:
Read:
Write:
Reset:
$0014
Bit 7
Bit 0
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK

SCTIE SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset
clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears
the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE SCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Reset clears
the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears
the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests

136
I/O Registers
TE Transmitter Enable Bit

Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the
transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the TxD returns to the idle condition (logic 1). Clearing and then setting
TE during a transmission queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = Transmitter enabled
0 = Transmitter disabled
NOTE
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear.
ENSCI is in SCI control register 1.
RE Receiver Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not
affect receiver interrupt flag bits. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
NOTE
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
RWU Receiver Wakeup Bit
This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled.
The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out
of the standby state and clears the RWU bit. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK Send Break Bit
Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic
1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s between them. Reset clears the
SBK bit.
1 = Transmit break characters
0 = No break characters being transmitted
NOTE
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling
SBK before the preamble begins causes the SCI to send a break character
instead of a preamble.

137

Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted
Enables these interrupts:
Receiver overrun interrupts
Noise error interrupts
Framing error interrupts
Parity error interrupts
Address:
$0015
Bit 7
Read:
R8
Write:
Reset:
Bit 0
T8
DMARE
DMATE
ORIE
NEIE
FEIE
PEIE
= Unimplemented
U = Unaffected

R8 Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character.
R8 is received at the same time that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on
the R8 bit.
T8 Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted
character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
DMARE DMA Receive Enable Bit
CAUTION
The DMA module is not included on this MCU. Writing a logic 1 to DMARE
or DMATE may adversely affect MCU performance.
1 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI
receiver CPU interrupt requests enabled)
0 = DMA not enabled to service SCI receiver DMA service requests generated by the SCRF bit (SCI
receiver CPU interrupt requests enabled)
DMATE DMA Transfer Enable Bit
CAUTION
The DMA module is not included on this MCU. Writing a logic 1 to DMARE
or DMATE may adversely affect MCU performance.
1 = SCTE DMA service requests enabled; SCTE CPU interrupt requests disabled
0 = SCTE DMA service requests disabled; SCTE CPU interrupt requests enabled
ORIE Receiver Overrun Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR.
1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled
138
I/O Registers
NEIE Receiver Noise Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE.
Reset clears NEIE.
1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled
FEIE Receiver Framing Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE.
Reset clears FEIE.
1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled
PEIE Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI error CPU interrupt
requests generated by the parity error bit, PE.
(See 9.8.4 SCI Status Register 1.) Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
9.8.4 SCI Status Register 1

SCI status register 1 (SCS1) contains flags to signal these conditions:
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Parity error
Address:
$016
Bit 7
Bit 0
Read:
SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
Write:
Reset:
= Unimplemented
Figure 9-12. SCI Status Register 1 (SCS1)

SCTE SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register.
SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by
reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register

139
TC Transmission Complete Bit

This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being
transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set.
TC is automatically cleared when data, preamble or break is queued and ready to be sent. There may
be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the
transmission actually starting. Reset sets the TC bit.
1 = No transmission in progress
0 = Transmission in progress
SCRF SCI Receiver Full Bit
This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data
register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is
set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading
SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input.
IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE
bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must
receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after
the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition
can set the IDLE bit. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
OR Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the SCDR before the receive shift
register receives the next character. The OR bit generates an SCI error CPU interrupt request if the
ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is
not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears
the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing
sequence. Figure 9-13 shows the normal flag-clearing sequence and an example of an overrun
caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit
because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next
flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is important to know which byte is lost
due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after
reading the data register.
NF Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an SCI
error CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and
then reading the SCDR. Reset clears the NF bit.
1 = Noise detected
0 = No noise detected

140
I/O Registers
FE Receiver Framing Error Bit

This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error
CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
1 = Framing error detected
0 = No framing error detected
BYTE 1
BYTE 2
BYTE 3
SCRF = 0
SCRF = 1
SCRF = 0
SCRF = 1
SCRF = 0
SCRF = 1
NORMAL FLAG CLEARING SEQUENCE
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCDR
BYTE 2
READ SCDR
BYTE 3
BYTE 1
BYTE 2
BYTE 3
SCRF = 0
OR = 0
SCRF = 1
OR = 1
SCRF = 0
OR = 1
SCRF = 1
SCRF = 1
OR = 1
DELAYED FLAG CLEARING SEQUENCE
BYTE 4
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 9-13. Flag Clearing Sequence

PE Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates
an SCI error CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1
with PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected

141
9.8.5 SCI Status Register 2

SCI status register 2 contains flags to signal the following conditions:
Break character detected
Incoming data
Address:
$0017
Bit 7
Read:
Bit 0
BKF
RPF
Write:
Reset:
= Unimplemented
Figure 9-14. SCI Status Register 2 (SCS2)

BKF Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1,
the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF
does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading
the SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the RxD pin
followed by another break character. Reset clears the BKF bit.
1 = Break character detected
0 = No break character detected
RPF Reception in Progress Flag Bit
This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit
search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start
bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling
RPF before disabling the SCI module or entering stop mode can show whether a reception is in
progress.
1 = Reception in progress
0 = No reception in progress
9.8.6 SCI Data Register

The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the SCI data register.
Address:
$0018
Bit 7
Bit 0
Read:
R7
R6
R5
R4
R3
R2
R1
R0
Write:
T7
T6
T5
T4
T3
T2
T1
T0
Reset:
Unaffected by reset
Figure 9-15. SCI Data Register (SCDR)

R7/T7R0/T0 Receive/Transmit Data Bits
Reading the SCDR accesses the read-only received data bits, R[7:0]. Writing to the SCDR writes the
data to be transmitted, T[7:0]. Reset has no effect on the SCDR.
NOTE
Do not use read/modify/write instructions on the SCI data register.
142
I/O Registers
9.8.7 SCI Baud Rate Register

The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter.
Address:
Read:
$0019
Bit 7
Write:
Reset:
Bit 0
SCP1
SCP0
SCR2
SCR1
SCR0
= Reserved
= Unimplemented
Figure 9-16. SCI Baud Rate Register (SCBR)

SCP1 and SCP0 SCI Baud Rate Prescaler Bits
These read/write bits select the baud rate prescaler divisor as shown in Table 9-6. Reset clears SCP1
and SCP0.
Table 9-6. SCI Baud Rate Prescaling
SCP1 and SCP0
Prescaler Divisor (PD)
00
01
10
11
13
SCR2SCR0 SCI Baud Rate Select Bits

These read/write bits select the SCI baud rate divisor as shown in Table 9-7. Reset clears
SCR2SCR0.
Table 9-7. SCI Baud Rate Selection
SCR2, SCR1, and SCR0
Baud Rate Divisor (BD)
000
001
010
011
100
16
101
32
110
64
111
128
Use this formula to calculate the SCI baud rate:

SCI clock source
baud rate = --------------------------------------------64 PD BD
where:
SCI clock source = bus clock
PD = prescaler divisor
BD = baud rate divisor
Table 9-8 shows the SCI baud rates that can be generated with a 4.9152MHz bus clock.

143
Table 9-8. SCI Baud Rate Selection Examples

SCP1 and SCP0
Prescaler
Divisor (PD)
SCR2, SCR1,
and SCR0
Baud Rate
Divisor (BD)
Baud Rate
(BUS CLOCK=4.9152MHz)
00
000
76,800
00
001
38,400
00
010
19,200
00
011
9,600
00
100
16
4,800
00
101
32
2,400
00
110
64
1,200
00
111
128
600
01
000
25,600
01
001
12,800
01
010
6,400
01
011
3,200
01
100
16
1,600
01
101
32
800
01
110
64
400
01
111
128
200
10
000
19,200
10
001
9,600
10
010
4,800
10
011
2,400
10
100
16
1,200
10
101
32
600
10
110
64
300
10
111
128
150
11
13
000
5,908
11
13
001
2,954
11
13
010
1,477
11
13
011
739
11
13
100
16
369
11
13
101
32
185
11
13
110
64
92
11
13
111
128
46

144
Chapter 10
10.1 Introduction
This section describes the 13-channel, 8-bit linear successive approximation analog-to-digital converter
(ADC).
10.2 Features
Features of the ADC module include:
13 channels with multiplexed input
Linear successive approximation with monotonicity
8-bit resolution
Single or continuous conversion
Conversion complete flag or conversion complete interrupt
Addr.
$003C
$003D
$003E
Register Name
ADC Status and Control Read:
Register Write:
(ADSCR) Reset:
Read:
ADC Data Register
Write:
(ADR)
Reset:
Read:
ADC Input Clock Register
Write:
(ADICLK)
Reset:
Bit 7
COCO
0
AD7
Bit 0
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
0
AD6
0
AD5
1
AD4
1
AD3
1
AD2
1
AD1
1
AD0
ADIV2
ADIV1
ADIV0

0
0
0
Figure 10-1. ADC I/O Register Summary

Thirteen ADC channels are available for sampling external sources at pins PTB0PTB7, PTD0PTD3,
and ADC12/T2CLK. An analog multiplexer allows the single ADC converter to select one of the 13 ADC
channels as ADC voltage input (ADCVIN). ADCVIN is converted by the successive approximation
register-based counters. The ADC resolution is 8 bits. When the conversion is completed, ADC puts the
result in the ADC data register and sets a flag or generates an interrupt.
Figure 10-2 shows a block diagram of the ADC.

145

INTERNAL
DATA BUS
READ DDRB/DDRD
DISABLE
WRITE DDRB/DDRD
DDRBx/DDRDx
RESET
WRITE PTB/PTD
ADCx
PTBx/PTDx
READ PTB/PTD
DISABLE
ADC CHANNEL x
ADC DATA REGISTER
ADC0ADC11
CONVERSION
COMPLETE
INTERRUPT
LOGIC
AIEN
COCO
BUS CLOCK
ADC
ADC VOLTAGE IN
ADCVIN
ADC12
CHANNEL
SELECT
(1 OF 13 CHANNELS)
ADCH[4:0]
ADC CLOCK
CLOCK
GENERATOR
ADIV[2:0]
Figure 10-2. ADC Block Diagram
10.3.1 ADC Port I/O Pins

PTB0PTB7 and PTD0PTD3 are general-purpose I/O pins that are shared with the ADC channels. The
channel select bits (ADC status and control register, $003C), define which ADC channel/port pin will be
used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The
remaining ADC channels/port pins are controlled by the port I/O logic and can be used as
general-purpose I/O. Writes to the port register or DDR will not have any affect on the port pin that is
selected by the ADC. Read of a port pin which is in use by the ADC will return a logic 0 if the corresponding
DDR bit is at logic 0. If the DDR bit is at logic 1, the value in the port data latch is read.

146
Interrupts
10.3.2 Voltage Conversion

When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF (full scale). If the input
voltage equals VSS, the ADC converts it to $00. Input voltages between VDD and VSS are a straight-line
linear conversion. All other input voltages will result in $FF if greater than VDD and $00 if less than VSS.
NOTE
Input voltage should not exceed the analog supply voltages.
10.3.3 Conversion Time

Fourteen ADC internal clocks are required to perform one conversion. The ADC starts a conversion on
the first rising edge of the ADC internal clock immediately following a write to the ADSCR. If the ADC
internal clock is selected to run at 1MHz, then one conversion will take 14s to complete. With a 1MHz
ADC internal clock the maximum sample rate is 71.43kHz.
Conversion Time =
14 ADC Clock Cycles

ADC Clock Frequency
Number of Bus Cycles = Conversion Time Bus Frequency
10.3.4 Continuous Conversion

In the continuous conversion mode, the ADC continuously converts the selected channel filling the ADC
data register with new data after each conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The
COCO bit (ADC status and control register, $003C) is set after each conversion and can be cleared by
writing the ADC status and control register or reading of the ADC data register.
10.3.5 Accuracy and Precision

The conversion process is monotonic and has no missing codes.
10.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a
conversion complete flag when interrupts are enabled.
10.5 Low-Power Modes

The following subsections describe the ADC in low-power modes.
10.5.1 Wait Mode

The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting the ADCH[4:0] bits in the ADC status and control register to logic 1s before
executing the WAIT instruction.

147
10.5.2 Stop Mode

The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the
analog circuitry before attempting a new ADC conversion after exiting stop mode.
10.6 I/O Signals

The ADC module has 12 channels that are shared with I/O port B and port D, and one channel on
ADC12/T2CLK pin.
10.6.1 ADC Voltage In (ADCVIN)

ADCVIN is the input voltage signal from one of the 13 ADC channels to the ADC module.
10.7 I/O Registers

These I/O registers control and monitor ADC operation:
ADC status and control register (ADSCR)
ADC data register (ADR)
ADC clock register (ADICLK)
10.7.1 ADC Status and Control Register

The following paragraphs describe the function of the ADC status and control register.
Address:
$003C
Bit 7
Read:
COCO
Write:
Reset:
Bit 0
AIEN
ADCO
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
= Unimplemented
Figure 10-3. ADC Status and Control Register (ADSCR)

COCO Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is
completed. This bit is cleared whenever the ADC status and control register is written or whenever the
ADC data register is read. Reset clears this bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)
When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is a read-only bit, and will always
be logic 0 when read.
AIEN ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled

148
I/O Registers
ADCO ADC Continuous Conversion Bit

When set, the ADC will convert samples continuously and update the ADR register at the end of each
conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] ADC Channel Select Bits
ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels. The five channel select
bits are detailed in the following table. Care should be taken when using a port pin as both an analog
and a digital input simultaneously to prevent switching noise from corrupting the analog signal. (See
Table 10-1.)
The ADC subsystem is turned off when the channel select bits are all set to one. This feature allows
for reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to
a logic 1.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
Table 10-1. MUX Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
ADC Channel
Input Select
ADC0
PTB0
ADC1
PTB1
ADC2
PTB2
ADC3
PTB3
ADC4
PTB4
ADC5
PTB5
ADC6
PTB6
ADC7
PTB7
ADC8
PTD3
ADC9
PTD2
ADC10
PTD1
ADC11
PTD0
ADC12
ADC12/T2CLK
Unused(1)
Reserved
Reserved
VDD(2)
VSS(2)
ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the
operation of the ADC converter both in production test and for user applications.

149
10.7.2 ADC Data Register

One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address:
Read:
$003D
Bit 7
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset:

= Unimplemented
Figure 10-4. ADC Data Register (ADR)
10.7.3 ADC Input Clock Register

This register selects the clock frequency for the ADC.
Address:
$003E
Bit 7
Read:
Write:
Reset:
ADIV2
ADIV1
ADIV0
Bit 0
= Unimplemented
Figure 10-5. ADC Input Clock Register (ADICLK)

ADIV[2:0] ADC Clock Prescaler Bits
ADIV[2:0] form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC
clock. Table 10-2 shows the available clock configurations. The ADC clock should be set to
approximately 1MHz.
Table 10-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
Bus Clock 1
Bus Clock 2
Bus Clock 4
Bus Clock 8
Bus Clock 16
X = dont care

150
Chapter 11
11.1 Introduction
Twenty six (26) bidirectional input-output (I/O) pins form four parallel ports. All I/O pins are programmable
as inputs or outputs.
NOTE
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
Addr.
$0000
$0001
$0003
$0004
$0005
$0007
$0008
Register Name
Port A Data Register (PTA)
Port B Data Register (PTB)
Port D Data Register (PTD)

Data Direction Register A
(DDRA)
Data Direction Register B
(DDRB)
Data Direction Register D
(DDRD)
Port E Data Register
(PTE)
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
$000A
Read:
Port D Control Register
Write:
(PDCR)
Reset:
$000C
Read:
Data Direction Register E
Write:
(DDRE)
Reset:
Bit 7
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
PTB2
PTB1
PTB0
PTD2
PTD1
PTD0
Unaffected by reset
PTB7
PTB6
PTB5
PTB4
PTB3
Unaffected by reset
PTD7
PTD6
PTD5
PTD4
PTD3
Unaffected by reset
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
PTE1
PTE0
Unaffected by reset
SLOWD7 SLOWD6 PTDPU7

0
PTDPU6
DDRE1
DDRE0
Figure 11-1. I/O Port Register Summary

151

Addr.
$000D
$000E
Register Name
Bit 7
Read:
Port A Input Pull-up Enable
PTA6EN
Register Write:
(PTAPUE) Reset:
0
Read:
PTA7 Input Pull-up
PTAPUE7
(PTA7PUE) Reset:
0
Bit 0
PTAPUE6
PTAPUE5
PTAPUE4
PTAPUE3
PTAPUE2
PTAPUE1
PTAPUE0
Figure 11-1. I/O Port Register Summary
Table 11-1. Port Control Register Bits Summary

Port
Module Control
Bit
DDR
DDRA0
KBIE0
PTA0/KBI0
DDRA1
KBIE1
PTA1/KBI1
DDRA2
KBIE2
PTA2/KBI2
DDRA3
KBIE3
PTA3/KBI3
DDRA4
KBIE4
PTA4/KBI4
DDRA5
KBIE5
PTA5/KBI5
DDRA6
OSC
KBI
PTAPUE ($000D)
KBIER ($001B)
PTA6EN
KBIE6
RCCLK/PTA6/KBI6(1)
DDRA7
KBI
KBIER ($001B)
KBIE7
PTA7/KBI7
DDRB0
PTB0/ADC0
DDRB1
PTB1/ADC1
DDRB2
PTB2/ADC2
DDRB3
DDRB4
DDRB5
PTB5/ADC5
DDRB6
PTB6/ADC6
DDRB7
PTB7/ADC7
DDRD0
PTD0/ADC11
DDRD1
DDRD2
DDRD3
DDRD4
DDRD5
DDRD6
DDRD7
DDRE0
DDRE1
Module
KBI
ADC
ADC
Register
KBIER ($001B)
ADSCR ($003C)
ADSCR ($003C)
Pin
Control Bit
PTB3/ADC3
ADCH[4:0]
PTB4/ADC4
PTD1/ADC10
ADCH[4:0]
PTD2/ADC9
PTD3/ADC8
TIM1
SCI
TIM2
T1SC0 ($0025)
ELS0B:ELS0A
PTD4/T1CH0
T1SC1 ($0028)
ELS1B:ELS1A
PTD5/T1CH1
SCC1 ($0013)
ENSCI
T2SC0 ($0035)
ELS0B:ELS0A
PTE0/T2CH0
T2SC1 ($0038)
ELS1B:ELS1A
PTE1/T2CH1
PTD6/TxD
PTD7/RxD
1. RCCLK/PTA6/KBI6 pin is only available when OSCSEL=0 (RC option);

PTAPUE register has priority control over the port pin.
RCCLK/PTA6/KBI6 is the OSC2 pin when OSCSEL=1 (XTAL option).

152
Port A
11.2 Port A
Port A is an 8-bit special function port that shares all of its pins with the keyboard interrupt (KBI) module
(see Chapter 13 Keyboard Interrupt Module (KBI)). Each port A pin also has software configurable pull-up
device if the corresponding port pin is configured as input port. PTA0PTA5 and PTA7 has direct LED
drive capability.
NOTE
PTA0PTA5 pins are available on 28-pin and 32-pin packages only.
PTA7 pin is available on 32-pin packages only.
11.2.1 Port A Data Register (PTA)

The port A data register (PTA) contains a data latch for each of the eight port A pins.
Address:
Read:
Write:
$0000
Bit 7
Bit 0
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Reset:
Additional Functions:
Alternative Functions:
Unaffected by Reset
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
Keyboard
Interrupt
Keyboard
Interrupt
Keyboard
Interrupt
Keyboard
Interrupt
Keyboard
Interrupt
Keyboard
Interrupt
Keyboard
Interrupt
Keyboard
Interrupt
Figure 11-2. Port A Data Register (PTA)

PTA[7:0] Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
KBI7KBI0 Port A Keyboard Interrupts
The keyboard interrupt enable bits, KBIE[7:0], in the keyboard interrupt control register (KBIER) enable
the port A pins as external interrupt pins, (see Chapter 13 Keyboard Interrupt Module (KBI)).
11.2.2 Data Direction Register A (DDRA)

Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to
a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.
NOTE
For those devices packaged in a 28-pin package, PTA7 is not connected.
DDRA7 should be set to a 1 to configure PTA7 as an output.
For those devices packaged in a 20-pin package, PTA0PTA5 and PTA7
are not connected. DDRA0DDRA5 and DDRA7 should be set to a 1 to
configure PTA0PTA5 and PTA7 as outputs.

153

Address:
Read:
Write:
$0004
Bit 7
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Reset:
Figure 11-3. Data Direction Register A (DDRA)

DDRA[7:0] Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 11-4 shows the port A I/O logic.
READ DDRA ($0004)
PTAPUEx
INTERNAL DATA BUS
WRITE DDRA ($0004)

DDRAx
RESET
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)

To KBI
Figure 11-4. Port A I/O Circuit

When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Table 11-2 summarizes the operation of the port A pins.
Table 11-2. Port A Pin Functions
PTAPUE
Bit
DDRA Bit
PTA Bit
X(1)
I/O Pin Mode
Accesses to DDRA
Accesses to PTA
Read/Write
Read
Write
VDD(2)
DDRA[7:0]
Pin
PTA[7:0](3)
Input, Hi-Z(4)
DDRA[7:0]
Pin
PTA[7:0](3)
Output
DDRA[7:0]
PTA[7:0]
PTA[7:0]
Input,
1. X = Dont care.
2. Pin pulled to VDD by internal pull-up.
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance.

154
Port A
11.2.3 Port A Input Pull-Up Enable Registers

The port A input pull-up enable registers contain a software configurable pull-up device for each of the
eight port A pins. Each bit is individually configurable and requires the corresponding data direction
register, DDRAx be configured as input. Each pull-up device is automatically disabled when its
corresponding DDRAx bit is configured as output.
Address:
$000D
Read:
Write:
Reset:
Bit 7
Bit 0
PTA6EN
PTAPUE6
PTAPUE5
PTAPUE4
PTAPUE3
PTAPUE2
PTAPUE1
PTAPUE0
Figure 11-5. Port A Input Pull-up Enable Register (PTAPUE)

Address:
$000E
Bit 7
Read:
Write:
Reset:
Bit 0
PTAPUE7
0
Figure 11-6. PTA7 Input Pull-up Enable Register (PTA7PUE)

PTA6EN Enable PTA6 on OSC2
This read/write bit configures the OSC2 pin function when RC oscillator option is selected. This bit has
no effect for XTAL oscillator option.
1 = OSC2 pin configured for PTA6 I/O, and has all the interrupt and pull-up functions
0 = OSC2 pin outputs the RC oscillator clock (RCCLK)
PTAPUE[7:0] Port A Input Pull-up Enable Bits
These read/write bits are software programmable to enable pull-up devices on port A pins.
1 = Corresponding port A pin configured to have internal pull-up if its DDRA bit is set to 0
0 = Pull-up device is disconnected on the corresponding port A pin regardless of the state of its
DDRA bit

155
11.3 Port B
Port B is an 8-bit special function port that shares all of its port pins with the analog-to-digital converter
(ADC) module, see Chapter 10
11.3.1 Port B Data Register (PTB)

The port B data register contains a data latch for each of the eight port B pins.
Address:
$0001
Read:
Write:
Bit 7
Bit 0
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
ADC7
ADC6
ADC5
ADC2
ADC2
ADC0
Reset:
Unaffected by reset
ADC4
ADC3
Figure 11-7. Port B Data Register (PTB)

PTB[7:0] Port B Data Bits
These read/write bits are software programmable. Data direction of each port B pin is under the control
of the corresponding bit in data direction register B. Reset has no effect on port B data.
ADC7ADC0 ADC channels 7 to 0
ADC7ADC0 are pins used for the input channels to the analog-to-digital converter module. The
channel select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used
as an ADC input and overrides any control from the port I/O logic. See Chapter 10 Analog-to-Digital
Converter (ADC).
11.3.2 Data Direction Register B (DDRB)

Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to
a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0005
Bit 7
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
Figure 11-8. Data Direction Register B (DDRB)

DDRB[7:0] Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 11-9 shows the
port B I/O logic.

156
Port D
READ DDRB ($0005)
INTERNAL DATA BUS
WRITE DDRB ($0005)

RESET
DDRBx
WRITE PTB ($0001)

PTBx
PTBx
READ PTB ($0001)
To Analog-To-Digital Converter
Figure 11-9. Port B I/O Circuit

When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0,
regardless of the state of its data direction bit. Table 11-3 summarizes the operation of the port B pins.
Table 11-3. Port B Pin Functions
Accesses to DDRB
DDRB Bit
PTB Bit
Accesses to PTB
I/O Pin Mode

Read/Write
Read
Write
X(1)
Input, Hi-Z(2)
DDRB[7:0]
Pin
PTB[7:0](3)
Output
DDRB[7:0]
PTB[7:0]
PTB[7:0]
1. X = dont care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect the input.
11.4 Port D
Port D is an 8-bit special function port that shares two of its pins with the serial communications interface
module (see Chapter 9), two of its pins with the timer 1 interface module, (see Chapter 8), and four of its
pins with the analog-to-digital converter module (see Chapter 10). PTD6 and PTD7 each has high current
sink (25mA) and programmable pull-up. PTD2, PTD3, PTD6 and PTD7 each has LED sink capability.
NOTE
PTD0PTD1 are available on 28-pin and 32-pin packages only.

157
11.4.1 Port D Data Register (PTD)

The port D data register contains a data latch for each of the eight port D pins.
Address:
Read:
Write:
$0003
Bit 7
Bit 0
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
ADC10
ADC11
Reset:
Additional Functions
Unaffected by reset
LED
(Sink)
LED
(Sink)
LED
(Sink)
LED
(Sink)
ADC8
ADC9
25mA sink
25mA sink
(Slow Edge) (Slow Edge)
pull-up
pull-up
RxD
TxD
T1CH1
T1CH0
Figure 11-10. Port D Data Register (PTD)

PTD[7:0] Port D Data Bits
These read/write bits are software programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
ADC11ADC8 ADC channels 11 to 8
ADC[11:8] are pins used for the input channels to the analog-to-digital converter module. The channel
select bits, ADCH[4:0], in the ADC status and control register define which port pin will be used as an
ADC input and overrides any control from the port I/O logic. See Chapter 10 Analog-to-Digital
Converter (ADC).
T1CH1, T1CH0 Timer 1 Channel I/Os
The T1CH1 and T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select
bits, ELSxB:ELSxA, determine whether the PTD4/T1CH0 and PTD5/T1CH1 pins are timer channel I/O
pins or general-purpose I/O pins. See Chapter 8 Timer Interface Module (TIM).
TxD, RxD SCI Data I/O Pins
The TxD and RxD pins are the transmit data output and receive data input for the SCI module. The
enable SCI bit, ENSCI, in the SCI control register 1 enables the PTD6/TxD and PTD7/RxD pins as SCI
TxD and RxD pins and overrides any control from the port I/O logic. See Chapter 9 Serial
Communications Interface (SCI).
11.4.2 Data Direction Register D (DDRD)

Data direction register D determines whether each port D pin is an input or an output. Writing a logic 1 to
a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
NOTE
For those devices packaged in a 20-pin package, PTD0PTD1 and are not connected. DDRD0DDRD1
should be set to a 1 to configure PTD0PTD1 as outputs.

158
Port D
Address:
$0007
Read:
Write:
Reset:
Bit 7
Bit 0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
Figure 11-11. Data Direction Register D (DDRD)

DDRD[7:0] Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1. Figure 11-12 shows the
port D I/O logic.
READ DDRD ($0007)
PTDPU[6:7]
INTERNAL DATA BUS
WRITE DDRD ($0007)

RESET
DDRDx
WRITE PTD ($0003)

PTDx
PTDx
READ PTD ($0003)
To ADC, TIM1, SCI
Figure 11-12. Port D I/O Circuit

When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0,
regardless of the state of its data direction bit. Table 11-4 summarizes the operation of the port D pins.
Table 11-4. Port D Pin Functions
Accesses to DDRD
Accesses to PTD
DDRD Bit
PTD Bit
I/O Pin Mode
Read/Write
Read
Write
X(1)
Input, Hi-Z(2)
DDRD[7:0]
Pin
PTD[7:0](3)
Output
DDRD[7:0]
PTD[7:0]
PTD[7:0]
1. X = dont care.

159
11.4.3 Port D Control Register (PDCR)

The port D control register enables/disables the pull-up resistor and slow-edge high current capability of
pins PTD6 and PTD7.
Address:
$000A
Bit 7
Read:
Write:
Reset:
Bit 0
SLOWD7
SLOWD6
PTDPU7
PTDPU6
Figure 11-13. Port D Control Register (PDCR)

SLOWDx Slow Edge Enable
The SLOWD6 and SLOWD7 bits enable the slow-edge, open-drain, high current output (25mA sink)
of port pins PTD6 and PTD7 respectively. DDRDx bit is not affected by SLOWDx.
1 = Slow edge enabled; pin is open-drain output
0 = Slow edge disabled; pin is push-pull (standard I/O)
PTDPUx Port D Pull-up Enable Bits
The PTDPU6 and PTDPU7 bits enable the pull-up device on PTD6 and PTD7 respectively, regardless
the status of DDRDx bit.
1 = Enable pull-up device
0 = Disable pull-up device
11.5 Port E
Port E is a 2-bit special function port that shares its pins with the timer 2 interface module (see Chapter 8).
NOTE
PTE0PTE1 are available on 32-pin packages only.
11.5.1 Port E Data Register (PTE)

The port E data register contains a data latch for each of the two port E pins.
Address:
$0008
Bit 7
Read:
Write:
Reset:
Bit 0
PTE1
PTE0
T2CH1
T2CH0
Unaffected by reset
Figure 11-14. Port E Data Register (PTE)

PTE[1:0] Port E Data Bits
These read/write bits are software programmable. Data direction of each port E pin is under the control
of the corresponding bit in data direction register E. Reset has no effect on port D data.

160
Port E
T2CH1, T2CH0 Timer 2 Channel I/Os

The T2CH1 and T2CH0 pins are the TIM2 input capture/output compare pins. The edge/level select
bits, ELSxB:ELSxA, determine whether the PTE0/T2CH0 and PTE1/T2CH1 pins are timer channel I/O
pins or general-purpose I/O pins. See Chapter 8 Timer Interface Module (TIM).
11.5.2 Data Direction Register E (DDRE)

Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to
a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer.
NOTE
For those devices packaged in a 20-pin package and 28-pin package, PTE0PTE1 are not connected.
DDRE0DDRE1 should be set to a 1 to configure PTE0PTE1 as outputs.
Address:
$000C
Bit 7
Read:
Write:
Reset:
Bit 0
DDRE1
DDRE0
Figure 11-15. Data Direction Register E (DDRE)

DDRE[1:0] Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears DDRE[1:0], configuring all port E pins
as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
NOTE
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1. Figure 11-16 shows the
port E I/O logic.
READ DDRE ($000C)
INTERNAL DATA BUS
WRITE DDRE ($000C)

RESET
DDREx
WRITE PTE ($0008)

PTEx
PTEx
READ PTE ($0008)
To TIM2
Figure 11-16. Port E I/O Circuit

161
When DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When DDREx is a logic 0,
regardless of the state of its data direction bit. Table 11-5 summarizes the operation of the port E pins.
Table 11-5. Port E Pin Functions
Accesses to DDRE
DDRE Bit
PTE Bit
Accesses to PTE
I/O Pin Mode

Read/Write
Read
Write
X(1)
Input, Hi-Z(2)
DDRE[1:0]
Pin
PTE[1:0](3)
Output
DDRE[1:0]
PTE[1:0]
PTE[1:0]
1. X = dont care.

162
Chapter 12
12.1 Introduction
The external interrupt (IRQ) module provides a maskable interrupt input.
12.2 Features
Features of the IRQ module include the following:
A dedicated external interrupt pin (IRQ)
IRQ interrupt control bits
Hysteresis buffer
Programmable edge-only or edge and level interrupt sensitivity
Automatic interrupt acknowledge
Selectable internal pullup resistor

A logic zero applied to the external interrupt pin can latch a CPU interrupt request. Figure 12-1 shows the
structure of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of
the following actions occurs:
Vector fetch A vector fetch automatically generates an interrupt acknowledge signal that clears
the IRQ latch.
Software clear Software can clear the interrupt latch by writing to the acknowledge bit in the
interrupt status and control register (INTSCR). Writing a logic one to the ACK bit clears the IRQ
latch.
Reset A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge
or falling-edge and low-level-triggered. The MODE bit in the INTSCR controls the triggering sensitivity of
the IRQ pin.
When the interrupt pin is edge-triggered only, the CPU interrupt request remains set until a vector fetch,
software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set
until both of the following occur:
Vector fetch or software clear
Return of the interrupt pin to logic one

163
The vector fetch or software clear may occur before or after the interrupt pin returns to logic one. As long
as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control
bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. (See 5.5 Exception
Control.)
RESET
INTERNAL ADDRESS BUS
ACK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
IRQPUD
INTERNAL
PULLUP
DEVICE
VDD
IRQF
D
CLR
IRQ
INTERRUPT
REQUEST
SYNCHRONIZER
CK
IRQ
IMASK
MODE
TO MODE
SELECT
LOGIC
HIGH
VOLTAGE
DETECT
Figure 12-1. IRQ Module Block Diagram

Addr.
$001D
Register Name
IRQ Status and Control Read:
Register Write:
(INTSCR) Reset:
Bit 7
0
0
6
0
5
0
4
0
3
IRQF
0
0
= Unimplemented
2
0
ACK
0
Bit 0
IMASK
MODE
Figure 12-2. IRQ I/O Register Summary
12.3.1 IRQ Pin

A logic zero on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear,
or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set,
both of the following actions must occur to clear IRQ:

164
IRQ Module During Break Interrupts
Vector fetch or software clear A vector fetch generates an interrupt acknowledge signal to clear
the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the ACK
bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that
poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does
not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK
bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the
program counter with the vector address at locations $FFFA and $FFFB.
Return of the IRQ pin to logic one As long as the IRQ pin is at logic zero, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to logic one may occur in any order. The
interrupt request remains pending as long as the IRQ pin is at logic zero. A reset will clear the latch and
the MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or
software clear immediately clears the IRQ latch.
The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not
affected by the IMASK bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
NOTE
An internal pull-up resistor to VDD is connected to the IRQ pin; this can be
disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).
12.4 IRQ Module During Break Interrupts

The system integration module (SIM) controls whether the IRQ latch can be cleared during the break
state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during
the break state. (See Chapter 5 System Integration Module (SIM).)
To allow software to clear the IRQ latch during a break interrupt, write a logic one to the BCFE bit. If a
latch is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic zero to the BCFE bit. With BCFE at logic zero
(its default state), writing to the ACK bit in the IRQ status and control register during the break state has
no effect on the IRQ latch.

165
12.5 IRQ Status and Control Register (INTSCR)

The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The
INTSCR has the following functions:
Shows the state of the IRQ flag
Clears the IRQ latch
Masks IRQ and interrupt request
Controls triggering sensitivity of the IRQ interrupt pin
Address:
Read:
$001D
Bit 7
IRQF
Write:
Reset:
2
ACK
Bit 0
IMASK
MODE
= Unimplemented
Figure 12-3. IRQ Status and Control Register (INTSCR)

IRQF IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK IRQ Interrupt Request Acknowledge Bit
Writing a logic one to this write-only bit clears the IRQ latch. ACK always reads as logic zero. Reset
clears ACK.
IMASK IRQ Interrupt Mask Bit
Writing a logic one to this read/write bit disables IRQ interrupt requests. Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
Address:
$001E
Bit 7
Bit 0
IRQPUD
LVIT1
LVIT0
Reset:
Not affected
Not affected
POR:
= Reserved
Read:
Write:

IRQPUD IRQ Pin Pull-Up Disable Bit
IRQPUD disconnects the internal pull-up on the IRQ pin.
1 = Internal pull-up is disconnected
0 = Internal pull-up is connected between IRQ pin and VDD
166
Chapter 13
13.1 Introduction
The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are
accessible via PTA0PTA7. When a port pin is enabled for keyboard interrupt function, an internal pull-up
device is also enabled on the pin.
13.2 Features
Features of the keyboard interrupt module include the following:
Eight keyboard interrupt pins with pull-up devices
Separate keyboard interrupt enable bits and one keyboard interrupt mask
Programmable edge-only or edge- and level- interrupt sensitivity
Exit from low-power modes
Addr.
$001A
$001B
Register Name
Keyboard Status and Read:
Control Register Write:
(KBSCR) Reset:
Keyboard Interrupt Read:
(KBIER) Reset:
Bit 7
0
6
0
5
0
4
0
3
KEYF
KBIE7
KBIE6
KBIE5
0
0
= Unimplemented
Bit 0
IMASKK
MODEK
2
0
ACKK
0
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
Figure 13-1. KBI I/O Register Summary
13.3 I/O Pins

The eight keyboard interrupt pins are shared with standard port I/O pins. The full name of the KBI pins
are listed in Table 13-1. The generic pin name appear in the text that follows.
KBI
Generic Pin Name
Full MCU Pin Name
Pin Selected for KBI Function by KBIEx

Bit in KBIER
KBI0KBI5
PTA0/KBI0PTA5/KBI5
KBIE0KBIE5
KBI6
OSC2/RCCLK/PTA6/KBI6(1)
KBIE6
KBI7
PTA7/KBI7
KBIE7
1. PTA6/KBI6 is only available when OSCSEL=0 at $FFD0 (RC option), and PTA6EN=1 at $000D.

167

INTERNAL BUS
NOTE:
To prevent false interrupts, user should use software
to debounce keyboard interrupt inputs.
KBI0
ACKK
VDD
VECTOR FETCH
DECODER
KEYF
RESET
.
KBIE0
CLR
Q
SYNCHRONIZER
CK
TO PULLUP ENABLE
.
KEYBOARD
INTERRUPT FF
KBI7
KEYBOARD
INTERRUPT
REQUEST
IMASKK
MODEK
KBIE7
TO PULLUP ENABLE
Figure 13-2. Keyboard Interrupt Block Diagram

Writing to the KBIE7KBIE0 bits in the keyboard interrupt enable register independently enables or
disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port A also
enables its internal pull-up device regardless of PTAPUEx bits in the port A input pull-up enable register
(see 11.2.3 Port A Input Pull-Up Enable Registers). A logic 0 applied to an enabled keyboard interrupt pin
latches a keyboard interrupt request.
A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK
bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt.
If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an
interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on
one pin because another pin is still low, software can disable the latter pin while it is low.
If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as
long as any keyboard pin is low.
If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both
of the following actions must occur to clear a keyboard interrupt request:
Vector fetch or software clear A vector fetch generates an interrupt acknowledge signal to clear
the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1
to the ACKK bit in the keyboard status and control register KBSCR. The ACKK bit is useful in
applications that poll the keyboard interrupt pins and require software to clear the keyboard
interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also
prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on
the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another
interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program
counter with the vector address at locations $FFE0 and $FFE1.
Return of all enabled keyboard interrupt pins to logic 1 As long as any enabled keyboard
interrupt pin is at logic 0, the keyboard interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur
in any order.
168
Keyboard Interrupt Registers
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a
vector fetch or software clear immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a
keyboard interrupt pin stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending
interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes
it useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, disable the pull-up device, use the data direction
register to configure the pin as an input and then read the data register.
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a logic 0 for software to
read the pin.
13.4.1 Keyboard Initialization

When a keyboard interrupt pin is enabled, it takes time for the internal pull-up to reach a logic 1. Therefore
a false interrupt can occur as soon as the pin is enabled.
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An
interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction
register A.
2. Write logic 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
13.5 Keyboard Interrupt Registers

Two registers control the operation of the keyboard interrupt module:
Keyboard status and control register
Keyboard interrupt enable register
13.5.1 Keyboard Status and Control Register
Flags keyboard interrupt requests

Acknowledges keyboard interrupt requests
Masks keyboard interrupt requests
Controls keyboard interrupt triggering sensitivity
169
Address: $001A
Read:
Bit 7
KEYF
Write:
Reset:
ACKK
0
Bit 0
IMASKK
MODEK
= Unimplemented
Figure 13-3. Keyboard Status and Control Register (KBSCR)

KEYF Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on port A. Reset clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt request on port A. ACKK always
reads as logic 0. Reset clears ACKK.
IMASKK Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from
generating interrupt requests on port A. Reset clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port A. Reset
clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
13.5.2 Keyboard Interrupt Enable Register

The port-A keyboard interrupt enable register enables or disables each port-A pin to operate as a
keyboard interrupt pin
Address:
Read:
Write:
Reset:
$001B
Bit 7
Bit 0
KBIE7
KBIE6
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
Figure 13-4. Keyboard Interrupt Enable Register (KBIER)

KBIE7KBIE0 Port-A Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard interrupt pin on port-A to latch
interrupt requests. Reset clears the keyboard interrupt enable register.
1 = KBIx pin enabled as keyboard interrupt pin
0 = KBIx pin not enabled as keyboard interrupt pin

170
Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
13.6.1 Wait Mode

The keyboard modules remain active in wait mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of wait mode.
13.6.2 Stop Mode

The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and
control register enables keyboard interrupt requests to bring the MCU out of stop mode.
13.7 Keyboard Module During Break Interrupts

The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during
bits during the break state.
To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE
bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default
state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during
the break state has no effect.

171

172
Chapter 14
14.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the
CONFIG1 register.

Figure 14-1 shows the structure of the COP module.
SIM
RESET VECTOR FETCH
RESET STATUS REGISTER
COP TIMEOUT
CLEAR STAGES 512
CLEAR ALL STAGES
INTERNAL RESET SOURCES(1)
SIM RESET CIRCUIT
12-BIT SIM COUNTER
ICLK
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COPD (FROM CONFIG1)
RESET
COPCTL WRITE
CLEAR
COP COUNTER
COP RATE SEL

(COPRS FROM CONFIG1)
NOTE: See SIM section for more details.
Figure 14-1. COP Block Diagram

173
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM)
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after
218 24 or 213 24 ICLK cycles; depending on the state of the COP rate select bit, COPRS, in
configuration register 1. Writing any value to location $FFFF before an overflow occurs prevents a COP
reset by clearing the COP counter and stages 12 through 5 of the SIM counter.
NOTE
Service the COP immediately after reset and before entering or after exiting
stop mode to guarantee the maximum time before the first COP counter
overflow.
A COP reset pulls the RST pin low for 32 ICLK cycles and sets the COP bit in the reset status register
(RSR). (See 5.7.2 Reset Status Register (RSR).).
NOTE
Place COP clearing instructions in the main program and not in an interrupt
subroutine. Such an interrupt subroutine could keep the COP from
generating a reset even while the main program is not working properly.
14.3 I/O Signals

The following paragraphs describe the signals shown in Figure 14-1.
14.3.1 ICLK
ICLK is the internal oscillator output signal, typically 50-kHz. The ICLK frequency varies depending on the
supply voltage. See Chapter 17 Electrical Specifications for ICLK parameters.
14.3.2 COPCTL Write

Writing any value to the COP control register (COPCTL) (see 14.4 COP Control Register) clears the
COP counter and clears bits 12 through 5 of the SIM counter. Reading the COP control register returns
the low byte of the reset vector.
14.3.3 Power-On Reset

The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 ICLK cycles after power-up.
14.3.4 Internal Reset

An internal reset clears the SIM counter and the COP counter.
14.3.5 Reset Vector Fetch

A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears
the SIM counter.
14.3.6 COPD (COP Disable)

The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register 1
(CONFIG1). (See Chapter 3 Configuration and Mask Option Registers (CONFIG & MOR).)

174
COP Control Register
14.3.7 COPRS (COP Rate Select)

The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1.
Address:
Read:
Write:
Reset:
$001F
Bit 7
Bit 0
COPRS
LVID
SSREC
STOP
COPD
= Reserved

COPRS COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
COPD COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
14.4 COP Control Register

The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address:
$FFFF
Bit 7
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
Bit 0
Figure 14-3. COP Control Register (COPCTL)
14.5 Interrupts
The COP does not generate CPU interrupt requests.
14.6 Monitor Mode

The COP is disabled in monitor mode when VTST is present on the IRQ pin or on the RST pin.

The WAIT and STOP instructions put the MCU in low-power consumption standby modes.

175
14.7.1 Wait Mode

The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically
clear the COP counter in a CPU interrupt routine.
14.7.2 Stop Mode

Stop mode turns off the ICLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available
that disables the STOP instruction. When the STOP bit in the configuration register has the STOP
instruction is disabled, execution of a STOP instruction results in an illegal opcode reset.
14.8 COP Module During Break Mode

The COP is disabled during a break interrupt when VTST is present on the RST pin.

176
Chapter 15
15.1 Introduction
This section describes the low-voltage inhibit module (LVI), which monitors the voltage on the VDD pin
and generates a reset when the VDD voltage falls to the LVI trip (LVITRIP) voltage.
15.2 Features
Features of the LVI module include the following:
Selectable LVI trip voltage
Selectable LVI circuit disable

Figure 15-1 shows the structure of the LVI module. The LVI is enabled after a reset. The LVI module
contains a bandgap reference circuit and comparator. Setting LVI disable bit (LVID) disables the LVI to
monitor VDD voltage. The LVI trip voltage selection bits (LVIT1, LVIT0) determine at which VDD level the
LVI module should take actions.
The LVI module generates one output signal:
LVI Reset an reset signal will be generated to reset the CPU when VDD drops to below the set trip
point.
VDD
LVID
VDD > LVITRIP = 0

LOW VDD
LVI RESET
VDD < LVITRIP = 1
DETECTOR
LVIT1
LVIT0
Figure 15-1. LVI Module Block Diagram

177
15.4 LVI Control Register (CONFIG2/CONFIG1)

The LVI module is controlled by three bits in the configuration registers, CONFIG1 and CONFIG2.
Address:
$001E
Read:
Write:
Bit 7
Bit 0
IRQPUD
LVIT1
LVIT0
STOP_
ICLKDIS
Cleared by POR only
Reset:

Address:
$001F
Read:
Write:
Bit 7
Bit 0
COPRS
LVID
SSREC
STOP
COPD
Reset:

LVID Low Voltage Inhibit Disable Bit
LVID disables the LVI module. Reset clears LVID.
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
LVIT1, LVIT0 LVI Trip Voltage Selection Bits
These two bits determine at which level of VDD the LVI module will come into action. LVIT1 and LVIT0
are cleared by a power-on reset only.
Table 15-1. Trip Voltage Selection
LVIT1
LVIT0
Trip Voltage(1)
Comments
VLVR3 (2.49V)
For VDD =3V operation
VLVR3 (2.49V)
VLVR5 (4.25V)
Reserved
1. See Chapter 17 Electrical Specifications for full parameters.

The STOP and WAIT instructions put the MCU in low-power-consumption standby modes.
15.5.1 Wait Mode

The LVI module, when enabled, will continue to operate in wait mode.
15.5.2 Stop Mode

The LVI module, when enabled, will continue to operate in stop mode.
178
Chapter 16
16.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops
normal program flow at a defined address to enter a background program.
16.2 Features
Features of the break module include the following:
Accessible I/O registers during the break Interrupt
CPU-generated break interrupts
Software-generated break interrupts
COP disabling during break interrupts

When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal (BKPT) to the SIM. The SIM then causes the CPU to load the instruction
register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The
program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
Software writes a logic one to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return from interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal operation. Figure 16-1 shows the
structure of the break module.
IAB[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
IAB[15:0]
CONTROL
BKPT
(TO SIM)
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
IAB[7:0]
Figure 16-1. Break Module Block Diagram

179
Addr.
Register Name
$FE00 Break Status Register (BSR)
$FE03
$FE0C
$FE0D
Break Flag Control

Register
(BFCR)
Break Address High
Register
(BRKH)
Break Address low
Register
(BRKL)
Break Status and Control

Register
(BRKSCR)
$FE0E
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
Bit 0
1
SBSW
See note
0
BCFE
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
BRKE
BRKA
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
= Reserved
0
0
= Unimplemented
Figure 16-2. Break I/O Register Summary

16.3.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
bits during the break state. (See 5.7.3 Break Flag Control Register (BFCR) and see the Break Interrupts
subsection for each module.)
16.3.2 CPU During Break Interrupts

The CPU starts a break interrupt by:
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD
($FEFC:$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
16.3.3 TIM During Break Interrupts

A break interrupt stops the timer counter.
16.3.4 COP During Break Interrupts

The COP is disabled during a break interrupt when VTST is present on the RST pin.

180
Break Module Registers
16.4 Break Module Registers

These registers control and monitor operation of the break module:
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
Break status register (BSR)
Break flag control register (BFCR)
16.4.1 Break Status and Control Register (BRKSCR)

The break status and control register contains break module enable and status bits.
Address:
$FE0E
Bit 7
Read:
Write:
Reset:
BRKE
BRKA
Bit 0
= Unimplemented
Figure 16-3. Break Status and Control Register (BRKSCR)

BRKE Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic
zero to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
BRKA Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a logic one to
BRKA generates a break interrupt. Clear BRKA by writing a logic zero to it before exiting the break
routine. Reset clears the BRKA bit.
1 = Break address match
0 = No break address match
16.4.2 Break Address Registers

The break address registers contain the high and low bytes of the desired breakpoint address. Reset
clears the break address registers.
Address:
Read:
Write:
Reset:
$FE0C
Bit 7
Bit 0
Bit 15
14
13
12
11
10
Bit 8
Figure 16-4. Break Address Register High (BRKH)

181

Address:
$FE0D
Read:
Write:
Reset:
Bit 7
Bit 0
Bit 7
Bit 0
Figure 16-5. Break Address Register Low (BRKL)
16.4.3 Break Status Register

The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.
Address:
$FE00
Read:
Write:
Bit 7
Bit 0
SBSW
Note(1)
Reset:
0
R
= Reserved
1. Writing a logic zero clears SBSW.
Figure 16-6. Break Status Register (BSR)

SBSW SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break
interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it. The following code is an example of this.
; This code works if the H register has been pushed onto the stack in the break
; service routine software. This code should be executed at the end of the
; break service routine software.
HIBYTE
EQU
LOBYTE
EQU
If not SBSW, do RTI

BRCLR
SBSW,BSR, RETURN
; See if wait mode or stop mode was exited

; by break.
TST
LOBYTE,SP
; If RETURNLO is not zero,
BNE
DOLO
; then just decrement low byte.
DEC
HIBYTE,SP
; Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN
PULH
RTI
; Restore H register.

182
Low-Power Modes
16.4.4 Break Flag Control Register (BFCR)

The break control register contains a bit that enables software to clear status bits while the MCU is in a
break state.
Address:
Read:
Write:
Reset:
$FE03
Bit 7
Bit 0
BCFE
0
R
= Reserved
Figure 16-7. Break Flag Control Register (BFCR)

BCFE Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break

The WAIT and STOP instructions put the MCU in low-power-consumption standby modes.
16.5.1 Wait Mode

If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from
the return address on the stack if SBSW is set (see 5.6 Low-Power Modes). Clear the SBSW bit by writing
logic zero to it.
16.5.2 Stop Mode

A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. See 5.7
SIM Registers.

183

184
Chapter 17
17.1 Introduction
This section contains electrical and timing specifications.
17.2 Absolute Maximum Ratings

Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it.
NOTE
This device is not guaranteed to operate properly at the maximum ratings.
Refer to Sections 17.5 and 17.8 for guaranteed operating conditions.
Table 17-1. Absolute Maximum Ratings
Characteristic(1)
Value
Unit
Supply voltage
VDD
0.3 to +6.0
Input voltage
VIN
VSS 0.3 to VDD +0.3
VTST
VSS 0.3 to +8.5
25
mA
Storage temperature
TSTG
55 to +150
Maximum current out of VSS
IMVSS
100
mA
Maximum current into VDD
IMVDD
100
mA
Mode entry voltage, IRQ pin

Maximum current per pin excluding VDD
and VSS
Symbol
1. Voltages referenced to VSS.
NOTE
This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIN and VOUT be constrained to the
range VSS (VIN or VOUT) VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD.)

185
17.3 Functional Operating Range

Table 17-2. Operating Range
Characteristic
Operating temperature range
Operating voltage range
Symbol
Value
Unit
TA
40 to +125
40 to +85
VDD
5 10%
3 10%
5 10%
17.4 Thermal Characteristics

Table 17-3. Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance
20-pin PDIP
20-pin SOIC
28-pin PDIP
28-pin SOIC
32-pin SDIP
32-pin LQFP
JA
I/O pin power dissipation
PI/O
User determined
Power dissipation(1)
PD
PD = (IDD VDD) + PI/O =

K/(TJ + 273 C)
Constant(2)
Average junction temperature
TJ
70
70
70
70
70
95
PD x (TA + 273 C)
C/W
+ PD2 JA
W/C
TA + (PD JA)
1. Power dissipation is a function of temperature.

2. K constant unique to the device. K can be determined for a known TA and measured PD.
With this value of K, PD and TJ can be determined for any value of TA.

186
5V DC Electrical Characteristics
17.5 5V DC Electrical Characteristics

Table 17-4. DC Electrical Characteristics (5V)
Characteristic(1)
Output high voltage (ILOAD = 2.0mA)
PTA0PTA7, PTB0PTB7, PTD0PTD7, PTE0PTE1
Output low voltage (ILOAD = 1.6mA)
PTA6, PTB0PTB7, PTD0, PTD1, PTD4, PTD5,
PTE0PTE1
Output low voltage (ILOAD = 25mA)
PTD6, PTD7
LED drives (VOL = 3V)
PTA0PTA5, PTA7, PTD2, PTD3, PTD6, PTD7
Input high voltage
PTA0PTA7, PTB0PTB7, PTD0PTD7, PTE0PTE1, RST,
IRQ, OSC1
Input low voltage
IRQ, OSC1
VDD supply current, fOP = 8MHz
Run(3)
XTAL oscillator option
RC oscillator option
Wait(4)
Stop(5) (40C to 125C)
Symbol
Min
Typ(2)
Max
Unit
VOH
VDD 0.8
VOL
0.4
VOL
0.5
IOL
10
16
25
mA
VIH
0.7 VDD
VDD
VIL
VSS
0.3 VDD
7.5
11
10
13
mA
mA
3
3.5
5.5
6
mA
mA
1.5
0.5
8
3
A
A
IDD
Digital I/O ports Hi-Z leakage current
IIL
10
Input current
IIN
Capacitance
Ports (as input or output)
COUT
CIN
12
8
pF
POR rearm voltage(6)
VPOR
100
mV
RPOR
0.035
V/ms
VTST
1.5 VDD
8.5
RPU1
RPU2
1.8
16
3.3
26
4.8
36
k
k
Low-voltage inhibit, trip falling voltage
VTRIPF
3.60
4.25
4.48
Low-voltage inhibit, trip rising voltage
VTRIPR
3.75
4.40
4.63
POR rise time ramp
rate(7)
Monitor mode entry voltage

resistors(8)
Pullup
PTD6, PTD7
RST, IRQ, PTA0PTA7
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 C only.
3. Run (operating) IDD measured using external square wave clock source (fOP = 8MHz). All inputs 0.2V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 8MHz). All inputs 0.2V from rail. No dc loads. Less than
100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD.
5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached.
8. RPU1 and RPU2 are measured at VDD = 5.0V.

187
17.6 5V Control Timing

Table 17-5. Control Timing (5V)
Characteristic(1)
Symbol
Min
Max
Unit
Internal operating frequency
fOP
MHz
(2)
tRL
750
ns
fT2CLK
MHz
tILIH
100
ns
tCYC
RST input pulse width low

TIM2 external clock input
IRQ interrupt pulse width low

IRQ interrupt pulse
(edge-triggered)(3)
period(3)
(4)
tILIL
Note
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise
noted.
2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
3. Values are based on characterization results, not tested in production.
4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
tRL
RST
tILIL
tILIH
IRQ
Figure 17-1. RST and IRQ Timing
17.7 5V Oscillator Characteristics

Table 17-6. Oscillator Specifications (5V)
Characteristic
Symbol
Internal oscillator clock frequency
fICLK
External reference clock to OSC1 (2)
fOSC
Crystal reference frequency (3)
Min
Typ
Max
50k(1)
dc
fXTALCLK
Hz
32M
Hz
32M
Hz
Crystal load capacitance (4)
CL
Crystal fixed capacitance (3)
C1
2 CL
Crystal tuning capacitance (3)
C2
2 CL
Feedback bias resistor
RB
10 M
RS
fRCCLK
2M
12M
Series resistor
(3), (5)
External RC clock frequency

RC oscillator external R
REXT
RC oscillator external C
CEXT
10
Hz
See Figure 17-2
Unit
pF
1. Typical value reflect average measurements at midpoint of voltage range, 25 C only. See Figure 17-5 for plot.
2. No more than 10% duty cycle deviation from 50%.
3. Fundamental mode crystals only.
4. Consult crystal vendor data sheet.
5. Not required for high frequency crystals.
188
3V DC Electrical Characteristics
RC frequency, fRCCLK (MHz)
14
12
CEXT = 10 pF
10
MCU
5V @ 25C
OSC1
8
6
VDD
4
REXT
CEXT
2
0
0
10
20
30
Resistor, REXT (k)
40
50
Figure 17-2. RC vs. Frequency (5V @25C)
17.8 3V DC Electrical Characteristics

Characteristic(1)
Output high voltage (ILOAD = 1.0mA)
PTA0PTA7, PTB0PTB7, PTD0PTD7, PTE0PTE1
Output low voltage (ILOAD = 0.8mA)
PTA6, PTB0PTB7, PTD0, PTD1, PTD4, PTD5,
PTE0PTE1
Output low voltage (ILOAD = 20mA)
PTD6, PTD7
LED drives (VOL = 1.8V)
PTA0PTA5, PTA7, PTD2, PTD3, PTD6, PTD7
Input high voltage
IRQ, OSC1
Input low voltage
PTA0PTA7, PTB0PTB7, PTD0PTD7, PTE0PTE1,RST,
IRQ, OSC1
Run(3)
Wait(4)
Stop(5) (40C to 85C)
Symbol
Min
Typ(2)
Max
Unit
VOH
VDD 0.4
VOL
0.4
VOL
0.5
IOL
12
mA
VIH
0.7 VDD
VDD
VIL
VSS
0.3 VDD
3
4
8
10
mA
mA
1
2
4.5
6
mA
mA
0.5
0.3
5
2
A
A
IDD
Digital I/O ports Hi-Z leakage current
IIL
10
Input current
IIN

189

Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Capacitance
Ports (as input or output)
COUT
CIN
12
8
pF
POR rearm voltage(6)
VPOR
100
mV
POR rise time ramp rate(7)
RPOR
0.035
V/ms
Monitor mode entry voltage
VTST
1.5 VDD
8.5
RPU1
RPU2
1.8
16
3.3
26
4.8
36
k
k
VLVI3
2.18
2.49
2.68
resistors(8)
Pullup
PTD6, PTD7
RST, IRQ, PTA0PTA7
Low-voltage inhibit, trip voltage
(No hysteresis implemented for 3V LVI)
3. Run (operating) IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 4MHz). All inputs 0.2V from rail. No dc loads. Less than
100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD.
5. Stop IDD measured with OSC1 grounded; no port pins sourcing current. LVI is disabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
8. RPU1 and RPU2 are measured at VDD = 5.0V.
17.9 3V Control Timing

Table 17-8. Control Timing (3V)
Characteristic(1)
Symbol
Min
Max
Unit
Internal operating frequency
fOP
MHz
RST input pulse width low(2)
tRL
1.5
fT2CLK
MHz
tILIH
200
ns
tILIL
Note(4)
tCYC
TIM2 external clock input

IRQ interrupt pulse width low (edge-triggered)(3)
IRQ interrupt pulse period(3)
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise
noted.
2. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
3. Values are based on characterization results, not tested in production.
4. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
tRL
RST
tILIL
tILIH
IRQ
Figure 17-3. RST and IRQ Timing

190
3V Oscillator Characteristics
17.10 3V Oscillator Characteristics

Table 17-9. Oscillator Specifications (3V)
Characteristic
Symbol
Internal oscillator clock frequency
fICLK
External reference clock to OSC1 (2)
fOSC
Crystal reference frequency (3)
Min
Typ
45k
dc
fXTALCLK
Max
Hz
16M
Hz
16M
Hz
Crystal load capacitance
(4)
CL
Crystal fixed capacitance
(3)
C1
2 CL
C2
2 CL
RB
10 M
RS
fRCCLK
2M
10M
Crystal tuning capacitance
(3)
Feedback bias resistor

Series resistor
(3), (5)
External RC clock frequency

RC oscillator external R
REXT
RC oscillator external C
CEXT
Unit
(1)
Hz
See Figure 17-4
10
pF
1. Typical value reflect average measurements at midpoint of voltage range, 25 C only. See Figure 17-5 for plot.
2. No more than 10% duty cycle deviation from 50%.
3. Fundamental mode crystals only.
4. Consult crystal vendor data sheet.
5. Not required for high frequency crystals.
14
12
CEXT = 10 pF
10
MCU
3V @ 25C
OSC1
8
6
VDD
REXT
CEXT
2
0
0
10
20
30
Resistor, REXT (k)
40
50
Figure 17-4. RC vs. Frequency (3V @25C)

191
Internal OSC frequency, fICLK (kHz)
70
60
40C
+25C
50
+85C
+125C
40
30
20
2
4
5
Supply Voltage, VDD (V)
Figure 17-5. Internal Oscillator Frequency
17.11 Typical Supply Currents
IDD (mA)
10
5.5 V
3.3 V
6
4
2
0
0
4
5
6
fOP or fBUS (MHz)
Figure 17-6. Typical Operating IDD (XTAL osc),

with All Modules Turned On (25 C)
5
IDD (mA)
5.5 V
3.3 V
3
2
1
0
0
4
5
6
fOP or fBUS (MHz)
Figure 17-7. Typical Wait Mode IDD (XTAL osc),

with All Modules Turned Off (25 C)

192
Timer Interface Module Characteristics
17.12 Timer Interface Module Characteristics

Table 17-10. Timer Interface Module Characteristics (5V and 3V)
Characteristic
Input capture pulse width
Input clock pulse width (T2CLK pulse width)
Symbol
Min
Max
tTIH, tTIL
1/fOP
tLMIN, tHMIN
(1/fOP) + 5ns
Unit
17.13 ADC Characteristics

Table 17-11. ADC Characteristics (5V and 3V)
Characteristic
Symbol
Min
Max
Unit
Supply voltage
VDDAD
2.7
(VDD min)
5.5
(VDD max)
Input voltages
VADIN
VSS
VDD
Resolution
BAD
Bits
Absolute accuracy
AAD
0.5
1.5
LSB
Includes quantization
ADC internal clock
fADIC
0.5
1.048
MHz
tAIC = 1/fADIC, tested only

at 1 MHz
Conversion range
RAD
VSS
VDD
Power-up time
tADPU
16
Conversion time
tADC
14
15
tAIC cycles
time(1)
Comments
tAIC cycles
tADS
tAIC cycles
Zero input
reading(2)
ZADI
00
01
Hex
VIN = VSS
Full-scale
reading(3)
FADI
FE
FF
Hex
VIN = VDD
CADI
(20) 8
pF
Not tested
Sample
Input capacitance
(3)
Input leakage
Port B/port D
1. Source impedances greater than 10 k adversely affect internal RC charging time during input sampling.
2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
3. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.

193
17.14 Memory Characteristics

Table 17-12. Memory Characteristics
Characteristic
RAM data retention voltage

FLASH program bus clock frequency
Symbol
Min
Max
Unit
VRDR
1.3
MHz
32k
8M
Hz
(1)
FLASH read bus clock frequency
fread
FLASH page erase time
terase(2)
ms
FLASH mass erase time
tmerase(3)
ms
FLASH PGM/ERASE to HVEN set up time
tnvs
10
FLASH high-voltage hold time
tnvh
FLASH high-voltage hold time (mass erase)
tnvhl
100
FLASH program hold time
tpgs
FLASH program time
tprog
30
40
(4)
FLASH return to read time
trcv
FLASH cumulative program hv period
tHV(5)
ms
10k
cycles
10k
cycles
10
years
FLASH row erase
endurance(6)
FLASH row program
endurance(7)
FLASH data retention time(8)
1. fread is defined as the frequency range for which the FLASH memory can be read.
2. If the page erase time is longer than terase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH
memory.
3. If the mass erase time is longer than tmerase (Min), there is no erase-disturb, but it reduces the endurance of the FLASH
memory.
4. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing
HVEN to logic 0.
5. tHV is defined as the cumulative high voltage programming time to the same row before next erase.
tHV must satisfy this condition: tnvs + tnvh + tpgs + (tprog 32) tHV max.
6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many
erase / program cycles.
7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many
erase / program cycles.
8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified.

194
Chapter 18
18.1 Introduction
This section gives the dimensions for:
20-pin plastic dual in-line package (case #738)
20-pin small outline integrated circuit package (case #751D)
28-pin plastic dual in-line package (case #710)
28-pin small outline integrated circuit package (case #751F)
32-pin shrink dual in-line package (case #1376)
32-pin low-profile quad flat pack (case #873A)
18.2 20-Pin Plastic Dual In-Line Package (PDIP)

A
20
11
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
SEATING
PLANE
M
N
E
G
J
D
0.25 (0.010)
20 PL
0.25 (0.010)
20 PL
M
T A
T B
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
Figure 18-1. 20-Pin PDIP (Case #738)

195
18.3 20-Pin Small Outline Integrated Circuit Package (SOIC)

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
A
20
11
10X
P
0.010 (0.25)
10
20X
0.010 (0.25)
T A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
S
F
R X 45 _
C
T
18X
SEATING
PLANE
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
Figure 18-2. 20-Pin SOIC (Case #751D)
18.4 28-Pin Plastic Dual In-Line Package (PDIP)
28
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
15
B
14
A
N
F
D
SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
36.45
37.21
13.72
14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 BSC
0
15
0.51
1.02
INCHES
MIN
MAX
1.435
1.465
0.540
0.560
0.155
0.200
0.014
0.022
0.040
0.060
0.100 BSC
0.065
0.085
0.008
0.015
0.115
0.135
0.600 BSC
0
15
0.020
0.040
Figure 18-3. 28-Pin PDIP (Case #710)

196
28-Pin Small Outline Integrated Circuit Package (SOIC)
18.5 28-Pin Small Outline Integrated Circuit Package (SOIC)

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
-A15
28
14X
-B1
P
0.010 (0.25)
14
28X
0.010 (0.25)
T A
X 45
C
26X
-T-
SEATING
PLANE
F
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
17.80
18.05
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0
8
10.01
10.55
0.25
0.75
INCHES
MIN
MAX
0.701
0.711
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0
8
0.395
0.415
0.010
0.029
Figure 18-4. 28-Pin SOIC (Case #751F)
18.6 32-Pin Shrink Dual In-Line Package (SDIP)

3
27.9
27.8
32
17
10.46
9.86
8.9
8.8
4.35
4.05
0.75
0.45
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5, 1994.
3. DIMENSIONS DO NOT INCLUDE MOLD FLASH OR
PROTRUSIONS.
4. DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION.
16
30X
1.778
2X
0.889
2.49
2.39
C
32X
0.13
0.5
0.4 4
T A B
T
SEATING
PLANE
10
0
0.34
0.22
SECTION CC
Figure 18-5. 32-Pin SDIP (Case #1376)

197
T, U, Z
18.7 32-Pin Low-Profile Quad Flat Pack (LQFP)
4X
A1
32
0.20 (0.008) AB TU Z
25
T
B
AE
P
B1
DETAIL Y
17
V1
AE
DETAIL Y
4X
Z
9
0.20 (0.008) AC TU Z
S1
S
DETAIL AD
G
AB
0.10 (0.004) AC
AC TU Z
AC
BASE
METAL
F
8X
M_
0.20 (0.008)
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
3. DATUM PLANE AB IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS T, U, AND Z TO BE DETERMINED
AT DATUM PLANE AB.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE AC.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE AB.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
SECTION AEAE
K
X
DETAIL AD
Q_
GAUGE PLANE
0.250 (0.010)
C E
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
Figure 18-6. 32-Pin LQFP (Case #873A)

198
Chapter 19
19.1 Introduction
This section contains ordering numbers for the MC68HC908JL8.
19.2 MC Order Numbers

Table 19-1. MC Order Numbers
MC Order Number
Operating
Temperature Range
MC68HC908JK8CP
40 C to +85 C
MC68HC908JK8MP
40 C to +125 C
MC68HC908JK8CDW
40 C to +85 C
MC68HC908JK8MDW
40 C to +125 C
MC68HC908JL8CP
40 C to +85 C
MC68HC908JL8MP
40 C to +125 C
MC68HC908JL8CDW
40 C to +85 C
MC68HC908JL8MDW
40 C to +125 C
MC68HC908JL8CSP
40 C to +85 C
MC68HC908JL8MSP
40 C to +125 C
MC68HC908JL8CFA
40 C to +85 C
MC68HC908JL8MFA
40 C to +125 C
Package
20-pin PDIP
20-pin SOIC
28-pin PDIP
28-pin SOIC
32-pin SDIP
32-pin LQFP
NOTE: Temperature grade "M" is available for VDD = 5V only.

199

200
Appendix A
MC68HC08JL8
A.1 Introduction
This section introduces the MC68HC08JL8, the ROM part equivalent to the MC68HC908JL8/JK8. The
entire data book applies to this ROM device, with exceptions outlined in this appendix.
Table A-1. Summary of MC68HC08JL8 and MC68HC908JL8 Differences
MC68HC08JL8
MC68HC908JL8
Memory ($DC00$FBFF)
8,192 bytes ROM
8,192 bytes FLASH
User vectors ($FFDC$FFFF)
36 bytes ROM
36 bytes FLASH
Registers at $FE08 and $FFCF
Not used;
locations are reserved.
FLASH related registers.

$FE08 FLCR
$FFCF FLBPR
Mask option register ($FFD0)
Defined by mask; read only.
Read/write FLASH register.
Monitor ROM
($FC00$FDFF and $FE10$FFCE)
$FC00$FDFF: Not used.

$FE10$FFCE: Used for testing
purposes only.
Used for testing and FLASH

programming/erasing.
Available Packages
20-pin PDIP (MC68HC08JK8)

20-pin SOIC (MC68HC08JK8)
28-pin PDIP
28-pin SOIC
32-pin SDIP
32-pin LQFP

28-pin PDIP
28-pin SOIC
32-pin SDIP
32-pin LQFP
A.2 MCU Block Diagram

Figure A-1 shows the block diagram of the MC68HC08JL8.
A.3 Memory Map

The MC68HC08JL8 has 8,192 bytes of user ROM from $DC00 to $FBFF, and 36 bytes of user ROM
vectors from $FFDC to $FFFF. On the MC68HC908JL8, these memory locations are FLASH memory.
Figure A-2 shows the memory map of the MC68HC08JL8.

201
INTERNAL BUS
USER ROM 8,192 BYTES
PORTA
ARITHMETIC/LOGIC
UNIT (ALU)
PTA7/KBI7**
PTA6/KBI6**
PTA5/KBI5**
PTA4/KBI4**
PTA3/KBI3**
PTA2/KBI2**
PTA1/KBI1**
PTA0/KBI0**
PTB7/ADC7
PTB6/ADC6
PTB5/ADC5
PTB4/ADC4
PTB3/ADC3
PTB2/ADC2
PTB1/ADC1
PTB0/ADC0
KEYBOARD INTERRUPT
MODULE
8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
DDRA
CPU
REGISTERS
PORTB
M68HC08 CPU

MODULE 1

MODULE 2
USER ROM VECTORS 36 BYTES
ADC12/T2CLK
INTERFACE MODULE
* RST
SYSTEM INTEGRATION
MODULE
LOW-VOLTAGE INHIBIT
MODULE
* IRQ
EXTERNAL INTERRUPT
MODULE
VDD
POWER
VSS
ADC REFERENCE
COMPUTER OPERATING
PROPERLY MODULE
PTE
POWER-ON RESET
MODULE
PORTD
RC OSCILLATOR
INTERNAL OSCILLATOR
##
DDRD
OSC2/RCCLK
CRYSTAL OSCILLATOR
BREAK
MODULE
DDRE
OSC1
DDRB
USER RAM 256 BYTES
PTD7/RxD**
PTD6/TxD**
PTD5/T1CH1
PTD4/T1CH0
PTD3/ADC8
PTD2/ADC9
PTD1/ADC10
PTD0/ADC11
##
PTE1/T2CH1
#
PTE0/T2CH0

## Pins available on 28-pin and 32-pin packages only.
Shaded blocks indicate differences to MC68HC908JL8
Figure A-1. MC68HC08JL8 Block Diagram
A.4 Reserved Registers

The two registers at $FE08 and $FFCF are reserved locations on the MC68HC08JL8.
On the MC68HC908JL8, these two locations are the FLASH control register and the FLASH block protect
register respectively.

202
$0000
$003F
I/O REGISTERS
64 BYTES
$0040
$005F
RESERVED
32 BYTES
$0060
$015F
RAM
256 BYTES
$0160
$DBFF
UNIMPLEMENTED
55,968 BYTES
$DC00
$FBFF
ROM
8,192 BYTES
$FC00
$FDFF
UNIMPLEMENTED
512 BYTES
$FE00
BREAK STATUS REGISTER (BSR)
$FE01
RESET STATUS REGISTER (RSR)
$FE02
RESERVED
$FE03
BREAK FLAG CONTROL REGISTER (BFCR)
$FE04
$FE05
$FE06
$FE07
RESERVED
$FE08
RESERVED
$FE09
$FF0B
RESERVED
$FE0C
BREAK ADDRESS HIGH REGISTER (BRKH)
$FE0D
BREAK ADDRESS LOW REGISTER (BRKL)
$FE0E
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
$FE0F
RESERVED
$FE10
$FFCE
MONITOR ROM
447 BYTES
$FFCF
RESERVED
$FFD0
MASK OPTION REGISTER (MOR) READ ONLY
$FFD1
$FFDB
RESERVED
11 BYTES
$FFDC
$FFFF
USER ROM VECTORS

36 BYTES
Figure A-2. MC68HC08JL8 Memory Map

203
A.5 Mask Option Register

The mask option register at $FFD0 is read only. The value is defined by mask option (hard-wired
connections) specified at the time as the ROM code submission.
On the MC68HC908JL8, the MOR is implemented as a FLASH, which can be programmed, erased, and
read.
A.6 Monitor ROM

The monitor program (monitor ROM: $FE10$FFCE) on the MC68HC08JL8 is for device testing only.
$FC00$FDFF are unused.
A.7 Electrical Specifications

Electrical specifications for the MC68HC908JL8 apply to the MC68HC08JL8, except for the parameters
indicated below.
A.7.1 DC Electrical Characteristics

Table A-2. DC Electrical Characteristics (5V)
Characteristic(1)
Symbol
IDD
Min
Typ(2)
Max
Unit
Values same as, and characterized from

MC68HC908JL8, but not tested.
Low-voltage inhibit, trip falling voltage
VTRIPF
3.55 (3.60)(3)
4.02 (4.25)
4.48 (4.48)
Low-voltage inhibit, trip rising voltage
VTRIPR
3.66 (3.75)
4.13 (4.40)
4.59 (4.63)
Max
Unit
3. The numbers in parenthesis are MC68HC908JL8 values.
Table A-3. DC Electrical Characteristics (3V)

Characteristic(1)
Low-voltage inhibit, trip voltage
(No hysteresis implemented for 3V LVI)
Symbol
IDD
VLVI3
Typ(2)
Min
Values same as, and characterized from

MC68HC908JL8, but not tested.
2.1 (2.18)(3)
2.4 (2.49)
2.69 (2.68)
3. The numbers in parenthesis are MC68HC908JL8 values.

204
14
12
CEXT = 10 pF
10
MCU
5V @ 25C
OSC1
8
6
VDD
4
REXT
CEXT
MC68HC908JL8
MC68HC08JL8
2
0
0
10
20
30
Resistor, REXT (k)
40
50
Figure A-3. RC vs. Frequency (5V @25C)
14
12
CEXT = 10 pF
10
MCU
3V @ 25C
OSC1
8
6
VDD
REXT
CEXT
MC68HC908JL8
MC68HC08JL8
2
0
0
10
20
30
Resistor, REXT (k)
40
50
Figure A-4. RC vs. Frequency (3V @25C)
A.8 Memory Characteristics

Table A-4. Memory Characteristics
Characteristic
RAM data retention voltage
Symbol
Min
Max
Unit
VRDR
1.3
Notes:
Since MC68HC08JL8 is a ROM device, FLASH memory electrical characteristics do not apply.

205
A.9 MC68HC08JL8 Order Numbers

These part numbers are generic numbers only. To place an order, ROM code must be submitted to the
ROM Processing Center (RPC).
Table A-5. MC68HC08JL8 Order Numbers
MC Order Number
Operating
Temperature Range
MC68HC08JK8CP
40 C to +85 C
MC68HC08JK8MP
40 C to +125 C
MC68HC08JK8CDW
40 C to +85 C
MC68HC08JK8MDW
40 C to +125 C
MC68HC08JL8CP
40 C to +85 C
MC68HC08JL8MP
40 C to +125 C
MC68HC08JL8CDW
40 C to +85 C
MC68HC08JL8MDW
40 C to +125 C
MC68HC08JL8CSP
40 C to +85 C
MC68HC08JL8MSP
40 C to +125 C
MC68HC08JL8CFA
40 C to +85 C
MC68HC08JL8MFA
40 C to +125 C
Package
20-pin PDIP
20-pin SOIC
28-pin PDIP
28-pin SOIC
32-pin SDIP
32-pin LQFP
NOTE: Temperature grade "M" is available for VDD = 5V only.

206
Appendix B
MC68HC908KL8
B.1 Introduction
This appendix introduces the MC68HC908KL8, an ADC-less device of the MC68HC908JL8. The entire
data book applies to this device, with exceptions outlined in this appendix.
Table B-1. Summary of MC68HC908KL8 and MC68HC908JL8 Differences
MC68HC908KL8
MC68HC908JL8
13-channel, 8-bit.
Registers at:
$003C, $003E, and $003E
Not used;
locations are reserved.
ADC registers.
Interrupt Vector at:

$FFDE and $FFDF
Not used.
ADC interrupt vector.
Available Packages
28-pin PDIP
28-pin SOIC
32-pin SDIP

28-pin PDIP
28-pin SOIC
32-pin SDIP
32-pin LQFP
B.2 MCU Block Diagram

Figure B-1 shows the block diagram of the MC68HC908KL8.
B.3 Pin Assignments

Figure B-2 and Figure B-3 show the pin assignments for the MC68HC908KL8.

207
INTERNAL BUS
PTA7/KBI7**
PTA6/KBI6**
PTA5/KBI5**
PTA4/KBI4**
PTA3/KBI3**
PTA2/KBI2**
PTA1/KBI1**
PTA0/KBI0**
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
KEYBOARD INTERRUPT
MODULE
USER FLASH 8,192 BYTES
PORTA
ARITHMETIC/LOGIC
UNIT (ALU)
DDRA
CPU
REGISTERS
PORTB
M68HC08 CPU

MODULE 1

MODULE 2
USER FLASH VECTORS 36 BYTES
* RST
SYSTEM INTEGRATION
MODULE
LOW-VOLTAGE INHIBIT
MODULE
* IRQ
EXTERNAL INTERRUPT
MODULE
POWER
COMPUTER OPERATING
PROPERLY MODULE
PORTD
POWER-ON RESET
MODULE
PTE
INTERNAL OSCILLATOR
VSS
RC OSCILLATOR
VDD
T2CLK
INTERFACE MODULE
DDRD
OSC2/RCCLK
CRYSTAL OSCILLATOR
BREAK
MODULE
DDRE
OSC1
DDRB
USER RAM 256 BYTES
PTD7/RxD**
PTD6/TxD**
PTD5/T1CH1
PTD4/T1CH0
PTD3
PTD2
PTD1
PTD0
PTE1/T2CH1
#
PTE0/T2CH0

Figure B-1. MC68HC908KL8 Block Diagram

208
IRQ
32
T2CLK
PTA0/KBI0
31
PTA7/KBI7
VSS
30
RST
OSC1
29
PTA5/KBI5
28
PTD4/T1CH0
PTA1/KBI1
27
PTD5/T1CH1
VDD
26
PTD2
PTA2/KBI2
25
PTA4/KBI4
PTA3/KBI3
24
PTD3
PTB7
10
23
PTB0
PTB6
11
22
PTB1
PTB5
12
21
PTD1
PTD7/RxD
13
20
PTB2
PTD6/TxD
14
19
PTB3
PTE0/T2CH0
15
18
PTD0
PTE1/T2CH1
16
17
PTB4
Figure B-2. 32-Pin SDIP Pin Assignment
IRQ
28
RST
PTA0/KBI0
27
PTA5/KBI5
VSS
26
PTD4/T1CH0
OSC1
25
PTD5/T1CH1
24
PTD2
PTA1/KBI1
23
PTA4/KBI4
VDD
22
PTD3
PTA2/KBI2
21
PTB0
PTA3/KBI3
20
PTB1
PTB7
10
19
PTD1
PTB6
11
18
PTB2
PTB5
12
17
PTB3
PTD7/RxD
13
16
PTD0
PTD6/TxD
14
15
PTB4

PTE0/T2CH0
PTE1/T2CH1
T2CLK
PTA7/KBI7
Figure B-3. 28-Pin PDIP/SOIC Pin Assignment

209
B.4 Reserved Registers

The following registers are reserved location on the MC68HC908KL8.
Addr.
$003C
$003D
$003E
Register Name
Bit 7
Bit 0
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Read:
Reserved Write:
Reset:
Figure B-4. Reserved Registers
B.5 Reserved Vectors

The following are reserved interrupt vectors on the MC68HC908KL8.
Table B-2. Reserved Vectors
Vector Priority
INT Flag
IF15
Address
Vector
$FFDE
Reserved
$FFDF
Reserved
B.6 MC68HC908KL8 Order Numbers

Table B-3. MC68HC908KL8 Order Numbers
Operating
Temperature Range
Package
MC68HC908KL8CP
40 C to +85 C
28-pin PDIP
MC68HC908KL8CDW
40 C to +85 C
28-pin SOIC
MC68HC908KL8CSP
40 C to +85 C
32-pin SDIP
MC Order Number

210
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MC68HC908JL8
Rev. 3.1, 3/2005
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Chapter 9 Serial Communications Interface (SCI) Corrected SCI

Figure 13-2 . Keyboard Interrupt Block Diagram

Added Appendix A MC68HC08JL8 ROM parts.

Added Appendix B MC68HC908KL8.

First general release.

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

ROM part for MC68HC908JL8

ROM part for MC68HC908JK8

11 LED drivers (sink)

Features of the CPU08 include the following:

1.3 MCU Block Diagram

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

MCU Block Diagram

CONTROL AND STATUS REGISTERS 64 BYTES

USER FLASH 8,192 BYTES

2-CHANNEL TIMER INTERFACE

2-CHANNEL TIMER INTERFACE

MONITOR ROM 959 BYTES

USER FLASH VECTORS 36 BYTES

USER RAM 256 BYTES

* Pin contains integrated pull-up device.

Figure 1-1. MC68HC908JL8 Block Diagram

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

1.4 Pin Assignments

Figure 1-2. 32-Pin LQFP Pin Assignment

Figure 1-3. 32-Pin SDIP Pin Assignment

Pins not available on 28-pin packages

Figure 1-4. 28-Pin PDIP/SOIC Pin Assignment

Pins not available on 20-pin packages

The 20-pin MC68HC908JL8 is designated MC68HC908JK8.

Figure 1-5. 20-Pin PDIP/SOIC Pin Assignment

1.5 Pin Functions

MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1

Table 1-2. Pin Functions

External IRQ pin; with programmable internal pull-up and schmitt

Used for monitor mode entry.

Crystal or RC oscillator input.

OSC2: crystal oscillator output; inverted OSC1 signal.

RCCLK: RC oscillator clock output.

ADC12: channel-12 input of ADC.

T2CLK: external input clock for TIM2.

Each pin has programmable internal pull-up when configured as

Pins as keyboard interrupts, KBI0KBI7.

PTA0PTA5 and PTA7 have LED direct sink capability.

8-bit general purpose I/O port;

PTD0PTD3 as ADC input channels, ADC11ADC8.