89 e 58 RD 2

FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD

SST89E/V58 / 54 / 52RD2/RD FlashFlex51 MCU
Data Sheet
FEATURES:
8-bit 8051-Compatible Microcontroller (MCU) with Embedded SuperFlash Memory Fully Software Compatible Development Toolset Compatible Pin-For-Pin Package Compatible SST89E5xRD2 Operation 0 to 40 MHz at 5V SST89V5xRD2 Operation 0 to 33 MHz at 3V 1 KByte Internal RAM Dual Block SuperFlash EEPROM 8/16/32 KByte primary block + 8 KByte secondary block (128-Byte sector size for both blocks) Individual Block Security Lock with SoftLock Concurrent Operation during In-Application Programming (IAP) Memory Overlay for Interrupt Support during IAP Support External Address Range up to 64 KByte of Program and Data Memory Three High-Current Drive Ports (16 mA each) Three 16-bit Timers/Counters Full-Duplex, Enhanced UART Framing Error Detection Automatic Address Recognition Ten Interrupt Sources at 4 Priority Levels Four External Interrupt Inputs Programmable Watchdog Timer (WDT) Programmable Counter Array (PCA) Four 8-bit I/O Ports (32 I/O Pins) and One 4-bit Port Second DPTR register Low EMI Mode (Inhibit ALE) SPI Serial Interface Standard 12 Clocks per cycle, the device has an option to double the speed to 6 clocks per cycle. TTL- and CMOS-Compatible Logic Levels Brown-out Detection Low Power Modes Power-down Mode with External Interrupt Wake-up Idle Mode Temperature Ranges: Commercial (0C to +70C) Industrial (-40C to +85C) Packages Available 40-contact WQFN (Port 4 feature not available) 44-lead PLCC 40-pin PDIP (Port 4 feature not available) 44-lead TQFP All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST89E5xRD2/RD and SST89V5xRD2/RD are members of the FlashFlex51 family of 8-bit microcontroller products designed and manufactured with SSTs patented and proprietary SuperFlash CMOS semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for SSTs customers. The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices. The devices come with 16/24/40 KByte of on-chip flash EEPROM program memory which is partitioned into 2 independent program memory blocks. The primary Block 0 occupies 8/16/32 KByte of internal program memory space and the secondary Block 1 occupies 8 KByte of internal program memory space. The 8-KByte secondary block can be mapped to the lowest location of the 8/16/32 KByte address space; it can also be hidden from the program counter and used as an independent EEPROM-like data memory. In addition to the 16/24/40 KByte of EEPROM program memory on-chip, the devices can address up to 64 KByte of external program memory. In addition to 1024 x8 bits of on-chip RAM, up to 64 KByte of external RAM can be addressed. The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and the firmware for SSTs devices. During poweron reset, the devices can be configured as either a slave to an external host for source code storage or a master to an external host for an in-application programming (IAP) operation. The devices are designed to be programmed in-system and in-application on the printed circuit board for maximum flexibility. The devices are pre-programmed with an example of the bootstrap loader in the memory, demonstrating the initial user program code loading or subsequent user code updating via the IAP operation. The sample bootstrap loader is available for the users reference and convenience only; SST does not guarantee its functionality or usefulness. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code.
2006 Silicon Storage Technology, Inc. S71255-05-000 5/06 1
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD

Data Sheet
TABLE OF CONTENTS
FEATURES: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.0 FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.0 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Program Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Program Memory Block Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Data RAM Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Expanded Data RAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 Dual Data Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0 FLASH MEMORY PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1 Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2 In-Application Programming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.0 TIMERS/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2 Timer Set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3 Programmable Clock-Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.0 SERIAL I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.1 Full-Duplex, Enhanced UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.0 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.0 PROGRAMMABLE COUNTER ARRAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.1 PCA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2 PCA Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.3 Compare/Capture Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.0 SECURITY LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.1 Hard Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2006 Silicon Storage Technology, Inc. S71255-05-000 5/06

Data Sheet 9.2 SoftLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.3 Security Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.4 Read Operation Under Lock Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.2 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.3 Brown-out Detection Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.0 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.1 Interrupt Priority and Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.0 POWER-SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.2 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.0 SYSTEM CLOCK AND CLOCK OPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13.1 Clock Input Options and Recommended Capacitor Values for Oscillator . . . . . . . . . . . . . . . . . . . . . . 62 13.2 Clock Doubling Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 14.0 ELECTRICAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14.2 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 15.0 PRODUCT ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 15.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 16.0 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
LIST OF FIGURES
FIGURE 1-1: Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 FIGURE 2-1: Pin Assignments for 40-contact WQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 2-2: Pin Assignments for 40-pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FIGURE 2-3: Pin Assignments for 44-lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FIGURE 2-4: Pin Assignments for 44-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FIGURE 3-1: Program Memory Organization for 8 KByte SST89x52RDx . . . . . . . . . . . . . . . . . . . . . . . . . . 11 FIGURE 3-2: Program Memory Organization for 16 KByte SST89x54RDx . . . . . . . . . . . . . . . . . . . . . . . . . 12 FIGURE 3-3: Program Memory Organization for 32 KByte SST89x58RDx . . . . . . . . . . . . . . . . . . . . . . . . . 12 FIGURE 3-4: Internal and External Data Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FIGURE 3-5: Dual Data Pointer Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FIGURE 4-1: Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FIGURE 4-2: Block-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FIGURE 4-3: Sector-Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Data Sheet FIGURE 4-4: Byte-Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 FIGURE 4-5: Byte-Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 FIGURE 4-6: Prog-SB3, Prog-SB2, Prog-SB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 FIGURE 4-7: Prog-SC0 and Prog-SC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 FIGURE 4-8: Enable-Clock-Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 FIGURE 6-1: Framing Error Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 FIGURE 6-2: UART Timings in Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FIGURE 6-3: UART Timings in Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FIGURE 6-4: SPI Master-slave Interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 FIGURE 6-5: SPI Transfer Format with CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 FIGURE 6-6: SPI Transfer Format with CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 FIGURE 7-1: Block Diagram of Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 FIGURE 8-1: PCA Timer/Counter and Compare/Capture Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 FIGURE 8-2: PCA Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FIGURE 8-3: PCA Compare Mode (Software Timer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 FIGURE 8-4: PCA High Speed Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 FIGURE 8-5: PCA Pulse Width Modulator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 FIGURE 8-6: PCA Watchdog Timer (Module 4 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 FIGURE 9-1: Security Lock Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 FIGURE 10-1: Power-on Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 FIGURE 11-1: Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 FIGURE 13-1: Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 FIGURE 14-1: IDD vs. Frequency for 3V SST89V5xRD2/RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 FIGURE 14-2: IDD vs. Frequency for 5V SST89E5xRD2/RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 FIGURE 14-3: External Program Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 FIGURE 14-4: External Data Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 FIGURE 14-5: External Data Memory Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 FIGURE 14-6: External Clock Drive Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 FIGURE 14-7: Shift Register Mode Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 FIGURE 14-8: AC Testing Input/Output Test Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 FIGURE 14-9: Float Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 FIGURE 14-10: A Test Load Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 FIGURE 14-11: IDD Test Condition, Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 FIGURE 14-12: IDD Test Condition, Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 FIGURE 14-13: IDD Test Condition, Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 FIGURE 16-1: 40-pin Plastic Dual In-line Pins (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 FIGURE 16-2: 44-lead Plastic Lead Chip Carrier (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 FIGURE 16-3: 44-lead Thin Quad Flat Pack (TQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 FIGURE 16-4: 40-contact Very-very-thin Quad Flat No-lead (WQFN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2006 Silicon Storage Technology, Inc.
S71255-05-000
5/06

Data Sheet
LIST OF TABLES
TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TABLE 3-1: SFCF Values for Program Memory Block Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 3-2: SFCF Values Under Different Reset Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 3-3: External Data Memory RD#, WR# with EXTRAM bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 TABLE 3-4: FlashFlex51 SFR Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TABLE 3-5: CPU related SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TABLE 3-6: Flash Memory Programming SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 TABLE 3-7: Watchdog Timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TABLE 3-8: Timer/Counters SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TABLE 3-9: Interface SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TABLE 3-10: PCA SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TABLE 4-1: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 TABLE 4-2: IAP Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TABLE 5-1: Timer/Counter 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TABLE 5-2: Timer/Counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TABLE 5-3: Timer/Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 TABLE 8-1: PCA Timer/Counter Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 TABLE 8-2: PCA Timer/Counter Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 TABLE 8-3: CMOD Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 TABLE 8-4: PCA High and Low Register Compare/Capture Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 TABLE 8-5: PCA Module Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 TABLE 8-6: PCA Module Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 TABLE 8-7: Pulse Width Modulator Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 TABLE 9-1: Security Lock Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 TABLE 9-2: Security Lock Access Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 TABLE 11-1: Interrupt Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 TABLE 12-1: Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 TABLE 13-1: Recommended Values for C1 and C2 by Crystal Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 TABLE 13-2: Clock Doubling Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 TABLE 14-1: Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 TABLE 14-2: Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 TABLE 14-3: AC Conditions of Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 TABLE 14-4: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 TABLE 14-5: Pin Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 TABLE 14-6: DC Electrical Characteristics for SST89E5xRD2/RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TABLE 14-7: DC Electrical Characteristics for SST89V5xRD2/RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 TABLE 14-8: AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 TABLE 14-9: External Clock Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 TABLE 14-10: Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 TABLE 14-11: Flash Memory Programming/Verification Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TABLE 16-1: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Data Sheet
1.0 FUNCTIONAL BLOCKS
8051 CPU Core

ALU, ACC, B-Register, Instruction Register, Program Counter, Timing and Control Oscillator
Interrupt Control
10 Interrupts
Watchdog Timer
Flash Control Unit
SuperFlash EEPROM Primary Block 8K/16K/32K x8 Secondary Block 8K x8
RAM 1K x8 8 I/O Port 0 8 Security Lock I/O Port 1 8 I/O Port 2 I/O 8 I/O Port 3 I/O 4 I/O Port 4 I/O I/O I/O
Timer 0 (16-bit)
Timer 1 (16-bit)
Timer 2 (16-bit)
SPI
PCA Enhanced UART
1255 B1.1
FIGURE
1-1: Functional Block Diagram
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Data Sheet
2.0 PIN ASSIGNMENTS
P1.4 (CEX1 / SS#)
P1.1 (T2 EX)
P1.3 (CEX0)
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
(CEX2 / MOSI) P1.5 (CEX3 / MISO) P1.6 (CEX4 / SCK) P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5
40
P0.3 (AD3)
P1.2 (ECI)
P1.0 (T2)
VDD
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7)
Top View
(contacts facing down)
EA# ALE/PROG#? PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13)
(WR#) P3.6
(RD#) P3.7
(A10) P2.2
(A11) P2.3
(A12) P2.4
XTAL2
XTAL1
VSS
(A8) P2.0
(A9) P2.1
1255 40-wqfn QI P1.0
FIGURE
2-1: Pin Assignments for 40-contact WQFN
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Data Sheet
(T2) P1.0 (T2 EX) P1.1 (ECI) P1.2 (CEX0) P1.3 (CEX1 / SS#) P1.4 (CEX2 / MOSI) P1.5 (CEX3 / MISO) P1.6 (CEX4 / SCK) P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5 (WR#) P3.6 (RD#) P3.7 XTAL2 XTAL1 VSS
1 2 3 4 5 6 7 8
40 39 38 37 36 35 34
VDD P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11)
XTAL2 XTAL1 (WR#) P3.6 VSS (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (RD#) P3.7 (A12) P2.4 P4.0 (CEX2 / MOSI) P1.5 (CEX3 / MISO) P1.6 (CEX4 / SCK) P1.7 RST (RXD) P3.0 INT2#/P4.3 (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5 1 2 3 4 5 6 7 8 9 10 P1.4 (SS# / CEX1)
P0.0 (AD0)
P1.1 (T2 EX)
P1.3 (CEX0)
P4.2/INT3#
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
40-pin PDIP Top View 33 32 9 31 10 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# P4.1 ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13)
44-lead TQFP Top View
11 23 12 13 14 15 16 17 18 19 20 21 22
P2.2 (A10) P2.1 (A9) P2.0 (A8)

1255 40-pdip PI P1.0
P0.3 (AD3)
1255 44-tqfp TQJ P2.0
P1.2 (ECI)
P1.0 (T2)
FIGURE
2-2: Pin Assignments for 40-pin PDIP
FIGURE
2-3: Pin Assignments for 44-lead TQFP
P1.4 (SS# / CEX1)
P1.1 (T2 EX)
P1.3 (CEX0)
P4.2/INT3#
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
6 (CEX2 / MOSI) P1.5 (CEX3 / MISO) P1.6 (CEX4 / SCK) P1.7 RST (RXD) P3.0 INT2#/P4.3 (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 (T1) P3.5 7 8 9 10 11 12 13 14 15 16
2 1 44 43 42 41 40 39 38 37 36 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# P4.1 ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13)
44-lead PLCC Top View
17 29 18 19 20 21 22 23 24 25 26 27 28
(WR#) P3.6 (RD#) P3.7 XTAL2 XTAL1 VSS P4.0 (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4
P0.3 (AD3)
P1.2 (ECI)
P1.0 (T2)
VDD
35 34 33 32 31 30
1255 44-plcc NJ P3.0
FIGURE
2-4: Pin Assignments for 44-lead PLCC
VDD
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Data Sheet
2.1 Pin Descriptions

TABLE
Symbol P0[7:0]
2-1: Pin Descriptions (1 of 2)

Type1 I/O Name and Functions Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins float that have 1s written to them, and in this state can be used as high-impedance inputs. In this application, it uses strong internal pull-ups when transitioning to VOH. Port 0 also receives the code bytes during the external host mode programming, and outputs the code bytes during the external host mode verification. External pull-ups are required during program verification. Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can drive LS TTL inputs. Port 1 pins are pulled high by the internal pull-ups when 1s are written to them and can be used as inputs in this state. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. P1[5, 6, 7] have high current drive of 16 mA. Port 1 also receives the low-order address bytes during the external host mode programming and verification. T2: External count input to Timer/Counter 2 or Clock-out from Timer/Counter 2 T2EX: Timer/Counter 2 capture/reload trigger and direction control ECI: PCA Timer/Counter External Input: This signal is the external clock input for the PCA timer/counter. CEX0: Compare/Capture Module External I/O Each compare/capture module connects to a Port 1 pin for external I/O. When not used by the PCA, this pin can handle standard I/O. SS#: Master Input or Slave Output for SPI. OR CEX1: Compare/Capture Module External I/O MOSI: Master Output line, Slave Input line for SPI OR CEX2: Compare/Capture Module External I/O MISO: Master Input line, Slave Output line for SPI OR CEX3: Compare/Capture Module External I/O SCK: Master clock output, slave clock input line for SPI OR CEX4: Compare/Capture Module External I/O Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins are pulled high by the internal pull-ups when 1s are written to them and can be used as inputs in this state. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 sends the high-order address byte during fetches from external Program memory and during accesses to external Data Memory that use 16-bit address (MOVX@DPTR). In this application, it uses strong internal pull-ups when transitioning to VOH. Port 2 also receives some control signals and high-order address bits during the external host mode programming and verification. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can drive LS TTL inputs. Port 3 pins are pulled high by the internal pull-ups when 1s are written to them and can be used as inputs in this state. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also receives some control signals and high-order address bits during the external host mode programming and verification. RXD: Universal Asynchronous Receiver/Transmitter (UART) - Receive input TXD: UART - Transmit output INT0#: External Interrupt 0 Input INT1#: External Interrupt 1 Input
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P1[7:0]
I/O with internal pull-ups
P1[0] P1[1] P1[2] P1[3]
I/O I I I/O
P1[4]
I/O
P1[5]
I/O
P1[6]
I/O
P1[7]
I/O
P2[7:0]
I/O with internal pull-up
P3[7:0]
I/O with internal pull-up
P3[0] P3[1] P3[2] P3[3]
I O I I

Data Sheet TABLE
Symbol P3[4] P3[5] P3[6] P3[7] PSEN#
2-1: Pin Descriptions (Continued) (2 of 2)

Type1 I I O O I/O Name and Functions T0: External count input to Timer/Counter 0 T1: External count input to Timer/Counter 1 WR#: External Data Memory Write strobe RD#: External Data Memory Read strobe Program Store Enable: PSEN# is the Read strobe to External Program Store. When the device is executing from Internal Program Memory, PSEN# is inactive (VOH). When the device is executing code from External Program Memory, PSEN# is activated twice each machine cycle, except when access to External Data Memory while one PSEN# activation is skipped in each machine cycle. A forced high-to-low input transition on the PSEN# pin while the RST input is continually held high for more than 20 machine cycles will cause the device to enter External Host mode for programming. Reset: While the oscillator is running, a high logic state on this pin for two machine cycles will reset the device. After a reset, if the PSEN# pin is driven by a high-to-low input transition while the RST input pin is held high, the device will enter the External Host mode, otherwise the device will enter the Normal operation mode. External Access Enable: EA# must be driven to VIL in order to enable the device to fetch code from the External Program Memory. EA# must be driven to VIH for internal program execution. However, Security lock level 4 will disable EA#, and program execution is only possible from internal program memory. The EA# pin can tolerate a high voltage2 of 12V. Address Latch Enable: ALE is the output signal for latching the low byte of the address during an access to external memory. This pin is also the programming pulse input (PROG#) for flash programming. Normally the ALE3 is emitted at a constant rate of 1/6 the crystal frequency4 and can be used for external timing and clocking. One ALE pulse is skipped during each access to external data memory. However, if AO is set to 1, ALE is disabled. Port 4: Port 4 is an 4-bit bi-directional I/O port with internal pull-ups. The port 4 output buffers can drive LS TTL inputs. Port 4 pins are pulled high by the internal pull-ups when 1s are written to them and can be used as inputs in this state. As inputs, port 4 pins that are externally pulled low will source current because of the internal pull-ups. Bit 0 of port 4 Bit 1 of port 4 Bit 2 of port 4 / INT3# External interrupt 3 input Bit 3 of port 4 / INT2# External interrupt 2 input Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier Power Supply Ground
T2-1.0 1255
RST
EA#
ALE/PROG#
I/O
P4[3:0]5
I/O with internal pull-ups
P4[0] P4[1] P4[2] / INT3# P4[3] / INT2# XTAL1 XTAL2 VDD VSS
I/O I/O I/O I/O I O I I
1. I = Input; O = Output 2. It is not necessary to receive a 12V programming supply voltage during flash programming. 3.ALE loading issue: When ALE pin experiences higher loading (>30pf) during the reset, the MCU may accidentally enter into modes other than normal working mode. The solution is to add a pull-up resistor of 3-50 K to VDD, e.g. for ALE pin. 4. For 6 clock mode, ALE is emitted at 1/3 of crystal frequency. 5. Port 4 is not present on the PDIP package.
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Data Sheet
3.0 MEMORY ORGANIZATION

The device has separate address spaces for program and data memory. bank selection. Please refer to Figures 3-1 through 3-3 for the program memory configuration. Program bank selection is described in the next section. The 8K/16K/32K x8 primary SuperFlash block is organized as 64/128/256 sectors, each sector consists of 128 Bytes. The 8K x8 secondary SuperFlash block is organized as 64 sectors, each sector consists also of 128 Bytes. For both blocks, the 7 least significant program address bits select the byte within the sector. The remainder of the program address bits select the sector within the block.
3.1 Program Flash Memory

There are two internal flash memory blocks in the device. The primary flash memory block (Block 0) has 8/16/32 KByte. The secondary flash memory block (Block 1) has 8 KByte. Since the total program address space is limited to 64 KByte, the SFCF[1:0] bit are used to control program
EA# = 0
FFFFH FFFFH E000H DFFFH
EA# = 1 SFCF[1:0] = 00
8 KByte Block 1 FFFFH E000H DFFFH
EA# = 1 SFCF[1:0] = 01
8 KByte Block 1
EA# = 1 SFCF[1:0] = 10, 11

FFFFH
External 64 KByte
Not Accessible
Not Accessible
Not Accessible
2000H 1FFFH 0000H 0000H
8 KByte Block 1
2000H 1FFFH 0000H
8 KByte Block 0
2000H 1FFFH 0000H
8 KByte Block 0
1255 F01.1
FIGURE
3-1: Program Memory Organization for 8 KByte SST89x52RDx
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Data Sheet
EA# = 0
EA# = 1 SFCF[1:0] = 00
EA# = 1 SFCF[1:0] = 01
8 KByte Block 1
EA# = 1 SFCF[1:0] = 10, 11

FFFFH
Not Accessible External 64 KByte
Not Accessible
Not Accessible
4000H 3FFFH 2000H 1FFFH 0000H 0000H
8 KByte Block 0 8 KByte Block 1
4000H 3FFFH 16 KByte Block 0 0000H
4000H 3FFFH 16 KByte Block 0 0000H

1255 F02.1
FIGURE
EA# = 0
EA# = 1 SFCF[1:0] = 00
EA# = 1 SFCF[1:0] = 01
8 KByte Block 1
EA# = 1 SFCF[1:0] = 10, 11

FFFFH
External 32 KByte External 24 KByte External 24 KByte
External 64 KByte
8000H 7FFFH
8000H 7FFFH
8000H 7FFFH
24 KByte Block 0 32 KByte Block 0 2000H 1FFFH 0000H 0000H 32 KByte Block 0
8 KByte Block 1 0000H 0000H

1255 F03.0
FIGURE
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Data Sheet
3.2 Program Memory Block Switching

The program memory block switching feature of the device allows either Block 1 or the lowest 8 KByte of Block 0 to be used for the lowest 8 KByte of the program address space. SFCF[1:0] controls program memory block switching. TABLE
10, 11 01 00
3-1: SFCF Values for Program Memory Block Switching

Program Memory Block Switching Block 1 is not visible to the PC; Block 1 is reachable only via in-application programming from E000H - FFFFH. Both Block 0 and Block 1 are visible to the PC. Block 0 is occupied from 0000H - 7FFFH. Block 1 is occupied from E000H - FFFFH. Block 1 is overlaid onto the low 8K of the program address space; occupying address locations 0000H - 1FFFH. When the PC falls within 0000H - 1FFFH, the instruction will be fetched from Block 1 instead of Block 0. Outside of 0000H - 1FFFH, Block 0 is used. Locations 0000H - 1FFFH of Block 0 are reachable through in-application programming.
T3-1.0 1255
SFCF[1:0]
3.2.1 Reset Configuration of Program Memory Block Switching Program memory block switching is initialized after reset according to the state of the Start-up Configuration bit SC0 and/or SC1. The SC0 and SC1 bits are programmed via an external host mode command or an IAP Mode command. See Table 4-2. Once out of reset, the SFCF[0] bit can be changed dynamically by the program for desired effects. Changing SFCF[0] will not change the SC0 bit. Caution must be taken when dynamically changing the SFCF[0] bit. Since this will cause different physical memory to be mapped to the logical program address space. The user must avoid executing block switching instructions within the address range 0000H to 1FFFH. TABLE 3-2: SFCF Values Under Different Reset Conditions
State of SFCF[1:0] after: Power-on or External Reset 00 (default) 01 10 11 WDT Reset or Brown-out Reset x0 x1 10 11
3.3 Data RAM Memory

The data RAM has 1024 bytes of internal memory. The RAM can be addressed up to 64KB for external data memory.
3.4 Expanded Data RAM Addressing

The SST89E/V5xRDx both have the capability of 1K of RAM. See Figure 3-4. The device has four sections of internal data memory: 1. The lower 128 Bytes of RAM (00H to 7FH) are directly and indirectly addressable. 2. The higher 128 Bytes of RAM (80H to FFH) are indirectly addressable. 3. The special function registers (80H to FFH) are directly addressable only. 4. The expanded RAM of 768 Bytes (00H to 2FFH) is indirectly addressable by the move external instruction (MOVX) and clearing the EXTRAM bit. (See Auxiliary Register (AUXR) in Section 3.6, Special Function Registers) Since the upper 128 bytes occupy the same addresses as the SFRs, the RAM must be accessed indirectly. The RAM and SFRs space are physically separate even though they have the same addresses. When instructions access addresses in the upper 128 bytes (above 7FH), the MCU determines whether to access the SFRs or RAM by the type of instruction given. If it is indirect, then RAM is accessed. If it is direct, then an SFR is accessed. See the examples below.
SC11 U (1) U (1) P (0) P (0)
SC01 U (1) P (0) U (1) P (0)
Software Reset 10 11 10 11
T3-2.0 1255
1. P = Programmed (Bit logic state = 0), U = Unprogrammed (Bit logic state = 1)
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Data Sheet Indirect Access: MOV@R0, #data; R0 contains 90H Register R0 points to 90H which is located in the upper address range. Data in #data is written to RAM location 90H rather than port 1. Direct Access: MOV90H, #data; write data to P1 Data in #data is written to port 1. Instructions that write directly to the address write to the SFRs. To access the expanded RAM, the EXTRAM bit must be cleared and MOVX instructions must be used. The extra 768 bytes of memory is physically located on the chip and logically occupies the first 768 bytes of external memory (addresses 000H to 2FFH). When EXTRAM = 0, the expanded RAM is indirectly addressed using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. Accessing the expanded RAM does not affect ports P0, P3.6 (WR#), P3.7 (RD#), or P2. With EXTRAM = 0, the expanded RAM can be accessed as in the following example. Expanded RAM Access (Indirect Addressing only): TABLE MOVX@DPTR, A; DPTR contains 0A0H DPTR points to 0A0H and data in A is written to address 0A0H of the expanded RAM rather than external memory. Access to external memory higher than 2FFH using the MOVX instruction will access external memory (0300H to FFFFH) and will perform in the same way as the standard 8051, with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals. When EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 8051. Using MOVX @Ri provides an 8-bit address with multiplexed data on Port 0. Other output port pins can be used to output higher order address bits. This provides external paging capabilities. Using MOVX @DPTR generates a 16-bit address. This allows external addressing up the 64K. Port 2 provides the high-order eight address bits (DPH), and Port 0 multiplexes the low order eight address bits (DPL) with data. Both MOVX @Ri and MOVX @DPTR generates the necessary read and write signals (P3.6 - WR# and P3.7 - RD#) for external memory use. Table 3-3 shows external data memory RD#, WR# operation with EXTRAM bit. The stack pointer (SP) can be located anywhere within the 256 bytes of internal RAM (lower 128 bytes and upper 128 bytes). The stack pointer may not be located in any part of the expanded RAM.
3-3: External Data Memory RD#, WR# with EXTRAM bit

MOVX @DPTR, A or MOVX A, @DPTR MOVX @Ri, A or MOVX A, @Ri ADDR = Any RD# / WR# not asserted1 RD# / WR# asserted
T3-3.0 1255
AUXR EXTRAM = 0 EXTRAM = 1
ADDR < 0300H RD# / WR# not asserted RD# / WR# asserted
ADDR >= 0300H RD# / WR# asserted RD# / WR# asserted
1. Access limited to ERAM address within 0 to 0FFH; cannot access 100H to 02FFH.
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Data Sheet
2FFH
Expanded RAM 768 Bytes
FFH
(Indirect Addressing)
FFH
(Direct Addressing) Special Function Registers (SFRs)
80H 7FH
Upper 128 Bytes Internal RAM Lower 128 Bytes Internal RAM
80H
(Indirect Addressing) 000H
00H
(Indirect & Direct Addressing)
FFFFH
(Indirect Addressing)
FFFFH
(Indirect Addressing) External Data Memory
External Data Memory
0300H 2FFH Expanded RAM 000H EXTRAM = 0 0000H EXTRAM = 1

1255 F05.0
FIGURE
3-4: Internal and External Data Memory Structure

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Data Sheet
3.5 Dual Data Pointers

The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS=0, DPTR0 is selected; when DPS=1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1. (See Figure 3-5)
AUXR1 / bit0
DPS DPTR1 DPTR0 DPH 83H DPL 82H
DPS = 0 DPTR0 DPS = 1 DPTR1
External Data Memory

1255 F06.0
FIGURE
3-5: Dual Data Pointer Organization
3.6 Special Function Registers

Most of the unique features of the FlashFlex51 microcontroller family are controlled by bits in special function registers (SFRs) located in the SFR memory map shown in Table 3-4. Individual descriptions of each SFR are provided and reset values indicated in Tables 3-5 to 3-9. TABLE
F8H F0H E8H E0H D8H D0H C8H C0H B8H B0H A8H A0H 98H 90H 88H 80H
3-4: FlashFlex51 SFR Memory Map

8 BYTES IP11 B1 IEA1 ACC1 CCON1 PSW1 T2CON1 WDTC1 IP1 P31 IE1 P21 SCON1 P11 TCON1 P01 TMOD SP TL0 DPL TL1 DPH TH0 TH1 WDTD AUXR SPDR PCON SBUF SADEN SFCF SADDR SFCM SPSR AUXR1 P4 SFAL SFAH SFDT SFST XICON IPH T2MOD RCAP2L RCAP2H TL2 CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3 SPCR TH2 CCAPM4 CL CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L CH CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H IP1H FFH F7H EFH E7H DFH D7H CFH C7H BFH B7H AFH A7H 9FH 97H 8FH 87H
T3-4.0 1255
1. Bit addressable SFRs
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Data Sheet TABLE 3-5: CPU related SFRs
Direct Address E0H F0H D0H 81H 82H 83H A8H E8H B8H B7H F8H F7H 87H 8EH A2H AEH EA SMOD1 X EC PPC PPCH SMOD0 EX3 ET2 PT2 PT2H BOF IE3 CY AC F0 Bit Address, Symbol, or Alternative Port Function MSB ACC[7:0] B[7:0] RS1 RS0 OV F1 P LSB Reset Value 00H 00H 00H 07H 00H 00H EX1 PX1 PX1H PX3 PX3H GF0 0 EX2 ET0 PT0 PT0H PX2 PX3 PD EXTRAM IE2 EX0 PX0 PX0H IDL AO DPS IT2 00H xxxx0xxxb x0000000b x0000000b xxxx0xxxb xxxx0xxxb 00010000b xxxxxxx00b xxxx00x0b 00H
T3-5.0 1255
Symbol Description ACC1 B1 PSW1 SP DPL DPH IE1 IEA1 IP1 IPH IP11 IP1H PCON AUXR AUXR1 XICON2 Accumulator B Register Program Status Word Stack Pointer Data Pointer Low Data Pointer High Interrupt Enable Interrupt Enable A Interrupt Priority Reg Interrupt Priority Reg High Interrupt Priority Reg A Interrupt Priority Reg A High Power Control Auxiliary Reg Auxiliary Reg 1 External Interrupt Control
SP[7:0] DPL[7:0] DPH[7:0] ES PS PSH POF IT3 ET1 EBO PT1 PT1H PBO PBOH GF1 GF2 0
1. Bit Addressable SFRs 2. X = Dont care
TABLE
3-6: Flash Memory Programming SFRs

Direct Address B1H B2H B3H B4H B5H B6H SB1_i SB2_i Bit Address, Symbol, or Alternative Port Function MSB FIE IAPEN FCM[6:0] LSB SWR BSEL Reset Value x0xxxx00b 00H 00H 00H 00H 000x00xxb
T3-6.0 1255
Symbol Description SFCF SFCM SFAL SFAH SFDT SFST SuperFlash Configuration SuperFlash Command SuperFlash Address Low SuperFlash Address High SuperFlash Data SuperFlash Status
SuperFlash Low Order Byte Address Register - A7 to A0 (SFAL) SuperFlash High Order Byte Address Register - A15 to A8 (SFAH) SuperFlash Data Register SB3_i EDC_i FLASH_BUSY
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Data Sheet TABLE
Symbol WDTC1 WDTD
3-7: Watchdog Timer SFRs

Description Watchdog Timer Control Watchdog Timer Data/Reload Direct Address C0H 85H Bit Address, Symbol, or Alternative Port Function MSB WDOUT WDRE WDTS WDT LSB SWDT Reset Value xxx00x00b 00H
T3-7.0 1255
Watchdog Timer Data/Reload
1. Bit Addressable SFRs
TABLE
Symbol TMOD TCON1 TH0 TL0 TH1 TL1
3-8: Timer/Counters SFRs

Description Timer/Counter Mode Control Timer/Counter Control Timer 0 MSB Timer 0 LSB Timer 1 MSB Timer 1 LSB Direct Address 89H GATE 88H 8CH 8AH 8DH 8BH C8H C9H CDH CCH CBH CAH TF2 X EXF2 RCLK TF1 Bit Address, Symbol, or Alternative Port Function MSB Timer 1 C/T# TR1 M1 TF0 M0 TR0 GATE IE1 TH0[7:0] TL0[7:0] TH1[7:0] TL1[7:0] TCLK EXEN2 TH2[7:0] TL2[7:0] RCAP2H[7:0] RCAP2L[7:0] TR2 C/T2# T2OE CP/RL2# DCEN Timer 0 C/T# IT1 M1 IE0 M0 IT0 00H 00H 00H 00H 00H 00H xxxxxx00b 00H 00H 00H 00H
T3-8.0 1255
LSB
Reset Value 00H
T2CON1 Timer / Counter 2 Control T2MOD2 Timer2 Mode Control TH2 TL2 Timer 2 MSB Timer 2 LSB
RCAP2H Timer 2 Capture MSB RCAP2L Timer 2 Capture LSB

1. Bit Addressable SFRs 2. X = Dont care
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Data Sheet TABLE 3-9: Interface SFRs
Direct Address 99H 98H A9H B9H D5H AAH 86H 80H 90H A0H B0H A5H RD# 1 WR# 1 T1 1 SPIE SPIF SPE WCOL SPDR[7:0] P0[7:0] P2[7:0] T0 1 INT1# INT0# P4.3 P4.2 TXD P4.1 RXD P4.0 T2EX T2 SM0/FE SM1 SM2 Bit Address, Symbol, or Alternative Port Function MSB SBUF[7:0] REN TB8 RB8 TI RI SADDR[7:0] SADEN[7:0] DORD MSTR CPOL CPHA SPR1 SPR0 LSB RESET Value Indeterminate 00H 00H 00H 04H 00H 00H FFH FFH FFH FFH FFH
T3-9.0 1255
Symbol Description SBUF SCON1 Serial Data Buffer Serial Port Control
SADDR Slave Address SADEN Slave Address Mask SPCR SPSR SPDR P01 P11 P21 P31 P42 SPI Control Register SPI Status Register SPI Data Register Port 0 Port 1 Port 2 Port 3 Port 4
1. Bit Addressable SFRs 2. P4 is similar to P1 and P3 ports
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Data Sheet TABLE 3-10: PCA SFRs
Symbol CH CL CCON1 CMOD Description
PCA Timer/Counter PCA Timer/Counter Control Register PCA Timer/Counter Mode Register
Direct Address MSB F9H E9H D8H D9H FAH EAH FBH EBH FCH ECH FDH EDH FEH EEH DAH DBH DCH DDH DEH CF CIDL
Bit Address, Symbol, or Alternative Port Function LSB CH[7:0] CL[7:0] CR WDTE CCF4 CCF3 CCF2 CPS1 CCF1 CPS0 CCF0 ECF
RESET Value 00H 00H 00x00000b 00xxx000b 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H
CCAP0H PCA Module 0 CCAP0L Compare/Capture Registers CCAP1H PCA Module 1 CCAP1L Compare/Capture Registers CCAP2H PCA Module 2 CCAP2L Compare/Capture Registers CCAP3H PCA Module 3 CCAP3L Compare/Capture Registers CCAP4H PCA Module 4 CCAP4L Compare/Capture Registers CCAPM0 PCA CCAPM1 Compare/Capture Module Mode CCAPM2 Registers CCAPM3 CCAPM4
1. Bit Addressable SFRs
CCAP0H[7:0] CCAP0L[7:0] CCAP1H[7:0] CCAP1L[7:0] CCAP2H[7:0] CCAP2L[7:0] CCAP3H[7:0] CCAP3L[7:0] CCAP4H[7:0] CCAP4L[7:0]
ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 x0000000b ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1 x0000000b ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2 x0000000b ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3 x0000000b ECOM4 CAPP4 CAPN4 MAT4 TOG4 PWM4 ECCF4 x0000000b
T3-10.0 1255
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Data Sheet SuperFlash Configuration Register (SFCF)
Location B1H 7 6 IAPEN 5 4 3 2 1 SWR 0 BSEL Reset Value x0xxxx00b
Symbol IAPEN
Function Enable IAP operation 0: IAP commands are disabled 1: IAP commands are enabled Software Reset See Section 10.2, Software Reset Program memory block switching bit See Figures 3-1 through 3-3 and Table 3-2
SWR BSEL
SuperFlash Command Register (SFCM)

Location B2H 7 FIE 6 FCM6 5 FCM5 4 FCM4 3 FCM3 2 FCM2 1 FCM1 0 FCM0 Reset Value 00H
Symbol FIE
Function Flash Interrupt Enable. 0: INT1# is not reassigned. 1: INT1# is re-assigned to signal IAP operation completion. External INT1# interrupts are ignored. Flash operation command 000_0001b Chip-Erase 000_1011b Sector-Erase 000_1101b Block-Erase 000_1100b Byte-Verify1 000_1110b Byte-Program 000_1111b Prog-SB1 000_0011b Prog-SB2 000_0101b Prog-SB3 000_1001b Prog-SC0 000_1001b Prog-SC1 000_1000bEnable-Clock-Double All other combinations are not implemented, and reserved for future use.
1. Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of FIE.
FCM[6:0]
SuperFlash Address Registers (SFAL)

Location B3H 7 6 5 4 3 2 1 0 Reset Value 00H SuperFlash Low Order Byte Address Register
Symbol SFAL
Function Mailbox register for interfacing with flash memory block. (Low order address register).
SuperFlash Address Registers (SFAH)

Location B4H 7 6 5 4 3 2 1 0 Reset Value 00H SuperFlash High Order Byte Address Register
Symbol SFAH
Function Mailbox register for interfacing with flash memory block. (High order address register).
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Data Sheet SuperFlash Data Register (SFDT)
Location B5H 7 6 5 4 3 2 1 0 Reset Value 00H SuperFlash Data Register
Symbol SFDT
Function Mailbox register for interfacing with flash memory block. (Data register).
SuperFlash Status Register (SFST) (Read Only Register)

Location B6H 7 SB1_i 6 SB2_i 5 SB3_i 4 3 EDC_i 2
FLASH_BUSY
1 -
0 -
Reset Value xxxxx0xxb
Symbol SB1_i SB2_i SB3_i EDC_i
Function Security Bit 1 status (inverse of SB1 bit) Security Bit 2 status (inverse of SB2 bit) Security Bit 3 status (inverse of SB3 bit) Please refer to Table 9-1 for security lock options. Double Clock Status 0: 12 clocks per machine cycle 1: 6 clocks per machine cycle
FLASH_BUSY Flash operation completion polling bit. 0: Device has fully completed the last IAP command. 1: Device is busy with flash operation.
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Data Sheet Interrupt Enable (IE)
Location A8H 7 EA 6 EC 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Reset Value 00H
Symbol EA
Function Global Interrupt Enable. 0 = Disable 1 = Enable PCA Interrupt Enable. Timer 2 Interrupt Enable. Serial Interrupt Enable. Timer 1 Interrupt Enable. External 1 Interrupt Enable. Timer 0 Interrupt Enable. External 0 Interrupt Enable.
EC ET2 ES ET1 EX1 ET0 EX0 Interrupt Enable A (IEA)

Location E8H 7 -
6 -
5 -
4 -
3 EBO
2 -
1 -
0 -
Reset Value xxxx0xxxb
Symbol EBO
Function Brown-out Interrupt Enable. 1 = Enable the interrupt 0 = Disable the interrupt
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Data Sheet Interrupt Priority (IP)
Location B8H 7 6 PPC 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 Reset Value x0000000b
Symbol PPC PT2 PS PT1 PX1 PT0 PX0
Function PCA interrupt priority bit Timer 2 interrupt priority bit Serial Port interrupt priority bit Timer 1 interrupt priority bit External interrupt 1 priority bit Timer 0 interrupt priority bit External interrupt 0 priority bit
Interrupt Priority High (IPH)

Location B7H 7 6 PPCH 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H Reset Value x0000000b
Symbol PPCH PT2H PSH PT1H PX1H PT0H PX0H Interrupt Priority 1 (IP1)
Location F8H 7 1
Function PCA interrupt priority bit high Timer 2 interrupt priority bit high Serial Port interrupt priority bit high Timer 1 interrupt priority bit high External interrupt 1 priority bit high Timer 0 interrupt priority bit high External interrupt 0 priority bit high
6 -
5 -
4 1
3 PBO
2 PX3
1 PX2
0 1
Reset Value 1xx10001b
Symbol PBO PX2 PX3
Function Brown-out interrupt priority bit External Interrupt 2 priority bit External Interrupt 3 priority bit
Interrupt Priority 1 High (IP1H)

Location F7H 7 1 6 5 4 1 3 PBOH 2 PX3H 1 PX2H 0 1 Reset Value 1xx10001b
Symbol PBOH PX2H PX3H
Function Brown-out Interrupt priority bit high External Interrupt 2 priority bit high External Interrupt 3 priority bit high
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Data Sheet Auxiliary Register (AUXR)
Location 8EH 7 6 5 4 3 2 1 EXTRAM 0 AO Reset Value xxxxxx00b
Symbol EXTRAM
Function Internal/External RAM access 0: Internal Expanded RAM access within range of 00H to 2FFH using MOVX @Ri / @DPTR. Beyond 300H, the MCU always accesses external data memory. For details, refer to Section 3.4, Expanded Data RAM Addressing . 1: External data memory access. Disable/Enable ALE 0: ALE is emitted at a constant rate of 1/3 the oscillator frequency in 6 clock mode, 1/6 fOSC in 12 clock mode. 1: ALE is active only during a MOVX or MOVC instruction.
AO
Auxiliary Register 1 (AUXR1)

Location A2H 7 6 5 4 3 GF2 2 0 1 0 DPS Reset Value xxxx00x0b
Symbol GF2 DPS
Function General purpose user-defined flag. DPTR registers select bit. 0: DPTR0 is selected. 1: DPTR1 is selected.
Watchdog Timer Control Register (WDTC)

Location C0H 7 6 5 4 WDOUT 3 WDRE 2 WDTS 1 WDT 0 SWDT Reset Value xxx00000b
Symbol WDOUT
Function Watchdog output enable. 0: Watchdog reset will not be exported on Reset pin. 1: Watchdog reset if enabled by WDRE, will assert Reset pin for 32 clocks. Watchdog timer reset enable. 0: Disable watchdog timer reset. 1: Enable watchdog timer reset. Watchdog timer reset flag. 0: External hardware reset or power-on reset clears the flag. Flag can also be cleared by writing a 1. Flag survives if chip reset happened because of watchdog timer overflow. 1: Hardware sets the flag on watchdog overflow. Watchdog timer refresh. 0: Hardware resets the bit when refresh is done. 1: Software sets the bit to force a watchdog timer refresh. Start watchdog timer. 0: Stop WDT. 1: Start WDT.
WDRE
WDTS
WDT
SWDT
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Data Sheet Watchdog Timer Data/Reload Register (WDTD)
Location 85H 7 6 5 4 3 2 1 0 Reset Value 00H Watchdog Timer Data/Reload
Symbol WDTD
Function Initial/Reload value in Watchdog Timer. New value wont be effective until WDT is set.
PCA Timer/Counter Control Register1 (CCON)

Location D8H 7 CF
1. Bit addressable
6 CR
5 -
4 CCF4
3 CCF3
2 CCF2
1 CCF1
0 CCF0
Reset Value 00x00000b
Symbol CF
Function PCA Counter Overflow Flag Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software, but can only cleared by software. PCA Counter Run control bit Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. Not implemented, reserved for future use.
Note: User should not write 1s to reserved bits. The value read from a reserved bit is indeterminate.
CR
CCF4 CCF3 CCF2 CCF1 CCF0
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
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Data Sheet PCA Timer/Counter Mode Register1 (CMOD)
Location D9H 7 CIDL 6 WDTE 5 4 3 2 CPS1 1 CPS0 0 ECF Reset Value 00xxx000b
1. Not bit addressable
Symbol CIDL
Function Counter Idle Control: 0: Programs the PCA Counter to continue functioning during idle mode 1: Programs the PCA Counter to be gated off during idle Watchdog Timer Enable: 0: Disables Watchdog Timer function on PCA module 4 1: Enables Watchdog Timer function on PCA module 4 Not implemented, reserved for future use.
WDTE
CPS1 CPS0
PCA Count Pulse Select bit 1 PCA Count Pulse Select bit 2
Selected PCA Input1 0 1 2 3
Internal clock, fOSC/6 in 6 clock mode (fOSC/12 in 12 clock mode) Internal clock, fOSC/2 in 6 clock mode (fOSC/4 in 12 clock mode) Timer 0 overflow External clock at ECI/P1.2 pin (max. rate = fOSC/4 in 6 clock mode, fOSC/8 in 12 clock mode) 1. fOSC = oscillator frequency
CPS1 CPS0 0 0 1 1 0 1 0 1
ECF
PCA Enable Counter Overflow interrupt: 0: Disables the CF bit in CCON 1: Enables CF bit in CCON to generate an interrupt
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Data Sheet PCA Compare/Capture Module Mode Register1 (CCAPMn)
Location DAH DBH DCH DDH DEH 7 6 ECOM0 ECOM1 ECOM2 ECOM3 ECOM4 5 CAPP0 CAPP1 CAPP2 CAPP3 CAPP4 4 CAPN0 CAPN1 CAPN2 CAPN3 CAPN4 3 MAT0 MAT1 MAT2 MAT3 MAT4 2 TOG0 TOG1 TOG2 TOG3 TOG4 1 PWM0 PWM1 PWM2 PWM3 PWM4 0 ECCF0 ECCF1 ECCF2 ECCF3 ECCF4 Reset Value 00xxx000b 00xxx000b 00xxx000b 00xxx000b 00xxx000b
1. Not bit addressable
Symbol ECOMn
Function Not implemented, reserved for future use.

Enable Comparator 0: Disables the comparator function 1: Enables the comparator function Capture Positive 0: Disables positive edge capture on CEX[4:0] 1: Enables positive edge capture on CEX[4:0] Capture Negative 0: Disables negative edge capture on CEX[4:0] 1: Enables negative edge capture on CEX[4:0] Match: Set ECOM[4:0] and MAT[4:0] to implement the software timer mode 0: Disables software timer mode 1: A match of the PCA counter with this modules compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. Toggle 0: Disables toggle function 1: A match of the PCA counter with this modules compare/capture register causes the the CEXn pin to toggle. Pulse Width Modulation mode 0: Disables PWM mode 1: Enables CEXn pin to be used as a pulse width modulated output Enable CCF Interrupt 0: Disables compare/capture flag CCF[4:0] in the CCON register to generate an interrupt request. 1: Enables compare/capture flag CCF[4:0] in the CCON register to generate an interrupt request.
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
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Data Sheet SPI Control Register (SPCR)
Location D5H 7 SPIE 6 SPE 5 DORD 4 MSTR 3 CPOL 2 CPHA 1 SPR1 0 SPR0 Reset Value 00H
Symbol SPIE SPE
Function If both SPIE and ES are set to one, SPI interrupts are enabled. SPI enable bit. 0: Disables SPI. 1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1.4, P1.5, P1.6, P1.7. Data Transmission Order. 0: MSB first in data transmission. 1: LSB first in data transmission. Master/Slave select. 0: Selects Slave mode. 1: Selects Master mode. Clock Polarity 0: SCK is low when idle (Active High). 1: SCK is high when idle (Active Low). Clock Phase control bit. The CPHA bit with the CPOL bit control the clock and data relationship between master and slave. See Figures 6-5 and 6-6. 0: Shift triggered on the leading edge of the clock. 1: Shift triggered on the trailing edge of the clock. SPI Clock Rate Select bits. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the oscillator frequency, fOSC, is as follows:
SPR1 0 0 1 1 SPR0 0 1 0 1 SCK = fOSC divided by 4 16 64 128
DORD
MSTR
CPOL
CPHA
SPR1, SPR0
SPI Status Register (SPSR)

Location AAH 7 SPIF 6 WCOL 5 4 3 2 1 0 Reset Value 00xxxxxxb
Symbol SPIF
Function SPI Interrupt Flag. Upon completion of data transfer, this bit is set to 1. If SPIE =1 and ES =1, an interrupt is then generated. This bit is cleared by software. Write Collision Flag. Set if the SPI data register is written to during data transfer. This bit is cleared by software.
WCOL
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Data Sheet SPI Data Register (SPDR)
Location 86H 7 6 5 4 SPDR[7:0] 3 2 1 0 Reset Value 00H
Power Control Register (PCON)

Location 87H 7 SMOD1 6 SMOD0 5 BOF 4 POF 3 GF1 2 GF0 1 PD 0 IDL Reset Value 00010000b
Symbol SMOD1 SMOD0
Function Double Baud rate bit. If SMOD1 = 1, Timer 1 is used to generate the baud rate, and the serial port is used in modes 1, 2, and 3. FE/SM0 Selection bit. 0: SCON[7] = SM0 1: SCON[7] = FE, Brown-out detection status bit, this bit will not be affected by any other reset. BOF should be cleared by software. Power-on reset will also clear the BOF bit. 0: No brown-out. 1: Brown-out occurred Power-on reset status bit, this bit will not be affected by any other reset. POF should be cleared by software. 0: No Power-on reset. 1: Power-on reset occurred General-purpose flag bit. General-purpose flag bit. Power-down bit, this bit is cleared by hardware after exiting from power-down mode. 0: Power-down mode is not activated. 1: Activates Power-down mode. Idle mode bit, this bit is cleared by hardware after exiting from idle mode. 0: Idle mode is not activated. 1: Activates idle mode.
BOF
POF
GF1 GF0 PD
IDL
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Data Sheet Serial Port Control Register (SCON)
Location 98H 7 SM0/FE 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI Reset Value 00000000b
Symbol FE
Function Set SMOD0 = 1 to access FE bit. 0: No framing error 1: Framing Error. Set by receiver when an invalid stop bit is detected. This bit needs to be cleared by software. SMOD0 = 0 to access SM0 bit. Serial Port Mode Bit 0 Serial Port Mode Bit 1
SM0 0 0 1 SM1 0 1 0 Mode 0 1 2 Description Shift Register 8-bit UART 9-bit UART Baud Rate1 fOSC/6 (6 clock mode) or fOSC/12 (12 clock mode) Variable fOSC/32 or fOSC/16 (6 clock mode) or fOSC/64 or fOSC/32 (12 clock mode) Variable
SM0 SM1
9-bit UART
1. fOSC = oscillator frequency
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then RI will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a given or broadcast address. In Mode 1, if SM2 = 1 then RI will not be activated unless a valid stop bit was received. In Mode 0, SM2 should be 0. Enables serial reception. 0: to disable reception. 1: to enable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission, Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
REN
TB8 RB8 TI
RI
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Data Sheet Timer/Counter 2 Control Register (T2CON)
Location C8H 7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2# Reset Value 00H
Symbol TF2 EXF2
Function Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflow to be used for the transmit clock. Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/stop control for Timer 2. A logic 1 starts the timer. Timer or counter select (Timer 2) 0: Internal timer (OSC/6 in 6 clock mode, OSC/12 in 12 clock mode) 1: External event counter (falling edge triggered) Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
RCLK
TCLK
EXEN2
TR2 C/T2#
CP/RL2#
Timer/Counter 2 Mode Control (T2MOD)

Location C9H 7 X 6 5 4 3 2 1 T2OE 0 DCEN Reset Value xxxxxx00b
Symbol X T2OE DCEN
Function Dont Care Not implemented, reserved for future use.

Timer 2 Output Enable bit. Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.
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Data Sheet External Interrupt Control (XICON)
Location AEH 7 X 6 EX3 5 IE3 4 IT3 3 0 2 EX2 1 IE2 0 IT2 Reset Value 00H
Symbol X EX2 IE2
Function Dont Care External Interrupt 2 Enable bit if set Interrupt Enable If IT2=1, IE2 is set/cleared automatically by hardware when interrupt is detected/ serviced. External Interrupt 2 is falling-edge/low-level triggered when this bit is cleared by software. External Interrupt 3 Enable bit if set Interrupt Enable If IT3=1, IE3 is set/cleared automatically by hardware when interrupt is detected/ serviced. External Interrupt3 is falling-edge/low-level triggered when this bit is cleared by software.
IT2 EX3 IE3
IT3
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Data Sheet
4.0 FLASH MEMORY PROGRAMMING

The device internal flash memory can be programmed or erased using the In-Application Programming (IAP) mode. 4.2.2 Memory Bank Selection for In-Application Programming Mode With the addressing range limited to 16 bit, only 64 KByte of program address space is visible at any one time. The bank selection (the configuration of EA# and SFCF[1:0]), allows Block 1 memory to be overlaid on the lowest 8 KByte of Block 0 memory, making Block 1 reachable. The same concept is employed to allow both Block 0 and Block 1 flash to be accessible to IAP operations. Code from a block that is not visible may not be used as a source to program another address. However, a block that is not visible may be programmed by code from the other block through mailbox registers. The device allows IAP code in one block of memory to program the other block of memory, but may not program any location in the same block. If an IAP operation originates physically from Block 0, the target of this operation is implicitly defined to be in Block 1. If the IAP operation originates physically from Block 1, then the target address is implicitly defined to be in Block 0. If the IAP operation originates from external program space, then, the target will depend on the address and the state of bank selection. 4.2.3 IAP Enable Bit The IAP enable bit, SFCF[6], enables in-application programming mode. Until this bit is set, all flash programming IAP commands will be ignored. 4.2.4 In-Application Programming Mode Commands All of the following commands can only be initiated in the IAP mode. In all situations, writing the control byte to the SFCM register will initiate all of the operations. All commands will not be enabled if the security locks are enabled on the selected memory block. The Program command is for programming new data into the memory array. The portion of the memory array to be programmed should be in the erased state, FFH. If the memory is not erased, it should first be erased with an appropriate Erase command. Warning: Do not attempt to write (program or erase) to a block that the code is currently fetching from. This will cause unpredictable program behavior and may corrupt program data.
4.1 Product Identification

The Read-ID command accesses the Signature Bytes that identify the device and the manufacturer as SST. External programmers primarily use these Signature Bytes in the selection of programming algorithms. TABLE 4-1: Product Identification
Address Manufacturers ID Device ID SST89E52RD2/RD SST89V52RD2/RD SST89E54RD2/RD SST89V54RD2/RD SST89E58RD2/RD SST89V58RD2/RD 31H 31H 31H 31H 31H 31H 9DH 9CH 9FH 9EH 9BH 9AH
T4-1.2 1255
Data BFH
30H
4.2 In-Application Programming Mode

The device offers either 16/24/40 KByte of in-application programmable flash memory. During in-application programming, the CPU of the microcontroller enters IAP mode. The two blocks of flash memory allow the CPU to execute user code from one block, while the other is being erased or reprogrammed concurrently. The CPU may also fetch code from an external memory while all internal flash is being reprogrammed. The mailbox registers (SFST, SFCM, SFAL, SFAH, SFDT and SFCF) located in the special function register (SFR), control and monitor the devices erase and program process. Table 4-2 outline the commands and their associated mailbox register settings. 4.2.1 In-Application Programming Mode Clock Source During IAP mode, both the CPU core and the flash controller unit are driven off the external clock. However, an internal oscillator will provide timing references for Program and Erase operations. The internal oscillator is only turned on when required, and is turned off as soon as the flash operation is completed.
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Data Sheet 4.2.4.1 Chip-Erase The Chip-Erase command erases all bytes in both memory blocks. This command is only allowed when EA#=0 (external memory execution). Additionally this command is not permitted when the device is in level 4 locking. In all other instances, this command ignores the Security Lock status and will erase the security lock bits and re-map bits.
IAP Enable ORL SFCF, #40H
Erase Block 0 MOV SFAH, #00H
OR
Erase Block 1 MOV SFAH, #F0H
Set-Up MOV SFDT, #55H
Set-Up MOV SFDT, #55H Polling scheme MOV SFCM, #0DH Polling scheme MOV SFCM, #01H Interrupt scheme MOV SFCM, #81H Interrupt scheme MOV SFCM, #8DH
SFST[2] indicates operation completion
INT1 interrupt indicates completion

1255 F09.0

1255 F08.0
FIGURE
4-2: Block-Erase
FIGURE
4-1: Chip-Erase
4.2.4.2 Block-Erase The Block-Erase command erases all bytes in one of the two memory blocks (Block 0 or Block 1). The selection of the memory block to be erased is determined by the (SFAH[7]) of the SuperFlash Address Register. For SST89x5xRD2/RD, if SFAH[7] = 0b, the primary flash memory Block 0 is selected. If SFAH[7:4] = EH, the secondary flash memory Block 1 is selected. The Block-Erase command sequence for SST89x5xRD2/RD is as follows:
4.2.4.3 Sector-Erase The Sector-Erase command erases all of the bytes in a sector. The sector size for the flash memory blocks is 128 Bytes. The selection of the sector to be erased is determined by the contents of SFAH and SFAL.
Program sector address MOV SFAH, #sector_addressH MOV SFAL, #sector_addressL
Polling scheme MOV SFCM, #0BH
Interrupt scheme MOV SFCM, #8BH

1255 F10.0
FIGURE
4-3: Sector-Erase
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Data Sheet 4.2.4.4 Byte-Program The Byte-Program command programs data into a single byte. The address is determined by the contents of SFAH and SFAL. The data byte is in SFDT.
Program byte address MOV SFAH, #byte_addressH MOV SFAL, #byte_addressL
Program byte address MOV SFAH, #byte_addressH MOV SFAL, #byte_addressL
MOV SFCM, #0CH
SFDT register contains data Move data to SFDT MOV SFDT, #data
1255 F12.0
FIGURE
Polling scheme MOV SFCM, #0EH Interrupt scheme MOV SFCM, #8EH
4-5: Byte-Verify

1255 F11.0
4.2.4.6 Prog-SB3, Prog-SB2, Prog-SB1 Prog-SB3, Prog-SB2, Prog-SB1 commands are used to program the security bits (see Table 9-1). Completion of any of these commands, the security options will be updated immediately. Security bits previously in un-programmed state can be programmed by these commands. Prog-SB3, Prog-SB2 and Prog-SB1 commands should only reside in Block 1 or external code memory.
FIGURE
4-4: Byte-Program
4.2.4.5 Byte-Verify The Byte-Verify command allows the user to verify that the device has correctly performed an Erase or Program command. Byte-Verify command returns the data byte in SFDT if the command is successful. The user is required to check that the previous flash operation has fully completed before issuing a Byte-Verify. Byte-Verify command execution time is short enough that there is no need to poll for command completion and no interrupt is generated.
Set-Up MOV SFDT, #0AAH
Program SB1 MOV SFCM, #0FH or MOV SFCM, #8FH
OR
Program SB2 MOV SFCM, #03H or MOV SFCM, #83H
OR
Program SB3 MOV SFCM, #05H or MOV SFCM, #85H
Polling SFST[2] indicates completion
INT1# Interrupt indicates completion

1255 F13.0
FIGURE
4-6: Prog-SB3, Prog-SB2, Prog-SB1
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Data Sheet 4.2.4.7 Prog-SC0, Prog-SC1 Prog-SC0 command is used to program the SC0 bit. This command only changes the SC0 bit and has no effect on BSEL bit until after a reset cycle. SC0 bit previously in un-programmed state can be programmed by this command. The Prog-SC0 command should reside only in Block 1 or external code memory. Prog-SC1 command is used to program the SC1 bit. This command only changes the SC1 bit and has no effect on SFCF[1] bit until after a reset cycle. SC1 bit previously in un-programmed state can be programmed by this command. The Prog-SC1 command should reside only in Block 1 or external code memory.
Set-up Enable-Clock-Double MOV SFAH, #55H MOV SFDT, #0AAH
Program Enable-Clock-Double Polling scheme MOV SFCM, #08H
Program Enable-Clock-Double Interrupt scheme MOV SFCM, #88H

1255 F15.0
FIGURE 4.2.5 Polling
4-8: Enable-Clock-Double
Set-up Program SC0 MOV SFAH, #5AH MOV SFDT, #0AAH
Set-up Program SC1 MOV SFAH, #0AAH MOV SFDT, #0AAH
A command that uses the polling method to detect flash operation completion should poll on the FLASH_BUSY bit (SFST[2]). When FLASH_BUSY de-asserts (logic 0), the device is ready for the next operation. MOVC instruction may also be used for verification of the Programming and Erase operation of the flash memory. MOVC instruction will fail if it is directed at a flash block that is still busy. 4.2.6 Interrupt Termination If interrupt termination is selected, (SFCM[7] is set), then an interrupt (INT1) will be generated to indicate flash operation completion. Under this condition, the INT1 becomes an internal interrupt source. The INT1# pin can now be used as a general purpose port pin and it cannot be the source of External Interrupt 1 during in-application programming. In order to use an interrupt to signal flash operation termination. EX1 and EA bits of IE register must be set. The IT1 bit of TCON register must also be set for edge trigger detection.
Program SC0 or SC1 Polling scheme MOV SFCM, #09H
Program SC0 or SC1 Interrupt scheme MOV SFCM, #89H

1255 F14.0
FIGURE
4-7: Prog-SC0 and Prog-SC1
4.2.4.8 Enable-Clock-Double Enable-Clock-Double command is used to make the MCU run at 6 clocks per machine cycle. The standard (default) is 12 clocks per machine cycle (i.e. clock double command disabled).
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Data Sheet TABLE
Operation Chip-Erase3 Block-Erase Sector-Erase Byte-Program Byte-Verify Prog-SB19 Prog-SB29 Prog-SB39 Prog-SC09 Prog-SC19 Enable-Clock-Double9 (Read)8
4-2: IAP Commands1

SFCM [6:0]2 01H 0DH 0BH 0EH 0CH 0FH 03H 05H 09H 09H 08H SFDT [7:0] 55H 55H X DI7 DO7 AAH AAH AAH AAH AAH AAH SFAH [7:0] X4 AH5 AH AH AH X X X 5AH AAH 55H SFAL [7:0] X X AL6 AL AL X X X X X X
T4-2.0 1255
1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands. 2. Interrupt/Polling enable for flash operation completion SFCM[7] = 1: Interrupt enable for flash operation completion 0: polling enable for flash operation completion 3. Chip-Erase only functions in IAP mode when EA#=0 (external memory execution) and device is not in level 4 locking. 4. X can be VIL or VIH, but no other value. 5. AH = Address high order byte 6. AL = Address low order byte 7. DI = Data Input, DO = Data Output, all other values are in hex. 8. SFAH[7:5] = 111b selects Block 1, SFAH[7] = 0b selects Block 0 9. Instruction must be located in Block 1 or external code memory. Note: DISIAPL pin in PLCC or TQFP will also disable IAP commands if it is externally pulled low when reset.
5.0 TIMERS/COUNTERS 5.1 Timers

The device has three 16-bit registers that can be used as either timers or event counters. The three timers/counters are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2). Each is designated a pair of 8-bit registers in the SFRs. The pair consists of a most significant (high) byte and least significant (low) byte. The respective registers are TL0, TH0, TL1, TH1, TL2, and TH2.
TABLE
5-1: Timer/Counter 0
TMOD Mode 0 Function 13-bit Timer 16-bit Timer 8-bit Auto-Reload Two 8-bit Timers 13-bit Timer 16-bit Timer 8-bit Auto-Reload Two 8-bit Timers Internal Control1 00H 01H 02H 03H 04H 05H 06H 07H External Control2 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH
T5-1.0 1255
Used as Timer
1 2 3 0
5.2 Timer Set-up

Refer to Table 3-8 for TMOD, TCON, and T2CON registers regarding timers T0, T1, and T2. The following tables provide TMOD values to be used to set up Timers T0, T1, and T2. Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set separately to turn the timer on.
Used as Counter
1 2 3
1. The Timer is turned ON/OFF by setting/clearing bit TR0 in the software. 2. The Timer is turned ON/OFF by the 1 to 0 transition on INT0# (P3.2) when TR0 = 1 (hardware control).
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Data Sheet TABLE 5-2: Timer/Counter 1
TMOD Mode 0 Used as Timer 1 2 3 0 Used as Counter 1 2 3 Function 13-bit Timer 16-bit Timer 8-bit Auto-Reload Does not run 13-bit Timer 16-bit Timer 8-bit Auto-Reload Not available Internal Control1 00H 10H 20H 30H 40H 50H 60H External Control2 80H 90H A0H B0H C0H D0H E0H T5-2.0 1255
5.3 Programmable Clock-Out

A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: 1. to input the external clock for Timer/Counter 2, or 2. to output a 50% duty cycle clock ranging from 122 Hz to 8 MHz at a 16 MHz operating frequency (61 Hz to 4 MHz in 12 clock mode). To configure Timer/Counter 2 as a clock generator, bit C/#T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: Oscillator Frequency n x (65536 - RCAP2H, RCAP2L)
T2CON
1. The Timer is turned ON/OFF by setting/clearing bit TR1 in the software. 2. The Timer is turned ON/OFF by the 1 to 0 transition on INT1# (P3.3) when TR1 = 1 (hardware control).
TABLE
5-3: Timer/Counter 2
Internal Control1 00H 01H 34H External Control2 08H 09H 36H
n=
2 (in 6 clock mode) 4 (in 12 clock mode)
Mode 16-bit Auto-Reload 16-bit Capture Used as Timer Baud rate generator receive and transmit same baud rate Receive only Transmit only Used as Counter 16-bit Auto-Reload 16-bit Capture
Where (RCAP2H, RCAP2L) = the contents of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. In the Clock-Out mode, Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will not be the same.
24H 14H 02H 03H
26H 16H 0AH 0BH

T5-3.0 1255
1. Capture/Reload occurs only on timer/counter overflow. 2. Capture/Reload occurs on timer/counter overflow and a 1 to 0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generating mode.
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Data Sheet
6.0 SERIAL I/O 6.1 Full-Duplex, Enhanced UART

The device serial I/O port is a full-duplex port that allows data to be transmitted and received simultaneously in hardware by the transmit and receive registers, respectively, while the software is performing other tasks. The transmit and receive registers are both located in the Serial Data Buffer (SBUF) special function register. Writing to the SBUF register loads the transmit register, and reading from the SBUF register obtains the contents of the receive register. The UART has four modes of operation which are selected by the Serial Port Mode Specifier (SM0 and SM1) bits of the Serial Port Control (SCON) special function register. In all four modes, transmission is initiated by any instruction that uses the SBUF register as a destination register. Reception is initiated in mode 0 when the Receive Interrupt (RI) flag bit of the Serial Port Control (SCON) SFR is cleared and the Reception Enable/ Disable (REN) bit of the SCON register is set. Reception is initiated in the other modes by the incoming start bit if the REN bit of the SCON register is set. 6.1.1 Framing Error Detection Framing Error Detection is a feature, which allows the receiving controller to check for valid stop bits in modes 1, 2, or 3. Missing stops bits can be caused by noise in serial lines or from simultaneous transmission by two CPUs. Framing Error Detection is selected by going to the PCON register and changing SMOD0 = 1 (see Figure 6-1). If a stop bit is missing, the Framing Error bit (FE) will be set. Software may examine the FE bit after each reception to check for data errors. After the FE bit has been set, it can only be cleared by software. Valid stop bits do not clear FE. When FE is enabled, RI rises on the stop bit, instead of the last data bit (see Figure 6-2 and Figure 6-3).
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
SCON
(98H)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD0 = 0) SMOD1 SMOD0 BOF POF GF1 GF0 PD IDL
PCON
(87H)
To UART framing error control

1255 F16.0
FIGURE
6-1: Framing Error Block Diagram
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Data Sheet
RXD
D0 Start bit
D1
D2
D3
D4
D5
D6
D7 Stop bit
Data byte
RI SMOD0=X FE SMOD0=1
1255 F17.0
FIGURE
6-2: UART Timings in Mode 1
RXD
D0 Start bit
D1
D2
D3
D4
D5
D6
D7
D8 Ninth bit Stop bit
Data byte
RI SMOD0=0 RI SMOD0=1 FE SMOD0=1

1255 F18.0
FIGURE
6-3: UART Timings in Modes 2 and 3
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Data Sheet 6.1.2 Automatic Address Recognition Automatic Address Recognition helps to reduce the MCU time and power required to talk to multiple serial devices. Each device is hooked together sharing the same serial link with its own address. In this configuration, a device is only interrupted when it receives its own address, thus eliminating the software overhead to compare addresses. This same feature helps to save power because it can be used in conjunction with idle mode to reduce the systems overall power consumption. Since there may be multiple slaves hooked up serial to one master, only one slave would have to be interrupted from idle mode to respond to the masters transmission. Automatic Address Recognition (AAR) allows the other slaves to remain in idle mode while only one is interrupted. By limiting the number of interruptions, the total current draw on the system is reduced. There are two ways to communicate with slaves: a group of them at once, or all of them at once. To communicate with a group of slaves, the master sends out an address called the given address. To communicate with all the slaves, the master sends out an address called the broadcast address. AAR can be configured as mode 2 or 3 (9-bit modes) and setting the SM2 bit in SCON. Each slave has its own SM2 bit set waiting for an address byte (9th bit = 1). The Receive Interrupt (RI) flag will only be set when the received byte matches either the given address or the broadcast address. Next, the slave then clears its SM2 bit to enable reception of the data bytes (9th bit = 0) from the master. When the 9th bit = 1, the master is sending an address. When the 9th bit = 0, the master is sending actual data. If mode 1 is used, the stop bit takes the place of the 9th bit. Bit RI is set only when the received command frame address matches the devices address and is terminated by a valid stop bit. Note that mode 0 cannot be used. Setting SM2 bit in the SCON register in mode 0 will have no effect. Each slaves individual address is specified by SFR SADDR. SFR SADEN is a mask byte that defines dont care bits to form the given address when combined with SADDR. See the example below:
Slave 1 SADDR = SADEN = GIVEN 1111 0001 1111 1010 Slave 3 SADDR = 1111 1001 SADEN = 1111 0101 GIVEN = 1111 X0X1 Slave 2 SADDR = SADEN = GIVEN 1111 0011 1111 1001
= 1111 0XX1
6.1.2.1 Using the Given Address to Select Slaves Any bits masked off by a 0 from SADEN become a dont care bit for the given address. Any bit masked off by a 1, becomes ANDED with SADDR. The dont cares provide flexibility in the user-defined addresses to address more slaves when using the given address. Shown in the example above, Slave 1 has been given an address of 1111 0001 (SADDR). The SADEN byte has been used to mask off bits to a given address to allow more combinations of selecting Slave 1 and Slave 2. In this case for the given addresses, the last bit (LSB) of Slave 1 is a dont care and the last bit of Slave 2 is a 1. To communicate with Slave 1 and Slave 2, the master would need to send an address with the last bit equal to 1 (e.g. 1111 0001) since Slave 1s last bit is a dont care and Slave 2s last bit has to be a 1. To communicate with Slave 1 alone, the master would send an address with the last bit equal to 0 (e.g. 1111 0000), since Slave 2s last bit is a 1. See the table below for other possible combinations.
Select Slave 1 Only Slave 1 Given Address 1111 0X0X Possible Addresses 1111 0000 1111 0100
Select Slave 2 Only Slave 2 Given Address 1111 0XX1 Possible Addresses 1111 0111 1111 0011
Select Slaves 1 and 2 Slaves 1 and 2 Possible Addresses 1111 0001 1111 0101
If the user added a third slave such as the example below:
= 1111 0X0X
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Data Sheet
Select Slave 3 Only Slave 2 Given Address 1111 X0X1 Possible Addresses 1111 1011 1111 1001
6.2 Serial Peripheral Interface

6.2.1 SPI Features Master or slave operation 10 MHz bit frequency (max) LSB first or MSB first data transfer Four programmable bit rates End of transmission (SPIF) Write collision flag protection (WCOL) Wake up from idle mode (slave mode only)
The user could use the possible addresses above to select slave 3 only. Another combination could be to select slave 2 and 3 only as shown below.
Select Slaves 2 and 3 Only Slaves 2 and 3 Possible Addresses 1111 0011
6.2.2 SPI Description The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the SST89E/V5xRDx and peripheral devices or between several SST89E/V5xRDx devices. Figure 6-4 shows the correspondence between master and slave SPI devices. The SCK pin is the clock output and input for the master and slave modes, respectively. The SPI clock generator will start following a write to the master devices SPI data register. The written data is then shifted out of the MOSI pin on the master device into the MOSI pin of the slave device. Following a complete transmission of one byte of data, the SPI clock generator is stopped and the SPIF flag is set. An SPI interrupt request will be generated if the SPI Interrupt Enable bit (SPIE) and the Serial Port Interrupt Enable bit (ES) are both set. An external master drives the Slave Select input pin, SS#/ P1[4], low to select the SPI module as a slave. If SS#/P1[4] has not been driven low, then the slave SPI unit is not active and the MOSI/P1[5] port can also be used as an input port pin. CPHA and CPOL control the phase and polarity of the SPI clock. Figures 6-5 and 6-6 show the four possible combinations of these two bits.
More than one slave may have the same SADDR address as well, and a given address could be used to modify the address so that it is unique. 6.1.2.2 Using the Broadcast Address to Select Slaves Using the broadcast address, the master can communicate with all the slaves at once. It is formed by performing a logical OR of SADDR and SADEN with 0s in the result treated as dont cares.
Slave 1 1111 0001 = SADDR +1111 1010 = SADEN 1111 1X11 = Broadcast
Dont cares allow for a wider range in defining the broadcast address, but in most cases, the broadcast address will be FFH. On reset, SADDR and SADEN are 0. This produces an given address of all dont cares as well as a broadcast address of all dont cares. This effectively disables Automatic Addressing mode and allows the microcontroller to function as a standard 8051, which does not make use of this feature.
MSB Master LSB 8-bit Shift Register
MISO MISO
MSB Slave LSB 8-bit Shift Register
MOSI MOSI
SPI Clock Generator
SCK SS#
SCK SS#
1255 F19.0
VDD VSS
FIGURE
6-4: SPI Master-slave Interconnection

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Data Sheet 6.2.3 SPI Transfer Formats
SCK Cycle # (for reference) SCK (CPOL=0) SCK (CPOL=1) MOSI (from Master) MISO (from Slave) SS# (to Slave)
MSB MSB
6 6
5 5
4 4
3 3
2 2
1 1
LSB LSB
1255 F20.0
FIGURE
6-5: SPI Transfer Format with CPHA = 0
SCK Cycle # (for reference) SCK (CPOL=0) SCK (CPOL=1) MOSI (from Master) MISO (from Slave) SS# (to Slave)
MSB MSB
6 6
5 5
4 4
3 3
2 2
1 1
LSB LSB
1255 F21.0
FIGURE
6-6: SPI Transfer Format with CPHA = 1
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Data Sheet
7.0 WATCHDOG TIMER

The device offers a programmable Watchdog Timer (WDT) for fail safe protection against software deadlock and automatic recovery. To protect the system against software deadlock, the user software must refresh the WDT within a user-defined time period. If the software fails to do this periodical refresh, an internal hardware reset will be initiated if enabled (WDRE= 1). The software can be designed such that the WDT times out if the program does not work properly. The WDT in the device uses the system clock (XTAL1) as its time base. So strictly speaking, it is a watchdog counter rather than a watchdog timer. The WDT register will increment every 344,064 crystal clocks. The upper 8-bits of the time base register (WDTD) are used as the reload register of the WDT. The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User software can clear WDTS by writing 1 to it. Figure 7-1 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control watchdog timer operation. During idle mode, WDT operation is temporarily suspended, and resumes upon an interrupt exit from idle. The time-out period of the WDT is calculated as follows: Period = (255 - WDTD) * 344064 * 1/fCLK (XTAL1) where WDTD is the value loaded into the WDTD register and fOSC is the oscillator frequency.
CLK (XTAL1)
Counter
344064 clks WDT Upper Byte
WDT Reset
Internal Reset
Ext. RST
WDTC
WDTD
1255 F22.0
FIGURE
7-1: Block Diagram of Programmable Watchdog Timer
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Data Sheet
8.0 PROGRAMMABLE COUNTER ARRAY

The Programmable Counter Array (PCA) present on the SST89E/V5xRD2/RD is a special 16-bit timer that has five 16-bit capture/compare modules. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. The 5th module can be programmed as a Watchdog Timer in addition to the other four modes. Each module has a pin associated with it in port 1. Module 0 is connected to P1.3 (CEX0), module 1 to P1[4] (CEX1), module 2 to P1[5] (CEX2), module 3 to P1[6] (CEX3), and module 4 to P1[7] (CEX4). PCA configuration is shown in Figure 8-1. PCA. External events associated with modules are shared with corresponding Port 1 pins. Modules not using the port pins can still be used for standard I/O. Each of the five modules can be programmed in any of the following modes: Rising and/or falling edge capture Software timer High speed output Watchdog Timer (Module 4 only) Pulse Width Modulator (PWM)
8.1 PCA Overview

PCA provides more timing capabilities with less CPU intervention than the standard timer/counter. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. Figure 8-1 shows a block diagram of the
8.2 PCA Timer/Counter

The PCA timer is a free-running 16-bit timer consisting of registers CH and CL (the high and low bytes of the count values). The PCA timer is common time base for all five modules and can be programmed to run at: 1/6 the oscillator frequency, 1/2 the oscillator frequency, Timer 0 overflow, or the input on the ECI pin (P1.2). The timer/counter source is determined from the CPS1 and CPS0 bits in the CMOD SFR as follows (see PCA Timer/Counter Mode Register (CMOD) on page 27):
TABLE
CPS1 0 0 1 1
8-1: PCA Timer/Counter Source

CPS0 0 1 0 1 12 Clock Mode fOSC /12 fOSC /4 Timer 0 overflow External clock at ECI pin (maximum rate = fOSC /8) 6 Clock Mode fOSC /6 fOSC /2 Timer 0 overflow External clock at ECI pin (maximum rate = fOSC /4)
T8-1.0 1255
16 Bits Each
Module 0 Module 1
16 Bits
P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4

1255 F23.0
PCA Timer/Counter
Module 2 Module 3 Module 4
FIGURE
8-1: PCA Timer/Counter and Compare/Capture Modules

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Data Sheet The table below summarizes various clock inputs at two common frequencies. TABLE 8-2: PCA Timer/Counter Inputs
Clock Increments PCA Timer/Counter Mode Mode 0: fOSC/12 Mode 1: Mode 2: Timer 0 8-bit mode 16-bit mode 8-bit auto-reload Mode 3: External Input MAX Overflows1 256 sec 65 msec 1 to 255 sec 0.66 sec 192 sec 49 sec 0.75 to 191 sec 0.50 sec
T8-2.0 1255
12 MHz 1 sec 330 nsec
16 MHz 0.75 sec 250 nsec
Timer 0 programmed in:
1. In Mode 2, the overflow interrupt for Timer 0 does not need to be enabled.
The four possible CMOD timer modes with and without the overflow interrupt enabled are shown below. This list assumes that PCA will be left running during idle mode. TABLE 8-3: CMOD Values
CMOD Value PCA Count Pulse Selected Internal clock, fOSC/12 Internal clock, fOSC/4 Timer 0 overflow External clock at P1.2 Without Interrupt Enabled 00H 02H 04H 06H With Interrupt Enabled 01H 03H 05H 07H
T8-3.0 1255
The CCON register is associated with all PCA timer functions. It contains run control bits and flags for the PCA timer (CF) and all modules. To run the PCA the CR bit (CCON.6) must be set by software. Clearing the bit, will turn off PCA. When the PCA counter overflows, the CF (CCON.7) will be set, and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. Each module has its own timer interrupt or capture interrupt flag (CCF0 for module 0, CCF4 for module 4, etc.). They are set when either a match or capture occurs. These flags can only be cleared by software. (See PCA Timer/Counter Control Register (CCON) on page 26.)
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Data Sheet
8.3 Compare/Capture Modules

Each PCA module has an associated SFR with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. Refer to PCA Compare/Capture Module Mode Register (CCAPMn) on page 28 for details. The registers each contain 7 bits which are used to control the mode each module will operate in. The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on module) will enable the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set, causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the modules capture/compare register. When there is a match between the PCA counter and the modules capture/compare register, the MATn (CCAPMn.3) and the CCFn bit in the CCON register to be set. TABLE
Symbol
Bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine whether the capture input will be active on a positive edge or negative edge. The CAPN bit enables the negative edge that a capture input will be active on, and the CAPP bit enables the positive edge. When both bits are set, both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set, enables the comparator function. Table 8-5 shows the CCAPMn settings for the various PCA functions. There are two additional register associated with each of the PCA modules: CCAPnH and CCAPnL. They are registers that hold the 16-bit count value when a capture occurs or a compare occurs. When a module is used in PWM mode, these registers are used to control the duty cycle of the output. See Figure 8-1.
8-4: PCA High and Low Register Compare/Capture Modules

Description Direct Address MSB FAH EAH FBH EBH FCH ECH FDH EDH FEH EEH Bit Address, Symbol, or Alternative Port Function LSB CCAP0H[7:0] CCAP0L[7:0] CCAP1H[7:0] CCAP1L[7:0] CCAP2H[7:0] CCAP2L[7:0] CCAP3H[7:0] CCAP3L[7:0] CCAP4H[7:0] CCAP4L[7:0] RESET Value 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H
T8-4.0 1255
CCAP0H PCA Module 0 CCAP0L Compare/Capture Registers CCAP1H PCA Module 1 CCAP1L Compare/Capture Registers CCAP2H PCA Module 2 CCAP2L Compare/Capture Registers CCAP3H PCA Module 3 CCAP3L Compare/Capture Registers CCAP4H PCA Module 4 CCAP4L Compare/Capture Registers
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Data Sheet TABLE 8-5: PCA Module Modes
TOGy2 0 0 0 0 0 1 0 0 or 13 PWMy2 ECCFy2 Module Code 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 No Operation 16-bit capture on positive-edge trigger at CEX[4:0] 16-bit capture on negative-edge trigger at CEX[4:0] 16-bit capture on positive/negative-edge trigger at CEX[4:0] Compare: software timer Compare: high-speed output Compare: 8-bit PWM Compare: PCA WDT (CCAPM4 only)4
T8-5.0 1255
Without Interrupt enabled -1 ECOMy2 CAPPy2 CAPNy2 MATy2 1. 2. 3. 4.
0 0 0 0 1 1 1 1
0 1 0 1 0 0 0 0
0 0 1 1 0 0 0 0
0 0 0 0 1 1 0 1
User should not write 1s to reserved bits. The value read from a reserved bit is indeterminate. y = 0, 1, 2, 3, 4 A 0 disables toggle function. A 1 enables toggle function on CEX[4:0] pin. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal.
TABLE
8-6: PCA Module Modes

TOGy2 0 0 0 0 1 0 0 or 14 PWMy2 ECCFy2 Module Code 0 0 0 0 0 1 0 1 1 1 1 1 X3 X5 16-bit capture on positive-edge trigger at CEX[4:0] 16-bit capture on negative-edge trigger at CEX[4:0] 16-bit capture on positive/negative-edge trigger at CEX[4:0] Compare: software timer Compare: high-speed output Compare: 8-bit PWM Compare: PCA WDT (CCAPM4 only)6
T8-6.0 1255
With Interrupt enabled -1 ECOMy2 CAPPy2 CAPNy2 MATy2 1. 2. 3. 4. 5. 6.
0 0 0 1 1 1 1
1 0 1 0 0 0 0
0 1 1 0 0 0 0
0 0 0 1 1 0 1
User should not write 1s to reserved bits. The value read from a reserved bit is indeterminate. y = 0, 1, 2, 3, 4 No PCA interrupt is needed to generate the PWM. A 0 disables toggle function. A 1 enables toggle function on CEX[4:0] pin. Enabling an interrupt for the Watchdog Timer would defeat the purpose of the Watchdog Timer. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal.
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Data Sheet 8.3.1 Capture Mode Capture mode is used to capture the PCA timer/counter value into a modules capture registers (CCAPnH and CCAPnL). The capture will occur on a positive edge, negative edge, or both on the corresponding modules pin. To use one of the PCA modules in the capture mode, either one or both the CCAPM bits CAPN and CAPP for that module must be set. When a valid transition occurs on the CEX pin corresponding to the module used, the PCA hardware loads the 16-bit value of the PCA counter register (CH and CL) into the modules capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set, then an interrupt will be generated. In the interrupt service routine, the 16-bit capture value must be saved in RAM before the next event capture occurs. If a subsequent capture occurred, the original capture values would be lost. After flag event flag has been set by hardware, the user must clear the flag in software. (See Figure 8-2)
CCON
CF
CR
CCF4
CCF3
CCF2
CCF1
CCF0
PCA Interrupt PCA Timer/Counter CH CL
CEXn
Capture
CCAPnH
CCAPnL
CCAPMn
n=0 to 4
ECOMn CAPPn CAPNn MATn 0 0
TOGn 0
PWMn ECCFn 0
1255 F24.0
FIGURE
8-2: PCA Capture Mode
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Data Sheet 8.3.2 16-Bit Software Timer Mode The 16-bit software timer mode is used to trigger interrupt routines, which must occur at periodic intervals. It is setup by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the modules capture registers (CCAPnL and CCAPnH) and when a match occurs, an interrupt will occur, if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set. If necessary, a new 16-bit compare value can be loaded into CCAPnH and CCAPnL during the interrupt routine. The user should be aware that the hardware temporarily disables the comparator function while these registers are being updated so that an invalid match will not occur. Thus, it is recommended that the user write to the low byte first (CCAPnL) to disable the comparator, then write to the high byte (CCAPnH) to re-enable it. If any updates to the registers are done, the user may want to hold off any interrupts from occurring by clearing the EA bit. (See Figure 8-3)
CF Write to CCAPnL Write to CCAPnH 1 0 Enable Reset CCAPnH
CR
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
PCA Interrupt
CCAPnL
16-bit Comparator
Match
CH
CL
PCA Timer/Counter
ECOMn CAPPn CAPNn 0 0
MATn
TOGn 0
PWMn ECCFn 0
1255 F25.0
CCAPMn
n=0 to 4
FIGURE
8-3: PCA Compare Mode (Software Timer)
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Data Sheet 8.3.3 High Speed Output Mode The high speed output mode is used to toggle a port pin when a match occurs between the PCA timer and the preloaded value in the compare registers. In this mode, the CEX output pin (on port 1) associated with the PCA module will toggle every time there is a match between the PCA counter (CH and CL) and the capture registers (CCAPnH and CCAPnL). To activate this mode, the user must set TOG, MAT, and ECOM bits in the modules CCAPMn SFR. High speed output mode is much more accurate than toggling pins since the toggle occurs before branching to an interrupt. In this case, interrupt latency will not affect the accuracy of the output. When using high speed output, using an interrupt is optional. Only if the user wishes to change the time for the next toggle is it necessary to update the compare registers. Otherwise, the next toggle will occur when the PCA timer rolls over and matches the last compare value. (See Figure 8-4)
CF Write to CCAPnL Write to CCAPnH 1 0 Enable Reset CCAPnH
CR
CCF4
CCF3
CCF2
CCF1
CCF0
CCON
PCA Interrupt
CCAPnL
16-bit Comparator
Match
Toggle CH CL CEXn
PCA Timer/Counter
MATn
TOGn
PWMn ECCFn 0
CCAPMn
n=0 to 4
1255 F26.0
FIGURE
8-4: PCA High Speed Output Mode
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Data Sheet 8.3.4 Pulse Width Modulator The Pulse Width Modulator (PWM) mode is used to generate 8-bit PWMs by comparing the low byte of the PCA timer (CL) with the low byte of the compare register (CCAPnL). When CL < CCAPnL the output is low. When CL CCAPnL the output is high. To activate this mode, the user must set the PWM and ECOM bits in the modules CCAPMn SFR. (See Figure 8-5 and Table 8-7) In PWM mode, the frequency of the output depends on the source for the PCA timer. Since there is only one set of CH and CL registers, all modules share the PCA timer and frequency. Duty cycle of the output is controlled by the value loaded into the high byte (CCAPnH). Since writes to the CCAPnH register are asynchronous, a new value written to the high byte will not be shifted into CCAPnL for comparison until the next period of the output (when CL rolls over from 255 to 00). To calculate values for CCAPnH for any duty cycle, use the following equation: CCAPnH = 256(1 - Duty Cycle) where CCAPnH is an 8-bit integer and Duty Cycle is a fraction.
CCAPnH
CCAPnL
0 Enable CL < CCAPnL 8-bit Comparator CL >= CCAPnL 1 CEXn
Overflow
CL PCA Timer/Counter
MATn 0
TOGn 0
PWMn ECCFn 0
CCAPMn
n=0 to 4
1255 F27.0
FIGURE TABLE
8-5: PCA Pulse Width Modulator Mode
8-7: Pulse Width Modulator Frequencies

PWM Frequency 12 MHz 3.9 KHz 11.8 KHz 15.5 Hz 0.06 Hz 3.9 KHz to 15.3 Hz 5.9 KHz 16 MHz 5.2 KHz 15.6 KHz 20.3 Hz 0.08 Hz 5.2 KHz to 20.3 Hz 7.8 KHz
T8-7.0 1255
PCA Timer Mode 1/12 Oscillator Frequency 1/4 Oscillator Frequency Timer 0 Overflow: 8-bit 16-bit 8-bit Auto-Reload External Input (Max)
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Data Sheet 8.3.5 Watchdog Timer The Watchdog Timer mode is used to improve reliability in the system without increasing chip count (See Figure 8-6). Watchdog Timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. It can also be used to prevent a software deadlock. If during the execution of the users code, there is a deadlock, the Watchdog Timer will time out and an internal reset will occur. Only module 4 can be programmed as a Watchdog Timer (but still can be programmed to other modes if the Watchdog Timer is not used). To use the Watchdog Timer, the user pre-loads a 16-bit value in the compare register. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. In order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the PCA timer, 2. periodically change the PCA timer value so it will never match the compare values, or 3. disable the watchdog timer by clearing the WDTE bit before a match occurs and then re-enable it. The first two options are more reliable because the Watchdog Timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most application the first solution is the best option. Use the code below to initialize the Watchdog Timer. Module 4 can be configured in either compare mode, and the WDTE bit in CMOD must also be set. The users software then must periodically change (CCAP4H, CCAP4L) to keep a match from occurring with the PCA timer (CH, CL). This code is given in the Watchdog routine below.
;============================================== Init_Watchdog: MOVCCAPM4, #4CH; Module 4 in compare mode MOVCCAP4L, #0FFH; Write to low byte first MOVCCAP4H, #0FFH; Before PCA timer counts up ; to FFFF Hex, these compare ; values must be changed. ORLCMOD, #40H; Set the WDTE bit to enable the ; watchdog timer without ; changing the other bits in ; CMOD ;============================================== ;Main program goes here, but call WATCHDOG periodically. ;============================================== WATCHDOG: CLR EA; Hold off interrupts MOVCCAP4L, #00; Next compare value is within MOVCCAP4H, CH; 65,535 counts of the ; current PCA SETBEA; timer value RET ;==============================================
This routine should not be part of an interrupt service routine. If the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine from the main program of the PCA timer.
CPS1 CPS0 ECF
CIDL Write to CCAP4L Write to CCAP4H 1 0 Enable Reset CCAP4H
WDTE
CMOD
CCAP4L
Module 4
16-bit Comparator
Match
Reset
CH
CL
PCA Timer/Counter
MATn 1
TOGn X
PWMn ECCFn 0 X
CCAPM4
1255 F28.0
FIGURE
8-6: PCA Watchdog Timer (Module 4 only)

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Data Sheet
9.0 SECURITY LOCK

The security lock protects against software piracy and prevents the contents of the flash from being read by unauthorized parties. It also protects against code corruption resulting from accidental erasing and programming to the internal flash memory. There are two different types of security locks in the device security lock system: hard lock and SoftLock. issued through the command mailbox register, SFCM, executed from a Locked (hard locked or soft locked) block, can be operated on a soft locked block: Block-Erase, SectorErase, Byte-Program and Byte-Verify. In external host mode, SoftLock behaves the same as a hard lock.
9.1 Hard Lock

When hard lock is activated, MOVC or IAP instructions executed from an unlocked or soft locked program address space, are disabled from reading code bytes in hard locked memory blocks (See Table 9-2). Hard lock can either lock both flash memory blocks or just lock the 8 KByte flash memory block (Block 1). All external host and IAP commands except for Chip-Erase are ignored for memory blocks that are hard locked.
9.3 Security Lock Status

The three bits that indicate the device security lock status are located in SFST[7:5]. As shown in Figure 91 and Table 9-1, the three security lock bits control the lock status of the primary and secondary blocks of memory. There are four distinct levels of security lock status. In the first level, none of the security lock bits are programmed and both blocks are unlocked. In the second level, although both blocks are now locked and cannot be programmed, they are available for read operation via Byte-Verify. In the third level, three different options are available: Block 1 hard lock / Block 0 SoftLock, SoftLock on both blocks, and hard lock on both blocks. Locking both blocks is the same as Level 2, Block 1 except read operation isnt available. The fourth level of security is the most secure level. It doesnt allow read/program of internal memory or boot from external memory. For details on how to program the security lock bits refer to the external host mode and in-application programming sections.
9.2 SoftLock
SoftLock allows flash contents to be altered under a secure environment. This lock option allows the user to update program code in the soft locked memory block through inapplication programming mode under a predetermined secure environment. For example, if Block 1 (8K) memory block is locked (hard locked or soft locked), and Block 0 memory block is soft locked, code residing in Block 1 can program Block 0. The following IAP mode commands
UUU/NN
Level 1 Level 2
PUU/SS
UPU/SS
UUP/LS
Level 3
UPP/LL PPU/LS PUP/LL UPP/LL
PPP/LL
Level 4
1255 F29.0
FIGURE
Note:
9-1: Security Lock Levels
P = Programmed (Bit logic state = 0), U = Unprogrammed (Bit logic state = 1), N = Not Locked, L = Hard locked, S = Soft locked
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Data Sheet TABLE
Level 1 2
9-1: Security Lock Options

Security Lock Bits1,2 SFST[7:5] 000 100 SB1 U P SB21 U U SB31 U U Security Status of: Block 1 Unlock SoftLock Block 0 Unlock SoftLock Security Type No Security Features are Enabled. MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA# is sampled and latched on Reset, and further programming of the flash is disabled. Level 2 plus Verify disabled, both blocks locked. Level 2 plus Verify disabled. Code in Block 1 may program Block 0 and vice versa. Level 2 plus Verify disabled. Code in Block 1 may program Block 0. Same as Level 3 hard lock/hard lock, but MCU will start code execution from the internal memory regardless of EA#.
T9-1.0 1255
011 101 010
U P U
P U P
P P U
Hard Lock SoftLock
Hard Lock SoftLock
110 001 4 111
P U P
P U P
U P P
Hard Lock Hard Lock
SoftLock Hard Lock
1. P = Programmed (Bit logic state = 0), U = Unprogrammed (Bit logic state = 1). 2. SFST[7:5] = Security Lock Status Bits (SB1_i, SB2_i, SB3_i)
9.4 Read Operation Under Lock Condition

The status of security bits SB1, SB2, and SB3 can be read when the read command is disabled by security lock. There are three ways to read the status. 1. External host mode: Read-back = 00H (locked) 2. IAP command: Read-back = previous SFDT data 3. MOVC: Read-back = FFH (blank)
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Data Sheet TABLE
Level
9-2: Security Lock Access Table

SFST[7:5] 111b (hard lock on both blocks) External Block 0/1 011b/101b (hard lock on both blocks) External Source Address1 Block 0/1 Target Address2 Block 0/1 External Block 0/1 External Block 0/1 External Block 0/1 External Block 0 Block 0 001b/110b (Block 0 = SoftLock, Block 1 = hard lock) Block 1 External Block 0 Block 1 Block 1 External External Block 0/1 External Block 0 Block 0 010b (SoftLock on both blocks) Block 1 External Block 0 Block 1 Block 1 External External Block 0/1 External Block 0 Block 0 100b (SoftLock on both blocks) Block 1 External Block 0 Block 1 Block 1 External External Block 0/1 External Block 0 Block 0 000b (unlock) Block 1 External Block 0 Block 1 Block 1 External External Block 0/1 External Byte-Verify Allowed External N N/A N N/A N N/A N N/A N N N/A N N N/A N N/A N N N/A N N N/A N N/A Y Y N/A Y Y N/A Y N/A Y Y N/A Y Y N/A Y N/A Host3 IAP N N/A N N/A N N/A N N/A N N N/A Y N N/A N N/A N Y N/A Y N N/A N N/A N Y N/A Y N N/A N N/A N Y N/A Y N N/A Y N/A MOVC Allowed 5xRDx Y Y N Y Y Y N Y Y N Y Y Y Y N Y Y Y Y Y Y Y N Y Y Y Y Y Y Y N Y Y Y Y Y Y Y Y Y
T9-2.0 1255
1. Location of MOVC or IAP instruction 2. Target address is the location of the byte being read 3. External host Byte-Verify access does not depend on a source address.
57

Data Sheet
10.0 RESET
A system reset initializes the MCU and begins program execution at program memory location 0000H. The reset input for the device is the RST pin. In order to reset the device, a logic level high must be applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable. ALE, PSEN# are weakly pulled high during reset. During reset, ALE and PSEN# output a high level in order to perform a proper reset. This level must not be affected by external element. A system reset will not affect the 1 KByte of on-chip RAM while the device is running, however, the contents of the on-chip RAM during power up are indeterminate. Following reset, all Special Function Registers (SFR) return to their reset values outlined in Tables 3-5 to 3-9.
VDD
+
10F
RST 8.2K C2 XTAL2
VDD
SST89E/V5xRDx
XTAL1
C1
1255 F30.1
FIGURE
10-1: Power-on Reset Circuit
10.1 Power-on Reset

At initial power up, the port pins will be in a random state until the oscillator has started and the internal reset algorithm has weakly pulled all pins high. Powering up the device without a valid reset could cause the MCU to start executing instructions from an indeterminate location. Such undefined states may inadvertently corrupt the code in the flash. When power is applied to the device, the RST pin must be held high long enough for the oscillator to start up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. An example of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 F capacitor and to VSS through an 8.2K resistor as shown in Figure 10-1. Note that if an RC circuit is being used, provisions should be made to ensure the VDD rise time does not exceed 1 millisecond and the oscillator startup time does not exceed 10 milliseconds. For a low frequency oscillator with slow start-up time the reset signal must be extended in order to account for the slow start-up time. This method maintains the necessary relationship between VDD and RST to avoid programming at an indeterminate location, which may cause corruption in the code of the flash. The power-on detection is designed to work as power up initially, before the voltage reaches the brown-out detection level. The POF flag in the PCON register is set to indicate an initial power up condition. The POF flag will remain active until cleared by software. Please see Section 3.6, Power Control Register (PCON) on page 30 for detailed information. For more information on system level design techniques, please review the FlashFlex51 MCU: Oscillator Circuit Design Considerations application note.
10.2 Software Reset

The software reset is executed by changing SFCF[1] (SWR) from 0 to 1. A software reset will reset the program counter to address 0000H. All SFR registers will be set to their reset values, except SFCF[1] (SWR), WDTC[2] (WDTS), and RAM data will not be altered.
10.3 Brown-out Detection Reset

The device includes a brown-out detection circuit to protect the system from severed supplied voltage VDD fluctuations. SST89E5xRD2/RD internal brown-out detection threshold is 3.85V, SST89V5xRD2/RD brown-out detection threshold is 2.35V. For brown-out voltage parameters, please refer to Tables 14-6 and 14-7. When VDD drops below this voltage threshold, the brownout detector triggers the circuit to generate a brown-out interrupt but the CPU still runs until the supplied voltage returns to the brown-out detection voltage VBOD. The default operation for a brown-out detection is to cause a processor reset. VDD must stay below VBOD at least four oscillator clock periods before the brown-out detection circuit will respond. Brown-out interrupt can be enabled by setting the EBO bit in IEA register (address E8H, bit 3). If EBO bit is set and a brown-out condition occurs, a brown-out interrupt will be generated to execute the program at location 004BH. It is required that the EBO bit be cleared by software after the brown-out interrupt is serviced. Clearing EBO bit when the brown-out condition is active will properly reset the device. If brown-out interrupt is not enabled, a brown-out condition will reset the program to resume execution at location 0000H.
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Data Sheet
11.0 INTERRUPTS 11.1 Interrupt Priority and Polling Sequence

The device supports eight interrupt sources under a four level priority scheme. Table 11-1 summarizes the polling sequence of the supported interrupts. Note that the SPI serial interface and the UART share the same interrupt vector. (See Figure 11-1) TABLE 11-1: Interrupt Polling Sequence
Description Ext. Int0 Brown-out T0 Ext. Int1 T1 PCA Ext. Int. 2 Ext. Int. 3 UART/SPI T2 Interrupt Flag IE0 TF0 IE1 TF1 CF/CCFn IE2 IE3 TI/RI/SPIF TF2, EXF2 Vector Address 0003H 004BH 000BH 0013H 001BH 0033H 003BH 0043H 0023H 002BH Interrupt Enable EX0 EBO ET0 EX1 ET1 EC EX2 EX3 ES ET2 Interrupt Priority PX0/H PBO/H PT0/H PX1/H PT1/H PPCH PX2/H PX3/H PS/H PT2/H Service Priority 1(highest) 2 3 4 5 6 7 8 9 10 Wake-Up Power-down yes no no yes no no no no no no
T11-1.0 1255
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Data Sheet
IE & IEA REGISTERS 0 INT0# 1 IT0 IE0
IP/IPH/IPA/IPAH REGISTERS
HIGHEST PRIORITY INTERRUPT
BOF
INTERRUPT POLLING SEQUENCE
TF0
0 INT1# 1 IT1 IE1
TF1
ECF
CF
CCFn
ECCFn
0 INT2# 1 IT2 IE2
0 INT3# 1 IT3 IE3
RI TI SPIF SPIE
TF2 EXF2
INDIVIDUAL ENABLES
GLOBAL DISABLE
LOWEST PRIORITY INTERRUPT

1255 F31.0
FIGURE
11-1: Interrupt Structure

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Data Sheet
12.0 POWER-SAVING MODES

The device provides two power saving modes of operation for applications where power consumption is critical. The two modes are idle and power-down, see Table 12-1.
12.2 Power-down Mode

The power-down mode is entered by setting the PD bit in the PCON register. In the power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. SRAM contents are retained during powerdown, the minimum VDD level is 2.0V. The device exits power-down mode through either an enabled external level sensitive interrupt or a hardware reset. The start of the interrupt clears the PD bit and exits power-down. Holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. Upon interrupt signal being restored to logic VIH, the first instruction of the interrupt service routine will execute. A hardware reset starts the device similar to power-on reset. To exit properly out of power-down, the reset or external interrupt should not be executed before the VDD line is restored to its normal operating voltage. Be sure to hold VDD voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms).
12.1 Idle Mode

Idle mode is entered setting the IDL bit in the PCON register. In idle mode, the program counter (PC) is stopped. The system clock continues to run and all interrupts and peripherals remain active. The on-chip RAM and the special function registers hold their data during this mode. The device exits idle mode through either a system interrupt or a hardware reset. Exiting idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits idle mode. After exit the Interrupt Service Routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the idle mode. A hardware reset starts the device similar to a power-on reset.
TABLE 12-1: Power Saving Modes

Mode Idle Mode Initiated by Software (Set IDL bit in PCON) MOV PCON, #01H; State of MCU CLK is running. Interrupts, serial port and timers/counters are active. Program Counter is stopped. ALE and PSEN# signals at a HIGH level during Idle. All registers remain unchanged. Exited by Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits idle mode, after the ISR RETI instruction, program resumes execution beginning at the instruction following the one that invoked idle mode. A user could consider placing two or three NOP instructions after the instruction that invokes idle mode to eliminate any problems. A hardware reset restarts the device similar to a power-on reset. Enabled external level sensitive interrupt or hardware reset. Start of interrupt clears PD bit and exits powerdown mode, after the ISR RETI instruction program resumes execution beginning at the instruction following the one that invoked power-down mode. A user could consider placing two or three NOP instructions after the instruction that invokes power-down mode to eliminate any problems. A hardware reset restarts the device similar to a power-on reset.
T12-1.0 1255
Power-down Mode
Software (Set PD bit in PCON) MOV PCON, #02H;
CLK is stopped. On-chip SRAM and SFR data is maintained. ALE and PSEN# signals at a LOW level during power -down. External Interrupts are only active for level sensitive interrupts, if enabled.
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Data Sheet
13.0 SYSTEM CLOCK AND CLOCK OPTIONS 13.1 Clock Input Options and Recommended Capacitor Values for Oscillator
Shown in Figure 13-1 are the input and output of an internal inverting amplifier (XTAL1, XTAL2), which can be configured for use as an on-chip oscillator. When driving the device from an external clock source, XTAL2 should be left disconnected and XTAL1 should be driven. At start-up, the external oscillator may encounter a higher capacitive load at XTAL1 due to interaction between the amplifier and its feedback capacitance. However, the capacitance will not exceed 15 pF once the external signal meets the VIL and VIH specifications. Crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one application to another. C1 and C2 should be adjusted appropriately for each design. Table 13-1, shows the typical values for C1 and C2 vs. crystal type for various frequencies TABLE 13-1:Recommended Values for C1 and C2 by Crystal Type
Crystal Quartz Ceramic C1 = C2 20-30pF 40-50pF
T13-1.0 1255
More specific information about on-chip oscillator design can be found in the FlashFlex51 Oscillator Circuit Design Considerations application note.
13.2 Clock Doubling Option

By default, the device runs at 12 clocks per machine cycle (x1 mode). The device has a clock doubling option to speed up to 6 clocks per machine cycle. Please refer to Table 13-2 for detail. Clock double mode can be enabled either via the external host mode or the IAP mode. Please refer to Table 4-2 for the IAP mode enabling commands (When set, the EDC# bit in SFST register will indicate 6 clock mode.). The clock double mode is only for doubling the internal system clock and the internal flash memory, i.e. EA#=1. To access the external memory and the peripheral devices, careful consideration must be taken. Also note that the crystal output (XTAL2) will not be doubled.
XTAL2 C2 C1 XTAL1 VSS External Oscillator Signal NC XTAL2
XTAL1
VSS
Using the On-Chip Oscillator FIGURE 13-1: Oscillator Characteristics

TABLE 13-2: Clock Doubling Features
Device Standard Mode (x1)
Clocks per Machine Cycle Max. External Clock Frequency (MHz)
External Clock Drive
1255 F32.0
Clock Double Mode (x2)

Clocks per Machine Cycle Max. External Clock Frequency (MHz)
SST89E5xRD2/RD SST89V5xRD2/RD
12 12
40 33
6 6
20 16
T13-2.0 1255
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Data Sheet
14.0 ELECTRICAL SPECIFICATION

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under Absolute Maximum Stress Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Voltage on EA# Pin to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20ns) on Any Other Pin to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD+1.0V Maximum IOL per I/O Pins P1.5, P1.6, P1.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum IOL per I/O for All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W Through Hole Lead Soldering Temperature (10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time. (Based on package heat transfer limitations, not device power consumption. Note: This specification contains preliminary information on new products in production. Specifications are subject to change without notice.
TABLE 14-1: Operating Range

Symbol TA Description Ambient Temperature Under Bias Standard Industrial VDD Supply Voltage SST89E5xRD2/RD SST89V5xRD2/RD fOSC Oscillator Frequency SST89E5xRD2/RD SST89V5xRD2/RD Oscillator Frequency for IAP SST89E5xRD2/RD SST89V5xRD2/RD .25 .25 40 33 MHz MHz
T14-1.0 1255
Min. 0 -40 4.5 2.7 0 0
Max +70 +85 5.5 3.6 40 33
Unit
C C
V V MHz MHz
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Data Sheet TABLE 14-2: Reliability Characteristics
Symbol NEND1 TDR
1
Parameter Endurance Data Retention Latch Up
Minimum Specification 10,000 100 100 + IDD
Units Cycles Years mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T14-2.0 1255
ILTH1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 14-3: AC Conditions of Test

Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF See Figures 14-8 and 14-10
T14-3.0 1255
TABLE 14-4: Recommended System Power-up Timings

Symbol TPU-READ
1
Parameter Power-up to Read Operation Power-up to Write Operation
Minimum 100 100
Units s s
T14-4.0 1255
TPU-WRITE1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter
TABLE 14-5: Pin Impedance (VDD=3.3V, TA=25 C, f=1 Mhz, other pins open)
Parameter CI/O
1
Description I/O Pin Capacitance Input Capacitance Pin Inductance
Test Condition VI/O = 0V VIN = 0V
Maximum 15 pF 12 pF 20 nH
T14-5.0 1255
CIN1 LPIN2
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. Refer to PCI spec.
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Data Sheet
14.1 DC Electrical Characteristics

TABLE 14-6: DC Electrical Characteristics for SST89E5xRD2/RD TA = -40C to +85C; VDD = 4.5-5.5V; VSS = 0V
Symbol VIL VIH VIH1 VOL VOL Parameter Input Low Voltage Input High Voltage Input High Voltage (XTAL1, RST) Output Low Voltage (Ports 1.5, 1.6, 1.7) Output Low Voltage (Ports 1, 2, 3)1 Test Conditions 4.5 < VDD < 5.5 4.5 < VDD < 5.5 4.5 < VDD < 5.5 VDD = 4.5V IOL = 16mA VDD = 4.5V IOL = 100A2 IOL = 1.6mA2 IOL = 3.5mA2 VOL1 Output Low Voltage (Port 0, ALE, PSEN#)1,3 VDD = 4.5V IOL = 200A2 IOL = 3.2mA2 VOH Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4 VDD = 4.5V IOH = -10A IOH = -30A IOH = -60A VOH1 Output High Voltage (Port 0 in External Bus Mode)4 VDD = 4.5V IOH = -200A IOH = -3.2mA VBOD IIL ITL ILI RRST CIO IDD Brown-out Detection Voltage Logical 0 Input Current (Ports 1, 2, 3) Logical 1-to-0 Transition Current (Ports 1, 2, 3)5 Input Leakage Current (Port 0) RST Pull-down Resistor Pin Capacitance6 Power Supply Current IAP Mode @ 40 MHz Active Mode @ 40 MHz Idle Mode @ 40 MHz Power-down Mode TA = 0C to +70C TA = -40C to +85C
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA Maximum IOL per port pin: Maximum IOL per 8-bit port:26mA Maximum IOL total for all outputs:71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
Min -0.5 0.2VDD + 0.9 0.7VDD
Max 0.2VDD - 0.1 VDD + 0.5 VDD + 0.5 1.0 0.3 0.45 1.0 0.3 0.45
Units V V V V V V V V V V V V V V
VDD - 0.3 VDD - 0.7 VDD - 1.5 VDD - 0.3 VDD - 0.7 3.85 4.15 -75 -650 10 40 225 15
V A A A K pF
VIN = 0.4V VIN = 2V 0.45 < VIN < VDD-0.3 @ 1 MHz, 25C
88 50 42 80 90
mA mA mA A A
T14-6.2 1255
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Data Sheet
2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 3. Load capacitance for Port 0, ALE and PSEN#= 100pF, load capacitance for all other outputs = 80pF. 4. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when the address bits are stabilizing. 5. Pins of Ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 6. Pin capacitance is characterized but not tested. EA# is 25pF (max).
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Data Sheet TABLE 14-7: DC Electrical Characteristics for SST89V5xRD2/RD TA = -40C to +85C; VDD = 2.7-3.6V; VSS = 0V
Symbol VIL VIH VIH1 VOL VOL Parameter Input Low Voltage Input High Voltage Input High Voltage (XTAL1, RST) Output Low Voltage (Ports 1.5, 1.6, 1.7) Output Low Voltage (Ports 1, 2, 3)1 Test Conditions 2.7 < VDD < 3.6 2.7 < VDD < 3.6 2.7 < VDD < 3.6 VDD = 2.7V IOL = 16mA VDD = 2.7V IOL = 100A2 IOL = VOL1 Output Low Voltage (Port 0, ALE, PSEN#)1,3 1.6mA2 IOL = 3.5mA2 VDD = 2.7V IOL = 200A2 IOL = VOH Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)4 3.2mA2 VDD - 0.3 VDD - 0.7 VDD - 1.5 VDD - 0.3 VDD - 0.7 2.35 VIN = 0.4V VIN = 2V 0.45 < VIN < VDD-0.3 @ 1 MHz, 25C 2.55 -75 -650 10 225 15 VDD = 2.7V IOH = -10A IOH = -30A IOH = -60A VOH1 Output High Voltage (Port 0 in External Bus Mode)4 VDD = 2.7V IOH = -200A IOH = -3.2mA VBOD IIL ITL ILI RRST CIO IDD Brown-out Detection Voltage Logical 0 Input Current (Ports 1, 2, 3) Logical 1-to-0 Transition Current (Ports 1, 2, 3)5 Input Leakage Current (Port 0) RST Pull-down Resistor Pin Capacitance6 Power Supply Current IAP Mode @ 33 MHz Active Mode @ 33 MHz Idle Mode @ 33 MHz Power-down Mode TA = 0C to +70C TA = -40C to +85C 21 45 55 mA A A
T14-7.1 1255
Min -0.5 0.2VDD + 0.9 0.7VDD
Max 0.7 VDD + 0.5 VDD + 0.5 1.0 0.3 0.45 1.0 0.3 0.45
Units V V V V V V V V V V V V V V V A A A K pF
47 30
mA mA
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA Maximum IOL per 8-bit port: 26mA Maximum IOL total for all outputs: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 3. Load capacitance for Port 0, ALE and PSEN#= 100pF, load capacitance for all other outputs = 80pF.
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Data Sheet
4. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN# to momentarily fall below the VDD - 0.7 specification when the address bits are stabilizing. 5. Pins of Ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 6. Pin capacitance is characterized but not tested. EA# is 25pF (max).
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Data Sheet
30 25 20 IDD (mA) 15 10 5 0 5 Typical Active IDD Typical Idle IDD 10 15 20 25 Internal Clock Frequency (MHz) 30 35
1255 F33.0
Maximum Active IDD Maximum Idle IDD
FIGURE
14-1: IDD vs. Frequency for 3V SST89V5xRD2/RD
50 Maximum Active IDD 40 IDD (mA) 30 20 10 0 5 10 15 20 25 Internal Clock Frequency (MHz) Typical Active IDD Typical Idle IDD 30 35 40
1255 F34.0
Maximum Idle IDD
FIGURE
14-2: IDD vs. Frequency for 5V SST89E5xRD2/RD
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Data Sheet
14.2 AC Electrical Characteristics

AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF; Load Capacitance for All Other Outputs = 80pF) TABLE 14-8: AC Electrical Characteristics (1 of 2) TA = -40C to +85C, VDD = 2.7-3.6V@33MHz, 4.5-5.5V@40MHz, VSS = 0V
Oscillator 33 MHz (x1 Mode) 16 MHz (x2 Mode)1 Symbol Parameter Min 0 0 46 5 10 5 10 56 55 5 10 66 60 35 25 0 25 10 22 72 65 10 142 120 142 120 62 75 0 36 38 152 150 183 150 66 46 70 116 60 90 3TCLCL - 25 (3V) 3TCLCL - 15 (5V) 4TCLCL - 75 (3V) 4TCLCL - 30 (5V) 0 0 2TCLCL - 25 (3V) 2TCLCL - 12 (5V) 8TCLCL - 90 (3V) 8TCLCL - 50 (5V) 9TCLCL - 90 (3V) 9TCLCL - 75 (5V) 3TCLCL + 25 (3V) 3TCLCL + 15 (5V) 10 6TCLCL - 40 (3V) 6TCLCL - 30 (5V) 6TCLCL - 40 (3V) 6TCLCL - 30 (5V) 5TCLCL - 90 (3V) 5TCLCL - 50 (5V) 17 TCLCL - 8 5TCLCL - 80 (3V) 5TCLCL - 60 (5V) 10 TCLCL - 5 (3V) TCLCL - 15 (5V) TCLCL - 25 (3V) TCLCL - 15 (5V) 3TCLCL - 25 (3V) 3TCLCL - 15 (5V) 3TCLCL - 55 (3V) 3TCLCL - 50 (5V) Max 33 16 40 MHz (x1 Mode) 20 MHz (x2 Mode)1 Min 0 0 35 Max 40 20 Min 0 0 2TCLCL - 15 TCLCL - 25 (3V) TCLCL - 15 (5V) TCLCL - 25 (3V) TCLCL - 15 (5V) 4TCLCL - 65 (3V) 4TCLCL - 45 (5V) Variable Max 40 20 Units MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1/TCLCL 1/2TCLCL TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TPXAV TAVIV TPLAZ TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL
x1 Mode Oscillator Frequency x2 Mode Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instr In ALE Low to PSEN# Low PSEN# Pulse Width PSEN# Low to Valid Instr In Input Instr Hold After PSEN# Input Instr Float After PSEN# PSEN# to Address valid Address to Valid Instr In PSEN# Low to Address Float RD# Pulse Width Write Pulse Width (WE#) RD# Low to Valid Data In Data Hold After RD# Data Float After RD# ALE Low to Valid Data In Address to Valid Data In ALE Low to RD# or WR# Low Address to RD# or WR# Low
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Data Sheet TABLE 14-8: AC Electrical Characteristics (Continued) (2 of 2) TA = -40C to +85C, VDD = 2.7-3.6V@33MHz, 4.5-5.5V@40MHz, VSS = 0V
Oscillator 33 MHz (x1 Mode) 16 MHz (x2 Mode)1 Symbol Parameter Min 3 5 142 125 10 0 5 55 10 1. Calculated values are for x1 Mode only 40 5 0 TCLCL - 25 (3V) TCLCL - 15 (5V) Max 40 MHz (x1 Mode) 20 MHz (x2 Mode)1 Min Max Min TCLCL - 27 (3V) TCLCL - 20 (5V) 7TCLCL - 70 (3V) 7TCLCL - 50 (5V) TCLCL - 20 0 TCLCL + 25 (3V) TCLCL + 15 (5V) Variable Max Units ns ns ns ns ns ns ns ns
TWHQX TQVWH TQVWX TRLAZ TWHLH
Data Hold After WR# Data Valid to WR# High Data Valid to WR# High to Low Transition
RD# Low to Address Float RD# to WR# High to ALE High
T14-8.0 1255
Explanation of Symbols Each timing symbol has 5 characters. The first character is always a T (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: C: D: H: I: L: P: Address Clock Input data Logic level HIGH Instruction (program memory contents) Logic level LOW or ALE PSEN# Q: R: T: V: W: X: Z: Output data RD# signal Time Valid WR# signal No longer a valid logic level High Impedance (Float)
For example: TAVLL = Time from Address Valid to ALE Low TLLPL = Time from ALE Low to PSEN# Low
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Data Sheet
TLHLL
ALE
TAVLL TLLPL TPLAZ TLLAX TLLIV TPLIV TPXAV TPXIZ TPXIX INSTR IN A0 - A7 TPLPH
PSEN#
PORT 0
A0 - A7 TAVIV
PORT 2
A8 - A15
A8 - A15
1255 F35.0
FIGURE
14-3: External Program Memory Read Cycle
TLHLL
ALE
TWHLH
PSEN#
TLLDV TRLRH TLLWL
RD#
TAVLL
TLLAX TRLAZ TRLDV
TRHDZ TRHDX
PORT 0
A0-A7 FROM RI or DPL TAVWL TAVDV
DATA IN
A0-A7 FROM PCL
INSTR IN
PORT 2
P2[7:0] or A8-A15 FROM DPH
A8-A15 FROM PCH

1255 F36.0
FIGURE
14-4: External Data Memory Read Cycle
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Data Sheet
TLHLL
ALE
TWHLH
PSEN#
TLLWL TWLWH
WR#
TAVLL
TLLAX TQVWX TQVWH TWHQX
PORT 0
A0-A7 FROM RI or DPL TAVWL
DATA OUT
A0-A7 FROM PCL
INSTR IN
PORT 2
P2[7:0] or A8-A15 FROM DPH
A8-A15 FROM PCH

1255 F37.0
FIGURE
14-5: External Data Memory Write Cycle
TABLE 14-9: External Clock Drive

Oscillator 12MHz Symbol 1/TCLCL TCLCL TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Frequency High Time Low Time Rise Time Fall Time Min 83 Max 40MHz Min 25 8.75 8.75 20 20 10 10 Max Min 0 0.35TCLCL 0.35TCLCL Variable Max 40 0.65TCLCL 0.65TCLCL Units MHz ns ns ns ns ns
T14-9.0 1255
VDD - 0.5
0.7VDD 0.2 VDD - 0.1 TCLCX TCHCL TCLCL TCHCX TCLCH

1255 F38.0
0.45 V
FIGURE
14-6: External Clock Drive Waveform
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Data Sheet TABLE 14-10: Serial Port Timing
Oscillator 12MHz Symbol TXLXL TQVXH TXHQX TXHDX TXHDV Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid Min 1.0 700 50 0 0 700 0 117 Max 40MHz Min 0.3 117 Max Min 12TCLCL 10TCLCL - 133 2TCLCL - 117 2TCLCL - 50 0 10TCLCL - 133 Variable Max Units s ns ns ns ns ns
T14-10.0 1255
INSTRUCTION ALE
TXLXL CLOCK TQVXH

OUTPUT DATA WRITE TO SBUF INPUT DATA CLEAR RI
TXHQX
1
TXHDV VALID VALID
2
TXHDX VALID
7
SET TI
VALID
VALID
VALID
VALID
VALID
SET R I
1255 F39.0
FIGURE
14-7: Shift Register Mode Timing Waveforms
VIHT
VHT VLT
1255 F40.0
VLOAD +0.1V VLOAD VLOAD -0.1V Timing Reference Points
VOH -0.1V VOL +0.1V

1255 F41.0
VILT
AC Inputs during testing are driven at VIHT (VDD -0.5V) for Logic "1" and VILT (0.45V) for a Logic "0". Measurement reference points for inputs and outputs are at VHT (0.2VDD + 0.9) and VLT (0.2VDD - 0.1)
Note: VHT- VHIGH Test VLT- VLOW Test VIHT-VINPUT HIGH Test VILT- VINPUT LOW Test
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH = 20mA.
FIGURE
14-8: AC Testing Input/Output Test Waveform
FIGURE
14-9: Float Waveform
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Data Sheet
TO TESTER
TO DUT CL
1255 F42.0
FIGURE 14-10: A Test Load Example
VDD VDD VDD RST P0 EA# RST IDD VDD VDD P0 EA#
VDD IDD VDD
SST89x5xRDx CLOCK SIGNAL (NC) XTAL2 XTAL1 VSS

1255 F43.1
SST89x5xRDx (NC) XTAL2 XTAL1 VSS

1255 F44.1
All other pins disconnected
FIGURE 14-11: IDD Test Condition, Active Mode
FIGURE 14-13: IDD Test Condition, Power-down Mode TABLE 14-11: Flash Memory Programming/ Verification Parameters1
Parameter2
VDD
VDD VDD P0 RST EA# IDD
Max 150 100 30 50 80
Units ms ms ms s s
T14-11.0 1255
Chip-Erase Time Block-Erase Time Sector-Erase Time Byte-Program Time3 Re-map or Security bit Program Time
SST89x5xRDx CLOCK SIGNAL (NC) XTAL2 XTAL1 VSS

1255 F45.1
1. For IAP operations, the program execution overhead must be added to the above timing parameters. 2. Program and Erase times will scale inversely proportional to programming clock frequency. 3. Each byte must be erased before programming.
FIGURE 14-12: IDD Test Condition, Idle Mode
S71255-05-000
5/06
75

Data Sheet
15.0 PRODUCT ORDERING INFORMATION

Device SST89x5xRDx Speed XX Suffix1 X Suffix2 XX X Package Attribute E1 = non-Pb F2 = non-Pb, non-Sn Package Modifier I = 40 pins J = 44 pins Package Type P = PDIP N = PLCC Q = WQFN TQ = TQFP Operation Temperature C = Commercial = 0C to +70C I = Industrial = -40C to +85C Operating Frequency 33 = 0-33MHz 40 = 0-40MHz Feature Attribute 2 = Port 4 present Feature Set and Flash Memory Size 52RD = C52 feature set + 8(16) KByte 54RD = C52 feature set + 16(32) KByte 58RD = C52 feature set + 32(40) KByte
Note: Number in parenthesis includes an additional 8 KByte flash which can be enabled.
Voltage Range E = 4.5-5.5V V = 2.7-3.6V Product Series 89 = C51 Core
1. Environmental suffix E denotes non-Pb solder. SST non-Pb solder devices are RoHS Compliant. 2. Environmental suffix F denotes non-Pb/non-SN solder. SST non-Pb/non-Sn solder devices are RoHS Compliant.
S71255-05-000
5/06
76

Data Sheet
15.1 Valid Combinations

Valid combinations for SST89E52RD2
SST89E52RD2-40-C-NJ SST89E52RD2-40-C-NJE SST89E52RD2-40-I-NJ SST89E52RD2-40-I-NJE SST89E52RD2-40-C-TQJ SST89E52RD2-40-C-TQJE SST89E52RD2-40-I-TQJ SST89E52RD2-40-I-TQJE
Valid combinations for SST89V52RD2

SST89V52RD2-33-C-NJ SST89V52RD2-33-C-NJE SST89V52RD2-33-I-NJ SST89V52RD2-33-I-NJE SST89V52RD2-33-C-TQJ SST89V52RD2-33-C-TQJE SST89V52RD2-33-I-TQJ SST89V52RD2-33-I-TQJE




S71255-05-000
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77

Data Sheet Valid combinations for SST89E52RD
SST89E52RD-40-C-PI SST89E52RD-40-C-PIE SST89E52RD-40-I-PI SST89E52RD-40-I-PIE
Valid combinations for SST89V52RD

SST89V52RD-33-C-PI SST89V52RD-33-C-PIE SST89V52RD-33-I-PI SST89V52RD-33-I-PIE
Valid combinations for SST89E54RD


SST89V54RD-33-C-PI SST89V54RD-33-C-PIE SST89V54RD-33-I-PI SST89V54RD-33-I-PIE SST89V54RD-33-I-QIF SST89V54RD-33-C-QIF
Valid combinations for SST89E58RD


SST89V58RD-33-C-PI SST89V58RD-33-C-PIE SST89V58RD-33-I-PI SST89V58RD-33-I-PIE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
S71255-05-000
5/06
78

Data Sheet
16.0 PACKAGING DIAGRAMS

40
C L
1 Pin #1 Identifier
.065 .075 2.020 2.070 12 4 places
.600 .625 .530 .557
Base Plane Seating Plane

.015 Min.
.220 Max.
.063 .090
.045 .055
.015 .022
.100 BSC
.100 .200
.008 .012 .600 BSC
0 15
Note:
1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent. = JEDEC min is .115; SST min is less stringent 2. All linear dimensions are in inches (min/max). 40-pdip-PI-7 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
FIGURE
16-1: 40-pin Plastic Dual In-line Pins (PDIP) SST Package Code: PI
TOP VIEW
Optional Pin #1 Identifier .042 .048 .685 .695 .646 .656
1 44
SIDE VIEW
.147 .158 .025 R. .045
BOTTOM VIEW
.020 R. MAX. .042 x45 .056
.042 .048 .685 .695 .646 .656 .026 .032
.013 .021 .500 REF. .590 .630
.050 BSC. .020 Min. .026 .032

44-plcc-NJ-7
.050 BSC. .165 .180
.100 .112
Note:
1. Complies with JEDEC publication 95 MS-018 AC dimensions (except as noted), although some dimensions may be more stringent. = JEDEC min is .650; SST min is less stringent 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils.
FIGURE
16-2: 44-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NJ
S71255-05-000 5/06
79

Data Sheet
Pin #1 Identifier
44
34
33
.30 .45 10.00 0.10 12.00 0.25 .80 BSC
11
23
12
10.00 0.10 12.00 0.25 1.2 max.
22
.09 .20 .95 1.05 .05 .15 .45 .75 1.00 ref
44-tqfp-TQJ-7
0- 7
Note:
1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (0.05) mm. 4. Package body dimensions do not include mold flash. Maximum allowable mold flash is .25mm.
1mm
FIGURE
16-3: 44-lead Thin Quad Flat Pack (TQFP) SST Package Code: TQJ
TOP VIEW
SIDE VIEW
0.2
BOTTOM VIEW
See notes 2 and 3 Pin #1
Pin #1
0.5 BSC 6.00 0.10 0.075 4.1 4.1 0.30 0.18
6.00 0.10 0.80 0.70
0.05 Max
0.45 0.35
Note: 1. Complies with JEDEC JEP95 MO-220I, variant WJJD-5 except external paddle nominal dimensions. 1mm 2. From the bottom view, the pin #1 indicator may be either a 45-degree chamfer or a half-circle notch. 3. The external paddle is electrically connected to the die back-side and possibly to certain VSS leads. 40-wqfn-6x6-QI-1 This paddle should be soldered to the PC board; it is suggested to connect this paddle to the VSS of the unit. Connection of this paddle to any other voltage potential will result in shorts and/or electrical malfunction of the device. 4. Untoleranced dimensions are nominal target dimensions. 5. All linear dimensions are in millimeters (max/min).
FIGURE
16-4: 40-contact Very-very-thin Quad Flat No-lead (WQFN) SST Package Code: QI
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80

Data Sheet TABLE 16-1: Revision History
Number 00 01 Description Date Mar 2004 Sep 2004
Initial Release
Changed MPNs of SST89E/V5xRD2 PDIP devices to SST89E/V5xRD Removed SST89E/V516RD2 devices and associated MPNs Removed all industrial temperature PDIP devices and associated MPNs Clarified Surface Mount Temperatures in Absolute Maximum Stress Ratings on page 63 Changes in Tables 14-6 and 14-7: Removed the minimum VDD=2V for IDD Power-down (also Figure 14-13) Removed the 12 MHz values for IDD Corrected MPN breakdown definition for 2 to read Port 4 present Corrected the SPI control Register definition for CPHA on page 29 Added SST89E/V5xRD industrial temperature PDIP devices and associated MPNs Added RoHS compliance information on page 1 and in the Product Ordering Information on page 76 Corrected the solder temperature profile under Absolute Maximum Stress Ratings on page 63 Removed references to External Host Mode programming Made changes to add WQFN package Revised Figure 3-1 on page 11. Changed 7HHH to 1HHH. Revised Figure 3-1 on page 11. Changed 8000H to 2000H. Changed document status from Preliminary Specification to Data Sheet.
02
Mar 2005
03 04 05
Mar 2006 Apr 2006 May 2006
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, CA 94086 Telephone 408-735-9110 Fax 408-735-9036 www.SuperFlash.com or www.sst.com
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FlashFlex51 MCU

SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD

2006 Silicon Storage Technology, Inc. S71255-05-000 5/06 1

FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD

FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD

FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD

2006 Silicon Storage Technology, Inc.

FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD

FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD

1.0 FUNCTIONAL BLOCKS

8051 CPU Core

Flash Control Unit

SuperFlash EEPROM Primary Block 8K/16K/32K x8 Secondary Block 8K x8

PCA Enhanced UART

1-1: Functional Block Diagram

2006 Silicon Storage Technology, Inc.

FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD

2.0 PIN ASSIGNMENTS

P1.4 (CEX1 / SS#)

P1.1 (T2 EX)

P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7)

EA# ALE/PROG#? PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13)

1255 40-wqfn QI P1.0

2-1: Pin Assignments for 40-contact WQFN

2006 Silicon Storage Technology, Inc.

FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD

P1.1 (T2 EX)

40-pin PDIP Top View 33 32 9 31 10 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21

44-lead TQFP Top View

P2.2 (A10) P2.1 (A9) P2.0 (A8)

2-2: Pin Assignments for 40-pin PDIP

2-3: Pin Assignments for 44-lead TQFP

P1.4 (SS# / CEX1)

P1.1 (T2 EX)

44-lead PLCC Top View

1255 44-plcc NJ P3.0

2-4: Pin Assignments for 44-lead PLCC

2006 Silicon Storage Technology, Inc.

FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD

2.1 Pin Descriptions

2-1: Pin Descriptions (1 of 2)

I/O with internal pull-ups

P1[0] P1[1] P1[2] P1[3]

I/O with internal pull-up

I/O with internal pull-up

P3[0] P3[1] P3[2] P3[3]

2006 Silicon Storage Technology, Inc.

FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD

2-1: Pin Descriptions (Continued) (2 of 2)

I/O with internal pull-ups

I/O I/O I/O I/O I O I I

2006 Silicon Storage Technology, Inc.

FlashFlex51 MCU SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD

3.0 MEMORY ORGANIZATION

3.1 Program Flash Memory

EA# = 1 SFCF[1:0] = 10, 11

2000H 1FFFH 0000H 0000H