FIRST/ SECOND SEMESTER 2022-2023
Course Handout Part II
Date: 16-01-2023
In addition to part-I (General Handout for all courses appended to the time table) this portion gives further
specific details regarding the course.
Course No. : CS/ECE/EEE/INSTR F241
Course Title : Microprocessor Programming and Interface
Instructor-in-Charge : Dr. Subhradeep Pal
Team of Instructors : Prof. Runa Kumari, Dr. Sourav Nandi, Dr. Gopal Krishna Kamath,
Dr. Atri Mukhopadhyay
Scope and Objective of the Course:
The objective of this course is to become familiar with the processor internal architecture and its operation
within the area of manufacturing and performance. This course will provide the instruction set of an Intel
microprocessor 8086 – 80486, programmers model of processor, demonstration of the modular assembly
programming using the various addressing modes, data transfer instructions, subroutines, macros etc.; Timing
diagrams; Concept of interrupts: hardware & software interrupts, Interrupt handling techniques, Interrupt
controllers; Types of Memory & memory interfacing; Programmable Peripheral devices and I/O Interfacing;
DMA controller and its interfacing: Design of processor based system. This course familiarizes the students
with the programming and interfacing of microprocessors, which will help in solving basic binary math
operations using the microprocessor and provide a strong foundation for designing real world applications using
microprocessors.
Textbooks:
1. T1: Barry B. Brey, The Intel Microprocessors: Architecture, Programming and Interfacing, Pearson, 8 th
Edition, 2009.
Reference books
1. R1: D. V. Hall, Microprocessor and Interfacing, Tata McGraw Hill, 2nd Edition.
2. R2: L. B. Das, The x86 Microprocessors, 2nd Edition, Pearson.
3. R3: N. Senthil Kumar, M. Saravanan, and S. Jeevanathan, Microprocessors and Microcontrollers,
Oxford University Press.
Course Plan:
Chapter in the
Lec. No. Learning objectives Topics to be covered
Text Book
Introduction to microprocessors,
Historical background, Basics of
Introduction to microprocessor T1: Chap. 1
1-2 computer architecture, Memory & I/O
and microcomputers R1: Chap. 1
organization, CISC, RISC, EPIC
Processors and Flynn’s Taxonomy
Detailed architecture of 8086, Pin
T1: Chap. 2 and 9
3-4 Architecture of 8086 configurations of 8086, Modes of
R1: Chap. 2
Operation, Clocking and Buses
Assembly Language
5-6 Addressing Modes T1: Chap. 3
Programming: Part I
Instruction set of 8086: Data transfer,
Assembly Language logical, arithmetic, flag manipulation, T1: Chap. 4-8
7-10
Programming: Part II control transfer, rotate, string, processor R3: Chap. 13
control instructions.
Assembly Language ALP Examples and practical examples of T1: Chap. 4-8
11-13
Programming: Part III usage of 8086 R3: Chap. 14
Types of 8086 interrupts, vector table,
T1: Chap. 12
14-15 Interrupts priority among 8086 interrupts, interrupt
R3: Chap. 15
service routine, practical examples
Physical Memory Organization of 8086,
Memory Devices, Address Decoding, T1: Chap. 10
16-19 Memory Interface
Memory Interface: Interfacing RAM and R3: Chap.16
EPROM using logic gates/ decoder ICs.
Basic I/O, I/O Instructions, I/O mapped
and memory mapped I/O, Interfacing with T1: Chap. 11
20-24 I/O Interface
8-bit I/O devices, I/O port address R3: Chap. 16
decoding
8255: General purpose PPI
Programmable Peripheral 8254: Programmable Interval Controller T1: Chap. 11
25-28
Devices 8259: Programmable Interrupt Controller T1: Chap. 12
ADCs and DACs
8237: Basic Operation, Pin Details,
T1: Chap. 13
29-31 DMA Controller Features, Architecture, DMA
R3: Chap. 7
Initialization, Operation with 8086
32-34 Bus Interface ISA, PCI, USB etc T1: Chap. 15
T1: Chap. 16
35-37 Advanced Processor Part I 80186-80286
R1: Chap. 15
T1: Chap. 17
38-40 Advanced Processor Part II 80386 and 80486
R1: Chap 15
8087: Pin layout, Architecture, Registers,
Lecture
41-42 Coprocessor for x86 family Interfacing with 8086, Instruction Set,
Notes/Slides
Application examples
Evaluation Scheme:
Sl. Weightage Nature of
Component Duration Marks Date & Time
No. (%) Component
13/03 11.30 -
1. Mid-Term Examination 90 mins. 30% 90 Closed Book
1.00PM
3 Announced Quizzes with 30 mins.
2. 10% 30 TBA Closed Book
(n-1) scheme Each
Regular Lab Evaluations 120 mins. / As per
3. 17% 50 Open Book
with (n-1) scheme week timetable
Comprehensive Lab Exam
4. 30 mins 3% 10 TBA Open Book
Quiz Test
5. Comprehensive Examination 3 hours 40% 180 08/05 AN Closed Book
Chamber Consultation Hour: Will be announced in the class.
Notices: All notices will be displayed via CMS only.
Make-up Policy:
1. Both announced quizzes and regular lab evaluations as both will follow (n-1) scheme strictly.
2. Make will be allowed for mid-term and end-term examination only to the genuine cases with prior
intimation.
Academic Honesty and Integrity Policy:
Academic honesty and integrity are to be maintained by all the students throughout the semester and no type of
academic dishonesty is acceptable.
INSTRUCTOR-IN-CHARGE
