Coverage:
EDA simulator tool will generate the below coverage types, when we enable tool
to generate coverage, and run simulation
1. Statement coverage
2. Block coverage
3. Conditional/Expression coverage
4. Branch/Decision coverage
5. Toggle coverage
6. FSM coverage
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1. Statement coverage /Line coverage
• Example :
always @(posedge clock)
begin
if(x == y) begin => Statement 1
out1 = y; => Statement 2
out2 = y^2 + y^2; => Statement 3
end
else begin => Statement 4
out1 = x+y; => Statement 5
out2 = y*y; => Statement 6
end
end
• Each line needs to be to covered by your stimulus or test bench, each line in the
always block represents block.
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2. Block coverage
• Example :
always @(posedge clock)
begin => Block 1 [always block]
if(x != y) begin => Block 2 [If block]
out1 = x+y*y
out2 = x^2 + y^2;
else => Block 3 [Else block]
out1 = x-y;
out2 = y+x;
end
• Each begin end creates a block ,test bench should able to cover it with its stimulus
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3. Conditional/Expression coverage
• Example :
x= y ? 1:0 ;--Conditional coverage which has two conditions
4. Branch/Decision coverage
• Example :
always @(posedge clock)
begin
if(x == y) begin => Branch [If branch]
out1 = x+y;
out2 = x^2 + y^2;
end
else begin => Branch [else branch]
out1 = x-y;
end
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5. Toggle coverage
Example :
x= y ? 1:0 ;--X and y sould be toggled from 0 and 1
6. FSM coverage
Example :
case(state)
IDLE : if (req_0 == 1'b1) begin
end
STATE0 :
STATE1:
All the above states and transition from each state needs to be covered
By covering all the above coverage with the test cases and test bench shows that,
test bench is powerful to generate the stimulus for the Verilog (RTL) code.
