DCD Assignment-3

1.List out the operators in Verilog.

Ans:
In Verilog, the operators can be categorized into several types:
1. Arithmetic Operators: +, -, *, /, %
2. Relational Operators: ==, !=, <, >, <=, >=
3. Logical Operators: &&, ||, !
4. Bitwise Operators: &, |, ^, ~, ^~ (XNOR)
5. Shift Operators: << (left shift), >> (right shift)
6. Reduction Operators: &, |, ^, ~&, ~|, ~^
7. Assignment Operators: =, <= (non-blocking)

2. Explain the following terms:

i) Simulation ii) Synthesis
Ans:
i) Simulation: Simulation is the process of verifying the functional behavior of a
hardware design by executing a Verilog or HDL model. It tests how the design
responds to inputs and helps identify logic errors before hardware implementation.
ii) Synthesis: Synthesis is the process of converting a high-level Verilog or HDL
description into a gate-level netlist. This step translates the design into hardware
components like logic gates and flip-flops, making it ready for physical
implementation on an FPGA or ASIC.
3.Define and give the syntaxes for the following with examples
i) always ii) case statement
Ans:
i) always block:
The always block in Verilog is used to describe behaviour that changes over time,
typically in response to changes in signals or at clock edges. It continuously
executes whenever its sensitivity list is triggered.
Example:
always @(posedge clk) begin
 q <= d; // Triggered on clock rising edge
end
ii) case statement:
The case statement is used for multi-way branching based on the value of an
expression. It simplifies conditions with multiple possibilities.
Example:
case(state)
2'b00: next_state = 2'b01;
2'b01: next_state = 2'b10;
default: next_state = 2'b00;
endcase
4. Define blocking and non-blocking assignments.
Ans:
Blocking Assignment (=):
A blocking assignment executes statements sequentially, meaning the next
statement will not be executed until the current one is complete. It behaves like
traditional programming assignments.
Non-blocking Assignment (<=):
A non-blocking assignment allows multiple assignments to occur simultaneously
by scheduling the update of variables for later (typically at the end of the current
time step). It is mainly used in sequential logic, such as flip-flops.
5. Sketch the gate level logic diagram of a 4:1 multiplexer. Develop a Verilog
code using gate level modelling.
Ans:
Gate-Level Logic Diagram of a 4:1 Multiplexer:
A 4:1 multiplexer has four inputs (I0, I1, I2, I3), two selection lines (S0, S1), and one
output (Y). The gate-level diagram consists of AND gates, OR gates, and NOT gates
to select the correct input based on the selection lines.
Gate Level Logic Diagram
Verilog Code:
module mux_4to1_gate(
input I0, I1, I2, I3, // 4 data inputs
input S0, S1, // 2 selection lines
output Y // Output
);
wire S0_n, S1_n;
wire AND0_out, AND1_out, AND2_out, AND3_out;
// Generate inverted selection lines
not(S0_n, S0);
not(S1_n, S1);
// AND gates for each input combination
and(AND0_out, I0, S1_n, S0_n); // I0 is selected when S1=0, S0=0
and(AND1_out, I1, S1_n, S0); // I1 is selected when S1=0, S0=1
and(AND2_out, I2, S1, S0_n); // I2 is selected when S1=1, S0=0
and(AND3_out, I3, S1, S0); // I3 is selected when S1=1, S0=1
// OR gate to combine the AND gates' outputs
 or(Y, AND0_out, AND1_out, AND2_out, AND3_out);
endmodule
6. Explain the following with examples:
i) Intra assignment delays ii) Inter assignment delays
Ans:
i) Intra-Assignment Delays:
Intra-assignment delays specify a time delay between the execution of the right-
hand side (RHS) and the assignment to the left-hand side (LHS) of a statement.
The RHS is evaluated immediately, but the LHS is updated only after the specified
delay.
Example:
a = #5 b + c;
here (b + c) is calculated right away, but the value is assigned to a after 5 time units.
ii) Inter-Assignment Delays:
Inter-assignment delays introduce a delay between two separate assignment
statements. This delay pauses the execution of the next assignment for the
specified time.
Example:
a = b + c; // Execute immediately
#10; // Wait for 10 time units
d = a - e; // Execute after the 10 time units delay
the value of a is updated immediately, but the next statement (assigning d) is delayed
by 10 time units.
7. Explain initial blocks, always blocks with examples.
Ans:
Initial Block:
An initial block in Verilog is executed only once at the start of simulation. It is used
to set initial conditions or to simulate stimulus that runs once. It is often used for
testbenches or initializing values.

Example:
initial begin
a = 0; // Set 'a' to 0 at time 0
b = 1; // Set 'b' to 1 at time 0
#10 a = 1; // After 10 time units, set 'a' to 1
End
Here, a and b are initialized at the start of simulation, and after 10 time units, a is
updated.
Always Block:
An always block is used to describe behavior that occurs continuously or in response
to events (like changes in signals or clock edges). It runs indefinitely in a loop during
simulation, triggering based on the sensitivity list.
Example:
always @(posedge clk) begin
q <= d; // Update 'q' with 'd' at every positive clock edge
end
Here, the always block is triggered on the rising edge of the clock (clk), and the
value of d is assigned to q using non-blocking assignment.
8. Write down a Verilog module for an SR flip-flop.
Ans:
Verilog Code for an SR Flip-Flop:
An SR (Set-Reset) flip-flop is a sequential logic circuit with two inputs, S (Set)
and R (Reset), and two outputs, Q and Q' (complement of Q). The behavior of
the SR flip-flop is as follows:
• If S = 1 and R = 0, the flip-flop is set, meaning Q = 1.
• If S = 0 and R = 1, the flip-flop is reset, meaning Q = 0.
• If both S = 0 and R = 0, the flip-flop retains its state.
• If both S = 1 and R = 1, it's an invalid state (typically not allowed in a
standard SR flip-flop).
Code:
module sr_flipflop (
 input S, R, clk, // Inputs: Set (S), Reset (R), Clock (clk)
output reg Q, // Output: Q
output Qbar // Output: Complement of Q (Q')
);
// Q' is the complement of Q
assign Qbar = ~Q;
// SR flip-flop behavior
always @(posedge clk) begin
if (S == 1 && R == 0) begin
Q <= 1; // Set the flip-flop
end
else if (S == 0 && R == 1) begin
Q <= 0; // Reset the flip-flop
end
else if (S == 1 && R == 1) begin
Q <= 1'bx; // Invalid state
end
// If S == 0 and R == 0, Q retains its previous state
end
endmodule

9. Describe the levels of abstraction in Verilog with example.

Ans:
Levels of Abstraction in Verilog
Verilog supports four distinct levels of abstraction that allow designers to model
hardware systems at different levels of detail. These abstraction levels help in
representing both high-level behaviour and low-level gate/transistor
functionality of digital circuits. The four levels are:
1. Behavioural Level
2. Dataflow Level
3. Gate-Level
4. Switch-Level
1. Behavioural Level
• Description:
The behavioural level is the highest level of abstraction. It describes what the
system does, not how it does it. At this level, the designer focuses on the
functionality without worrying about how the hardware is implemented. This
is often used in testbenches or when describing complex algorithms.
Example:
A Verilog code for an 8-bit counter using the behavioural level:
module counter (
input clk, reset,
output reg [7:0] count
);
always @(posedge clk or posedge reset) begin
if (reset)
count <= 8'b0; // Reset count to 0
else
count <= count + 1; // Increment count
end
endmodule
2. Dataflow Level
• Description:
The dataflow level focuses on how data moves through the system,
emphasizing the flow of data between registers and combinational logic. It
uses continuous assignment statements (assign) to define how the inputs
affect the outputs using Boolean expressions.
Example:
A Verilog code for a 4:1 multiplexer using the dataflow level:
module mux_4to1 (
input [1:0] sel, // Selection lines
input [3:0] in, // Inputs
output out // Output
);
assign out = (sel == 2'b00) ? in[0] :
(sel == 2'b01) ? in[1] :
(sel == 2'b10) ? in[2] :
in[3]; // Output based on selection lines
endmodule
3. Gate-Level
• Description:
At the gate level, the design is modeled in terms of logic gates like AND, OR,
NOT, etc. This level provides a detailed view of how the design is
implemented using basic logic gates and flip-flops.
Example:
A Verilog code for a 2-input AND gate using the gate level:
module and_gate (
input a, b,
output y
);
and (y, a, b); // AND gate primitive
endmodule
4. Switch-Level
• Description:
The switch-level abstraction is the lowest level in Verilog, describing the
design in terms of transistors (MOSFETs). At this level, switches (nmos,
pmos) are used to model transistors and their interconnections. It is typically
used for very low-level transistor-level design and verification.
Example:
A Verilog code for a simple CMOS inverter using switch-level modelling:
module cmos_inverter (
input a,
output y
);
wire n1;

// nMOS transistor
nmos (n1, y, a); // drain, source, gate

// pMOS transistor
pmos (y, 1'b1, a); // drain, source, gate
endmodule
10.Develop a Verilog description using gate level modeling for a 4-Bit ripple
carry adder. Instantiate a full adder and use it as a building block to
model the 4-Bit ripple carry adder.
Ans:
// Full Adder Module
module full_adder (
input A, // First input
input B, // Second input
input Cin, // Carry input
output Sum, // Sum output
output Cout // Carry output
);
// Internal wire for intermediate sum
wire S1, C1, C2;
 // Sum logic
xor (S1, A, B); // Intermediate sum
xor (Sum, S1, Cin); // Final sum

// Carry logic
and (C1, A, B); // Carry from A and B
and (C2, S1, Cin); // Carry from intermediate sum and Cin
or (Cout, C1, C2); // Final carry out
endmodule

// 4-Bit Ripple Carry Adder Module

module ripple_carry_adder (
input [3:0] A, // 4-bit input A
input [3:0] B, // 4-bit input B
input Cin, // Carry input
output [3:0] Sum, // 4-bit sum output
output Cout // Final carry output
);
// Internal carry wires
wire C1, C2, C3; // Carry outputs from each full adder

// Instantiate the first full adder

full_adder FA0 (
.A(A[0]),
.B(B[0]),
.Cin(Cin),
 .Sum(Sum[0]),
.Cout(C1)
);

// Instantiate the second full adder

full_adder FA1 (
.A(A[1]),
.B(B[1]),
.Cin(C1),
.Sum(Sum[1]),
.Cout(C2)
);

// Instantiate the third full adder

full_adder FA2 (
.A(A[2]),
.B(B[2]),
.Cin(C2),
.Sum(Sum[2]),
.Cout(C3)
);

// Instantiate the fourth full adder

full_adder FA3 (
.A(A[3]),
.B(B[3]),
.Cin(C3),
 .Sum(Sum[3]),
.Cout(Cout)
);

endmodule
11.Write down names of basic gate primitives in Verilog and briefly explain
how they are instantiated.
Ans:
Basic gate primitives represent the fundamental logic gates used in digital
circuits. These primitives include AND, OR, NOT, NAND, NOR, XOR, and
XNOR gates
Detailed Explanation of Each Gate Primitive:
1. AND Gate:
wire y;
and (y, a, b); // y = a AND b
o Operation: Outputs 1 if both a and b are 1.
2. OR Gate:
wire y;
or (y, a, b); // y = a OR b
o Operation: Outputs 1 if at least one of a or b is 1.
3. NOT Gate:
wire y;
not (y, a); // y = NOT a
o Operation: Outputs 1 if a is 0 and vice versa.

4. NAND Gate:
wire y;
nand (y, a, b); // y = NOT (a AND b)
o Operation: Outputs 0 only if both a and b are 1.
5. NOR Gate:
wire y;
nor (y, a, b); // y = NOT (a OR b)
o Operation: Outputs 1 only if both a and b are 0.
6. XOR Gate:
wire y;
xor (y, a, b); // y = a XOR b
o Operation: Outputs 1 if exactly one of a or b is 1.
7. XNOR Gate:
wire y;
xnor (y, a, b); // y = NOT (a XOR b)
o Operation: Outputs 1 if both a and b are the same (both 0 or both 1).
12.Write a Verilog behavioural description for a 4-bit up counter.
Ans:.
Verilog Code
module up_counter (
input clk, // Clock input
input reset, // Asynchronous reset
output reg [3:0] count // 4-bit output for the counter
);
// Always block triggered on the rising edge of the clock or reset
always @(posedge clk or posedge reset) begin
if (reset) begin
count <= 4'b0000; // Reset the counter to 0
end else begin
 count <= count + 1; // Increment the counter by 1
end
end
endmodule