A System Verilog Testbench
Constructs
By
Santosh Krishna M
We will discuss about
Top SystemVerilog Testbench Constructs
Program
Interface
Clocking Block
modports
Program Block
The testbench (program) runs separately
from design (module)
• Triggered by clock
• Samples just before clock edge, drives just after clock
clock
Design
Testbench
Sample Drive
inputs outputs
Program Block
Benefits:
• Encapsulates the testbench
• Separates the testbench from the DUT
• Provides an entry point for execution
Functionality:
• Can be instantiated in any hierarchical location
Typically at the top level
• Ports can be connected in the same manner as any
other module
• Executes in the SV reactive region
Program Block
• It does not allow always block. Only initial and methods
are allowed, which are more controllable.
• Each program can be explicitly exited by calling the
$exit system task. Unlike $finish, which exits simulation
immediately, even if there are pending events.
Fork .... join
fork...join block always causes the process executing the fork
statement to block until the termination of all forked processes
program main ;
initial
begin
#10;
$display(" BEFORE fork time = %d ",$time );
fork
begin
# (20);
$display("time = %d # 20 ",$time );
end
begin
#(10);
$display("time = %d # 10 ",$time );
end
begin
#(5);
$display("time = %d # 5 ",$time );
end
join_none
$display(" time = %d Outside the main fork ",$time );
#(40);
end
endprogram
RESULTS
BEFORE fork time = 10
time = 10 Outside the main fork
time = 15 # 5
time = 20 # 10
time = 30 # 20
program main ;
initial begin
#(10);
$display(" First fork time = %d ",$time );
fork
begin
# (20);
$display("time = %d # 20 ",$time);
end
begin
#(10);
$display("time = %d # 10 ",$time);
end
begin
#(5);
$display("time = %d # 5 ",$time);
#(2);
$display("time = %d # 2 ",$time);
end
join_any
$display(" time = %d Outside the main fork ",$time );
#(40);
end
endprogram
RESULTS:
First fork time = 10
time = 15 # 5
time = 17 # 2
time = 17 Outside the main fork
time = 20 # 10
time = 30 # 20
program main ;
initial
begin
#(10);
$display(" BEFORE fork time = %d ",$time );
fork
begin
# (20);
$display("time = %d # 20 ",$time );
end
begin
#(10);
$display("time = %d # 10 ",$time );
end
begin
#(5);
$display("time = %d # 5 ",$time );
end
join
$display(" time = %d Outside the main fork ",$time );
#(40);
end
endprogram
RESULTS
BEFORE fork time = 10
time = 15 # 5
time = 20 # 10
time = 30 # 20
time = 30 Outside the main fork
Disable fork
The disable fork statement terminates all active descendants
(subprocesses) of the calling process.
If any of the child processes have descendants of their own, the
disable fork statement shall terminate them.
Sometimes, it is required to kill the child processes after certain
condition.
program main();
initial begin
#(10);
$display(" BEFORE fork time = %0d ",$time );
fork
begin
# (20);
$display(" time = %0d # 20 ",$time );
end
begin
#(10);
$display(" time = %0d # 10 ",$time );
end
begin
#(5);
$display(" time = %0d # 5 ",$time );
end
join_any
$display(" time = %0d Outside the main fork ",$time );
disable fork;
$display(" Killed the child processes");
end
endprogram
RESULTS
BEFORE fork time = 10
time = 15 # 5
time = 15 Outside the main fork
Killed the child processes
Interface
Bundling of port signals
• Provide an abstract encapsulation of communication
between blocks
• Directional information (modports)
• Timing (clocking blocks)
device1 interface device2
Interface
Interface:An example
Interface bus_a (input clock);
logic [7:0] address;
logic [31:0] data ;
bit valid ;
bit rd_wr ;
Endinterface: bus_a
Clocking Block
Specify synchronization characteristics of the
design
Offer a clean way to drive and sample signals
Can be declared inside interface, module or
program
Clocking Block
Features
• Clock specification
• Input skew, output skew
• Cycle delay (##)
Clocking Block
Interface inter(input clk);
logic enin;
logic [31:0] din ;
bit enout ;
bit [31:0] dout ;
Signals will be sampled
2ns before posedge ck
clocking cb @(posedge ck);
default input #2ns output #3ns;
input enout, dout;
Signals will be driven
output ein,din;
3ns after posedge ck
endclocking:cb
endinterface
Modports
An interface can have multiple viewpoints
• Master/Slave, Transmitter/Receiver
These can be specified using modports
All signal names
Interface bus_b (input clock);
in a modport must
be declared in the
logic [7:0] addr,data;
interface
logic [1:0] mode ;
bit ready ;
modport master (input ready,output addr,data,mode) ;
modport slave (input addr,data,mode,output ready) ;
endinterface: bus_b
Thank you
