Embedded Tutorial Solutions-1
Embedded Tutorial Solutions-1
Embedded Tutorial Solutions-1
Q. A watchdog timer that uses two cascaded 16 bit up counters as shown in figure below
is connected to an 11.981 MHz oscillator. A timeout should occur if the function
watchdog_reset is not called in 5 minutes. What is the value that should be loaded into
the counter pair when the function is called?
Sol:
The question asks for the value that should be loaded into the counter pair of a watchdog timer
when the function watchdog_reset is called. The watchdog timer uses two cascaded 16-bit up
counters and is connected to an 11.981 MHz oscillator. A timeout should occur if the function
watchdog_reset is not called within 5 minutes.
AG
Steps to solve:
Write driver to support LM75A digital temperature sensor through I2C. Assume APIs for
I2C interface as listed below are available.
uint32_t I2C_Addr (uint8_t adr, uint8_t dir); //adr: Device address dir: direction bit
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//Return type of the these functions is 1 used to indicate error condition otherwise 0. //
I2C_Addr(..), I2C_Write(…) waits for acknowledgement. If no acknowledgement error is
condition is generated.
Sol:
void LM75_Read (int8_t slaveadd, int8_t pointer, int8_t size, int8_t *pointerD);
void LM75_Write(int8_t slaveadd, int8_t pointer, int8_t size, int8_t *pointerD);
void LM75_Configuration(int8_t slaveadd, int8_t config, int16_t tempos, int 16_t temphys)
{
int8_t Pdata = Config;
int8_t array[2];
LM75_Write(slaveadd, 0x01, 1, &Pdata);
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temphys *= 2;
array[0] = ((temphys<< 7) & 0xFF00)>>8
array[1] = (temphys << 7)& 0xFF
LM75_Write(slaveadd, 0x02, 2, array);
Solution:
(SPI can be used but the design will be complex so , we will be giving manual data inputs ,
using GPIOs)
Connections:
PA1 - GPIO_Input -> SDO
PA2 - GPIO_Output -> SCLK
PA0 - GPIO_Output -> CS bar
VDD and Vref both to High (VDD)
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GND - GND
AIN - Analog Input to a Analog sensor
NC - No connection
#include "main.h"
void SystemClock_Config();
void MX_GPIO_Init();
void main() {
HAL_Init();
SystemClock_Config();
MX_GPIO_Init();
while(1) {
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, GPIO_PIN_RESET);
for(int i=0; i<16; i++){
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_SET);
HAL Delay (1);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_RESET);
AG
HAL-Delay (1);
if (i<12) {
adcOut = HAL_GPIO_ReadPin(GPIOA,GPIO_PIN_1);
adcout<<= 1;
}
}
HAL-Delay(1);
}
Solution:
#include "main.h"
I2C_HandleTypeDef hi2c1;
int main(void) {
// Initialize HAL, system clock, I2C1, etc.
AGHAL_Init();
SystemClock_Config();
MX_I2C1_Init();
Design software code to use ADC and WDT. The system is expected to complete analog
to dgital conversion in 50 msec, otherwise reset may be issued to recover from probable
transient error. HAL functions of ADC can be found in next slide.
HAL generated:
ADC_HandleTypeDef hadc1; //ADC handler
AG
void MX_ADC1_Init();
Solution:
‘
#include “main.h”
ADC_HandleTypeDef hadc1;
IWDG_HandleTypeDef hiwdg;
void SystemClock_Config();
static void MX_GPIO_Init();
void MX_ADC1_intit();
void MX_ADC1_Init();
uint32_t analogValue;
int main(){
HAL_Init();
SystemClock_Config();
MX_GPIO_Init();
MX_ADC1_Init();
MX_IWDG_Init();
while(1){
HAL_ADC_Start(&hadc1);
HAL_IWDG_Init(&hiwdg);
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AG
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Unit 2
Tutorial -03 Unit 2
Q.A cache has 512KB capacity,4B word,64B block size and 8 way set associative. The
system is using 32 bit address. Given the address 0xABC89984, which set of cache will
be searched and specify which word of the selected cache block will be forwarded if it is
a hit in cache?
AG
Detailed Solution:
Cache Size = E * B * S
Block Size = 64Bytes
E = no. of lines per set = 8 (since 8 way set associative)
Cache size = 512KB
S = 512K/8*64 = 1024
WKT, S = 2^s
s= no. of sets = 10 byte
b= no. of bytes per line
B = 2^b => b= 6 byte
Since 4Byte is one word in cache, so for offset it will be 6 - 4 =2
16bits - tag
10bits - set
Remaining 6bits - offset + word index
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Unit 2 tutorial 1b
Design the memory hierarchy to achieve an effective memory access time t=10.04us with
cache hit ratios h1=0.98 and a hit ratio h2=0.9 in the main memory . Also limit the total
cost of the memory hierarchy is upper bounded by $15,000.
Solution:
Tutorial 1a Unit 2
Q.Perform capacity planning for a two level memory hierarchy system. The first level, M1
is a cache with three capacity choices 64 Kbytes, 128 Kbytes and 256 Kbytes. The
second level, M2 is a main memory with a 4 Mbyte capacity. Let C1 and C2 be the cost
per byte and t1 and t2 the access times for M1 and M2 respectively. Assume C1 =20C2
and t2 =10t1. The cache hit ratios for the three capacities are assumed to be 0.7, 0.9 and
0.98 respectively.
i) What is the average access time ta in terms of t1=20ns in the three cache designs?
ii) Express the average byte cost of the entire memory hierarchy if C2=$0.2/Kbyte.
iii) Compare the three memory designs and indicate the order of merit in terms of
average costs and average access times respectively. Choose the optimal design based
on the product of average cost & average access times.
Solution:
i) The average access time ta in terms of t1=20ns in the three cache designs can be calculated
as follows:
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(Unit 2 tutorial 2)
Q. Show Hamming code parity bits calculation for data bits 111011100011101. Show
decoding of data by considering single bit errors and multi bit errors.
Data : 111011100011101
123456789012345678901
?_1_110_1110001_11101
Position -1 check 1 leave 1
No. of 1 = 8 even parity
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0?1_110_1110001_11101
Position -2 check 2 leave 2
No. of 1 = 7 odd parity
011?110_1110001_11101
Position -4 check 4 leave 4
No. of 1 = 4 even
0110110?1110001_11101
Position -8 check 8 leave 8
No. of 1 = 4 even
011011001110001?11101
Position -16 check 16 leave 16
No. of 1 = 4 even
AG
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Unit 1
Tutorial 2 Unit 1
A new multimedia unit (MU) is added to a processor, which accelerates the
completion of multimedia instructions given to the processor by four times.
Assuming a program consists of 40% multimedia instructions, what is the
overall speedup gained while running the program when it is executed on
the processor with the new MU compared to when it is run on the
processor without this MU? Use Amdahl’s Law to calculate.
Solution:
Amdahl’s Law :
Where
● Soverall is the overall speedup.
● P is the fraction of the workload that benefits from the enhancement.
● S enhanced is the speedup factor for the enhanced portion.
AG
4 times accelerated => S enhanced = 4
P = 40% = 0.4
S overall = 1.428
Tutorial 4 Unit 1:
The execution times (in seconds) of three programs on three MCUs are given below:
Solution
𝑀𝐼𝑃𝑆 = 𝐶𝑙𝑜𝑐𝑘𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦/𝐶𝑃𝐼∗1,000,000
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For MCU A:
For MCU B: