CMOS ASIC Design Course Project Report

Title: Design of 8-bit Counter and RTL to GDSII Implementation

Objective: To design an 8-bit counter using Verilog and implement the complete flow from RTL
(Register Transfer Level) to GDSII (Graphic Data System II).

1. Introduction

This project involves the design and implementation of a CMOS 8-bit counter. The design flow
follows the standard ASIC design process, beginning with the RTL design in Verilog, synthesis, and
timing analysis using Cadence Genus, and layout generation in Cadence Innovus. The counter
increments its value on every clock pulse, resets to zero upon reset, and signals completion after
reaching its maximum value (255).

2. Design Specifications

 Technology Node: 180 nm

 Clock Frequency: 30 MHz

 Design Functionality:

o The counter increments from 0 to 255.

o Upon reaching 255, the counter resets to 0 and asserts the count_done signal.

Verilog Code:

module counter_8bit(clk, rst_n, cnt_enb, count, count_done);

input clk;

input rst_n;

input cnt_enb;

output reg [7:0] count;

output reg count_done;

always @(posedge clk) begin

if (~rst_n || ~cnt_enb) begin

count <= 8'd0;

count_done <= 1'b0;

end else begin

if (count == 8'b11111111) begin

count_done <= 1'b1;

end else begin

count_done <= 1'b0;

count <= count + 8'd1;

end

end

end

endmodule

3. Synthesis Using Cadence Genus

The synthesis of the Verilog code was performed using Cadence Genus, targeting the 180nm
technology node. The following commands were used:

set_db common_ui false;

set_attribute library /cad_area/install/FOUNDRY/digital/180nm/dig/lib/slow.lib;

set_attr lef_library /cad_area/install/FOUNDRY/digital/180nm/dig/lef/all.lef;

read_hdl counter_8bit.v;

elaborate;

set_top_module counter_8bit;

read_sdc counter.sdc;

set_db syn_generic_effort medium;

set_db syn_map_effort medium;

set_db syn_opt_effort medium;

syn_generic;

syn_map;

syn_opt;

report_area > counter_area.rep;

report_power > counter_power.rep;

report_gates > counter_gates.rep;

report_timing > counter_timing.rep;

generate_report -outdir REPORTS -tag Counter;

write_hdl > counter_8bit_syn_opt.v;

report_qor -levels_of_logic -power -exclude_constant_nets > counter_QOR1.rep;

4. SDC Constraints:

The following constraints were defined in the counter.sdc file:

create_clock -name clk -period 5 [get_ports clk]

set_input_delay 2 -clock [get_clocks clk] [get_ports rst_n]

set_input_delay 2 -clock [get_clocks clk] [get_ports cnt_enb]

set_output_delay 2 -clock [get_clocks clk] [get_ports count]

set_output_delay 2 -clock [get_clocks clk] [get_ports count_done]

5. Synthesis Results:

Area Report

Instance Module Cell Count Cell Area Net Area Total Area

counter_8bit 20 785.030 299.959 1084.989

Gate Summary

Gate Type Instances Area Library

ADDHXL 6 219.542 tsmc18

AND2X2 1 13.306 tsmc18

AOI2BB1XL 1 16.632 tsmc18

DFFHQX1 1 53.222 tsmc18

DFFTRX1 7 395.842 tsmc18

DFFTRXL 1 56.549 tsmc18

INVX1 1 6.653 tsmc18

NAND2X1 1 9.979 tsmc18

NAND3X1 1 13.306 tsmc18

Total 20 785.030

Area Distribution

Type Instances Area Area %

Sequential 9 505.613 64.4

Inverter 1 6.653 0.8

Logic 10 272.765 34.7

Total 20 785.030 100.0

Power Report

Category Leakage (W) Internal (W) Switching (W) Total (W) Row %

Memory 0.00000 0.00000 0.00000 0.00000 0.00%

Register 1.40552e-08 1.13336e-04 2.26773e-06 1.15618e-04 83.18%

Logic 1.07493e-08 4.64772e-06 5.01699e-06 9.67546e-06 6.96%

Clock 0.00000 0.00000 1.36994e-05 1.36994e-05 9.86%

Total 2.48045e-08 1.17983e-04 2.09841e-05 1.38992e-04 100.0%

Timing Summary

Metric Value

Slack (ps) 2189

Total Negative Slack 0

Failing Paths 0

6. Physical Design Using Cadence Innovus

The physical design was implemented in Cadence Innovus, following these steps:

1. Floorplanning:

o Defined the chip size and placed macro blocks.

o Allocated spaces for I/O and core areas.

o Created power and ground rings.

o Defined the power grid for reliable power distribution.

3. Placement:

o Placed standard cells optimally using automated placement tools.

o Designed a clock tree network to minimize skew and latency.

5. Routing:

o Routed the design while meeting all DRC (Design Rule Check) constraints.

6. GDSII Generation:

o Generated the final GDSII layout for fabrication.

7. Observations and Results:

 Functional Verification:

o Verified using RTL simulations and post-synthesis netlist simulations.

 Area, Power, and Performance:

o Area and power reports confirmed optimization within constraints.

o Timing analysis ensured no violations in critical paths.

 Layout:

o DRC and LVS clean layout achieved.

8. Conclusion:

The project successfully implemented an 8-bit counter from RTL to GDSII. The design met all
functional and performance requirements, demonstrating the efficacy of the design flow. The project
provided hands-on experience in digital design, synthesis, and physical design processes.