Embedded Systems with ARM Cortex-M3

Microcontrollers in Assembly Language and C

Chapter 20
Analog-to-Digital Converter (ADC)

Dr. Yifeng Zhu

Electrical and Computer Engineering
University of Maine

Spring 2015

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Analog-to-Digital Converter (ADC)
} ADC is important to almost all application fields
} Converts a continuous-time voltage signal within a given range
to discrete-time digital values to quantify the voltage’s
amplitudes

x(t) x(n)

ADC

quantize
continuous-time analog signal discrete-time digital values

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Analog-to-Digital Converter (ADC)
} Three performance parameters:
} sampling rate: number of conversions per second (thousands to milions)
} resolution: number of bits in ADC output (6 to 24)
} power dissipation: power efficiency of ADC
} Many ADC implementations:
} sigma-delta
} for apps requiring low sampling rate (<100 kHz) but high resolution (12-24 bit)
} e.g.: voice and audio apps in cell phones
} successive-approximation (SAR)
} for low-power data acquisitions w/ moderate sampling rates (<5MHz)
} e.g.: STM32 microcontrollers
} pipelined
} for high-speed apps (sampling rate > 5MHz) and relatively low resolution
} e.g.: radar communication
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 Resolution
} Resolution is determined by number of bits (in binary) to represent an analog input.
} Example of two quantization methods (N = 3)

½Δ
Δ

𝑉 𝑉
𝐷𝑖𝑔𝑖𝑡𝑎𝑙 𝑅𝑒𝑠𝑢𝑙𝑡 = 𝑓𝑙𝑜𝑜𝑟 2! × 𝐷𝑖𝑔𝑖𝑡𝑎𝑙 𝑅𝑒𝑠𝑢𝑙𝑡 = 𝑟𝑜𝑢𝑛𝑑 2! ×
𝑉"#$ 𝑉"#$
Max quantization error = Δ = VREF/23 Max quantization error = ±½ Δ = ±VREF/24
4 𝑟𝑜𝑢𝑛𝑑 𝑥 = 𝑓𝑙𝑜𝑜𝑟(𝑥 + 0.5)
Quantization Error
} For N-bit ADC, it is limited to ±½Δ
} Δ = is the step size of the converter.

} Example: for 12-bit ADC and input voltage range [0, 3V]

1 3𝑉
𝑀𝑎𝑥 𝑄𝑢𝑎𝑛𝑡𝑖𝑧𝑎𝑡𝑖𝑜𝑛 𝐸𝑟𝑟𝑜𝑟 = ∆= = 0.367𝑚𝑉
2 2×2!"

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Minimum Sampling Rate:
Nyquist–Shannon Sampling Theorem
} In order to be able to reconstruct the analog input signal, the sampling rate
should be at least twice the maximum frequency component contained in
the input signal
} Example of two sine waves have the same sampling values. This is called
aliasing.

from wiki.com

} Antialiasing (beyond the scope of this course)

} Pre-filtering: use analog hardware to filtering out high-frequency components and only
sampling the low-frequency components. The high-frequency components are ignored.
} Post-filtering: Oversample continuous signal, then use software to filter out high-frequency
components

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Successive-approximation (SAR) ADC

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 Determining Minimum Sampling Time

𝒕
&𝑻 Sampling time is software
𝑽𝑪 𝒕 = 𝑽𝒊𝒏 ×(𝟏 − 𝒆 𝒄)
programmable!

Smaller sampling error

Larger sampling time Tradeoff
Slower ADC speed

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Programming ADC Sampling Time

4 cycles
9 cycles
HSI Clock ADC Clock
Prescaler 16 cycles

Selection
16 MHz /1, /2, /4
24 cycles
default prescaler = 1 48 cycles
96 cycles
192 cycles
384 cycles

ADC sample time register (SMPR)

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Successive-approximation (SAR) ADC

• Binary search algorithm to

gradually approaches the
input voltage
• Settle into ±½ LSB bound
within the time allowed

𝑇)*+ = 𝑇,-./0123 + 𝑇+42567,142

𝑇+42567,142 = N×𝑇)*+_+049:

𝑇%&'()*+, is software configurable

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ADC Conversion Time
𝑇<=> = 𝑇?@ABCDEF + 𝑇>GEHIJ?DGE

Suppose ADCCLK = 16 MHz and Sampling time = 4 cycles

For 12-bit ADC

𝑇<=> = 4 + 12 = 16 𝑐𝑦𝑐𝑙𝑒𝑠 = 1𝜇𝑠

For 6-bit ADC

𝑇<=> = 4 + 6 = 10 𝑐𝑦𝑐𝑙𝑒𝑠 = 625𝑛𝑠

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Data Alignment

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ADC: Regular vs injected

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ADC Mode

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ADC Mode
Regular channel:
1. Set SWSTART in ADC_CR2
2. The channel is selected by SQ1[4:0]
in SQR5
3. Result is stored in ADC_DR
4. EOC is set after conversion
5. Interrupt is generated if EOCIE is set

Injected channel:
1. Set JSWSTART in ADC_CR2
2. The channel is selected by JSQ1[4:0]
in JSQR
3. Result is stored in ADC_JDR1
4. JEOC is set after conversion
5. Interrupt is generated if JEOCIE is set

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ADC Mode

} Channels are selected by

ADC_SQRx registers for regular
channels, and by ADC_JSQR register
for injected channel

} All channels in a regular group share

the same result register ADC_DR.
Make sure to read data between
consecutive sampling.

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VREF
} Some chips does not expose VREF to a pin
} STM32L LQFP64 does not have VREF pin
} STM32L LQFP100 does
} Infer internal VREF
Corresponds to VREF
} How?

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Analog Watchdog
Analog voltage
Two programmable thresholds

Higher threshold (HTR)

Guarded Area
Lower threshold (LTR)

} If V < VLTR or V > VHTR, the analog watchdog (AWD) flag (in ADC Status
Register) is set, generating an interrupt to the processor
} The monitor is automatically performed by hardware, not software
} Convenient and efficient feature
} Help processor detect exceptions and recover from specific situations
} For example, monitor sensor data and raise alarm on some level.

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Example: ADC with Timer Interrupts
Main program

ADC
Set up timer timer
interrupt
interrupt
Timer ADC
Timer ISR
Peripheral Peripheral

Wait for Set ADC_Done flag ADC ISR

DAC_Done = 1

Process Data
} ISR = Interrupt Service Routine
} TIMER ISR starts ADC
Repeat } ADC samples multiple channels
} ADC ISR copies ADC data register to memory

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Example: ADC with Timer and DMA
Main program
Set up DMA
Set up timer timer
sampling
interrupt
channels DMA
Timer ADC Controller
Timer ISR
Peripheral Peripheral

Wait for Set DMA_Done flag

DMA_Done = 1

Process Data
} Timer ISR starts ADC and DMA
} DMA automatically copies ADC results
Repeat of multiple channels to memory after
each conversion

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