MOS Capacitor

1
 MOS Capacitor Structure

Schematic cross section of an n-Channel MOSFET with VG

MOS capacitor bias at VS = VD= 0

2
 Ideal MOS Capacitor
Key assumptions:
✓ Metal is an equipotential region.
✓ Oxide is a perfect insulator with zero current flow.
✓ Neither oxide nor oxide-semiconductor interface have charge centers.
✓ Semiconductor is uniformly doped.
✓ An ohmic contact has been established on the back side of the wafer.
✓ Analysis will be one-dimensional.
✓ The semiconductor is thick enough to have a quasi-neutral region
(where electric field is zero and all energy bands are flat).

Note : The assumption of an equipotential surface in the metal simply states

that a perfect conductor can not support and electric field.

3
 Vacuum level
Energy band diagram
0.95 eV
  electron affinity Ec
qΦm = 4.10 eV q = 4.05 eV
Φ  work function qΦs

Ef Ec
Eg
 s =  + 2q +F metal Eg  8-9 eV Ei
qϕF
Ef
Ev
kT  N A  p-type
F = ln  semiconductor
q  ni 
Ev
Oxide
Ideal MOS Capacitor

Φm = Φs i.e. Φms = 0
Uniform silicon doping

All charges equal zero

4
 Vacuum level
Energy band diagram
0.95 eV
  electron affinity Ec
qΦm = 4.10 eV q = 4.05 eV
Φ  work function qΦs

Ef Ec
Eg
 s =  + 2q +F metal Eg  8-9 eV Ei
qϕF
Ef
Ev
kT  N A  p-type
F = ln  semiconductor
q  ni 
Ev
Oxide

Φm = Φs i.e. Φms = 0
Uniform silicon doping Ec
Ei
Ef Ef
metal Ev

Flat-Band condition occurs at VG = 0

5
 When an ideal MOS capacitor is biased
When VG < 0
- + E
VG = Vox + s - +
VG<0 - + P - silicon
Vox  Oxide Voltage - + hole
- + flow
ϕs  Surface potential
ϕs
➢ In case of a negative gate voltage is Vox
applied (-VG) (Accumulation) negative
Q
Qm − Qs
VG = Vox +  s = + s = + s
C ox C ox
Qp=Qacc
x
Qs  Total charge induced in the Qm 0
silicon per unit area Qs = -Qm

➢ The capacitance of the MOS structure in

Accumulation is that of a parallel-plate  ox
capacitor between the metal gate and the C= = C ox F/cm-2
t ox
Accumulation layer. 6
 - +
E
Qm − Qs VG<0 - +
VG = Vox +  s = + s = + s - +
C ox C ox
Metal Oxide P-type silicon
ϕs  Surface potential
Qs  Total charge induced in the
silicon per unit area

Efm Ec
Surface electron and hole densities are:
qVG < 0 - qϕs Ei

ns = ni e q (  s −  F ) KT = no e q  s KT
Ef
qϕs<0
Ev

ps = ni e q (  F −  s ) KT = po e q ( −  s KT )

ϕs < 0 Accumulation of holes

Qacc
x
➢ ϕs is very small (even for large applied Qm 0
negative gate voltage values) Qs = -Qm

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8
 Negative
When VG > 0 fixed charge
+ - --
VG = Vox + s +
+ - --
+
+ E - --
Vox  Oxide Voltage VG >0 + - - - P - silicon
+
+ - - -
+
- - - hole
ϕs  Surface potential
+
+
+
- - - flow
ϕs
Vox
➢ In case of a small positive gate voltage
positive
is applied (+VG) (Depletion) Q

Qm − Qs
VG = Vox +  s = + s = + s Qd
C ox C ox Qm x
0
Qs  Total charge induced in the
silicon per unit area Qs = Qd = -Qm

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 − Qs
VG = Vox +  s = + s
Metal Oxide P-type silicon
C ox

ϕs  Surface potential
Qs  Total charge induced in the Ec
silicon per unit area
qϕs qϕF Ei
Ef
Surface electron and hole densities are: qVG > 0 qϕs>0
Ev
Efm

ns = ni e q (  s −  F ) KT = no e q  s KT

ps = ni e q (  F −  s ) KT = po e q ( −  s KT ) Qs = Qd = -Qm

x
Qm 0
ϕs < 0 Accumulation of holes
Qd
ϕs = 0 Flat-band condition
ϕF > ϕS > 0 Depletion of holes

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 − Qs Metal Oxide P-type silicon
VG = Vox +  s = + s
C ox
ϕs  Surface potential
Qs  Total charge induced in the Ec
silicon per unit area
qϕs qϕF Ei
Ef
qVG > 0 qϕs>0
Surface electron and hole densities are: Efm
Ev

ns = ni e q (  s −  F ) KT = no e q  s KT

ps = ni e q (  F −  s ) KT = po e q ( −  s KT ) Qs = Qd = -Qm

x
ϕs < 0 Accumulation of holes Qm 0

ϕs = 0 Flat-band condition Qd

ϕF > ϕs > 0 Depletion of holes

ϕF = ϕs Midgap with ns=ps=ni

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12
 For ϕ s ≤ ϕF

➢ If a small positive bias is applied to the gate, holes near the silicon surface
are repelled by the gate. Because the acceptor doping atoms cannot move
in the silicon lattice, a negative charge appears underneath the gate oxide.

➢ The gate charge is a surface charge, but the charge in the silicon is not. It
is a depletion charge.

➢ Starting with Poisson’s equation, one can get:

qN A 2
s = xd
2 si

2 si s
xd =
qN A

Qd = − qN A xd = − 2q si N A s
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 The total capacitance:

dQm dQ dQd
C= =− d =−
dVG dVG Q
d ( − d + s )
C ox
dQd / d s 1
=− =
Qd 1 1
d( − +  s ) / d s +
C ox C ox C d
dQd  si
Where C d = − =
d s xd

Plot Xd as a function of VG?

Plot the charge, the electric field and the potential distributions of the MOS structure?

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 Negative
When VG >> 0 fixed charge

In case of a larger positive gate voltage ++

++
-
- - -- ---
++ - - -- ---
is applied (++VG) (Inversion) ++ -
- -- ---
VG>0>>0
++
++
E -
-
- - - - -P - silicon
-
++
++ - - - --- -
There are two sources of electrons that
++
++
-
- - - --- -
++ -
-
- - --- -
can change the charge density of the ++

inversion region ϕs>0

Vox
1. The minority carrier of p-type
substrate
2. The thermal generation of electron -
hole pairs within the depletion region Q
Mobile
Charge
Qm − Qs Qd
VG = Vox +  s = + s = + s Qm
C ox C ox x
0

Qs  Total charge induced in the silicon Qs = -Qm

per unit area (Qn+ Qd)
Qn
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 Metal Oxide P-type silicon
Electric field
Vox direction
Ec

Ei
qϕF
qϕs
ns = ni e q (  s −  F ) KT = no e q  s KT Ef
(ϕs>0) Ev
Neutral region
ps = ni e q (  F −  s ) KT = po e q ( −  s KT )
VG > 0
Deple-
Ef tion
region

ϕs < 0 Accumulation of holes

Qm Inversion region
ϕs = 0 Flat-band condition
ϕF > ϕs > 0 Depletion of holes Qs = Qn + Qd = -Qm

ϕF = ϕs Midgap with ns=ps=ni 0 x

ϕs > ϕF Inversion Qd
Qn

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➢ Once again, if we apply the “Depletion Region Approximation”
(neglect all charges but those due to ionized dopants) :

Qd = −qN A xd

qN A
E( x ) = ( xd − x )
 si

qN A
( x ) = ( xd − x )2
2 si

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➢ The carrier concentartion as a function of the surface potential in the MOS
structure.

ϕF 2ϕF ϕs

➢ As in the case of accumulation, the capacitance of the MOS structure is

once again equal to Cox
➢ When the gate voltage is increased beyond inversion layer formation, the
surface potential increases only very slightly and for all practical purposes
one can assume that when an inversion layer is present, regardless of the
gate voltage. the depth of the depletion region is given by:
4 siF
xd max =
qN A 18
 Charge in MOS Structure p-type silicon
Ec

d 2
dx 2
= −
dE − q
=
dx  si
p(x ) − n( x ) + N +
D − N −
A  qϕF
Ei
qϕs qϕ
Ef
2 KTN A  − q / KT q  Ev
E( x ) =    e + − 1
 si  KT  Neutral region
Depletion
12 region
ni2  q / KT q  Inversion region
+ 2 e − − 1 
NA  KT  
x
At x = 0 ϕ = ϕs and E = Es Qd
Qn
Qs = Qn + Qd= -Qm
Qs=εsi Es Gauss’s Law
12
 − q s / KT q s  ni  q s / KT q s 
2
Qs =  2 si KTN A  e + − 1+ 2  e − − 1
 KT  N A  KT 
Qs is the silicon charge per unit area − Qs
VG = Vox +  s = + s
KT si C ox
2
= LD LD is the Debye length
q NA
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 NA
ϕs

ϕs

ns> NA
ϕF
ps> NA
ϕs
ns< NA ns< NA
Ps< NA ns> ps

ϕF

After Sze 1981 ϕs 20

 1
Variation of ϕs with VG
tox = 5.5 nm
0.8
 q  2ϕF
Qs = 2 si KTN A  e − q s / KT + s − 1
 KT  0.6

ϕs (V)
12 tox = 25 nm
n  q s / KT q s 
2
+ i
e − − 1  0.4
N 2
A KT  
0.2 NA = 4.5x1015
− Qs
VG = Vox +  s = + s 0
C ox 0 0.5 1 1.5 2 2.5
VG (V)

➢ ϕs increases with VG even in strong inversion.

➢ In ultra thin oxide thickness ϕs in strong inversion

can be 200 mV higher that 2ϕF.

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22
 MOS Capacitance (C-V Curve)

(Quasi-static)
Low frequency
ϕs

ϕs= ϕF ϕs= 2ϕF

High
frequency

Deep depletion

Dielectric mode

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 MOS Capacitance:
Accumulation Depletion Inversion
High Low
frequency frequency

Cox Cox Cox Cox

Csi  Cacc
Cd Cd Cinv Cd Cinv

1 1 1 1 1 1
C = Cox = + = + C = Cox
C C ox Cd C C ox Cd

Flat Band Capacitance (CFB):

1 1 1
= +
At ϕs=0, C= CFB C FB C ox  si LD

Where LD is the Debye length. LD is the effective dynamic depletion region thickness.
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Case a:

✓ Let us first consider the case of a low-frequency ac signal (quasi-static curve

in Figure). When the gate voltage is negative an accumulation layer is present.

✓ As the gate voltage varies a corresponding variation of the accumulation

charge occurs, and the capacitance of the structure is equal to Cox

✓ When the gate voltage is increased the silicon surface becomes depleted, and
the variations of gate voltage induce variations of the depletion charge.

✓ The value of the capacitance is then given by the series combination of the
gate and depletion region capacitances.

✓ As the gate voltage is further increased an inversion layer is formed and

variations of gate voltage give rise to variations of inversion charge and thus the
measure capacitance is again equal to Cox

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Case b:

✓ If we repeat the same measurement using a higher frequency for the small
ac signal (1 MHz, typically), thermal generation cannot create minority
carriers fast enough to support a variation of charge in the inversion layer.

✓ Therefore, while the portions of the curve in accumulation and depletion are
identical to the previous experiment, the inversion part of the curve is not.

✓ The variation of charge due to the variation of the gate voltage is no longer
supported by the inversion charge, but by a variation of the depletion
charge.

✓ The depth of the depletion region is equal to xdmax ± ∆xd

where ∆xd is a small modulation of the depletion depth due to the
application of the small ac gate bias.

✓ In this case the capacitance of the structure is given by the series

association of the gate capacitance, Cox and the depletion capacitance,
εsi/xdmax

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Case c:

✓ If a fast gate voltage ramp is used there is no time for generation of

minority carriers (electrons).

✓ Majority carriers are readily available to form an accumulation layer, so

that the accumulation part of the curve remains unchanged.

✓ When the gate voltage is ramped up, a depletion layer is formed, but no
inversion layer can be formed.

✓ Therefore, only a depletion charge can respond to the gate voltage

variation, and the depletion depth can be larger than xdmax .Such
operation is called the deep-depletion regime, and the surface potential is
not clamped at 2ϕF

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Case d:

✓ If a very high-frequency ac signal is used, even majority carriers may not

have time to react to the gate voltage variation.

✓ Frequencies of 1 GHz or higher must be used for this effect to appear. The
higher the doping concentration, the higher the frequency.

✓ In this case the whole semiconductor sample behaves as a dielectric

(dielectric mode of operation in Figure).

✓ Such that the capacitance of the structure is given by the series

association of Cox and εsi/dsi where dsi is the thickness of the silicon wafer.

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 Real MOS Capacitor
➢ Work Function Difference

qΦs Ec
Efm
Ec Ei
qΦm qVG < 0
Ei Ef
Ef Ev
metal Ev

Equilibrium Flat-Band
VG = 0 VG = VFB = ms

➢ Charges in the Oxide and at Interface

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 Oxide Charges / Interface Traps

Charge Type Location Cause Effect on Device

Qit(C/cm2) Interface SiO2/Si Dangling Junction Leakage
Trapped interface bonds, Hot current, Noise,
Charge electron Threshold Voltage
damage, Shift
contaminants
Qf(C/cm2) Fixed Charge Close to Si+ Threshold Voltage
SiO2/Si Shift
interface
Qot(C/cm2) Oxide Trapped In SiO2 Trapped Threshold Voltage
Charge electrons and Shift
holes
Qm(C/cm2) Mobile Charge In SiO2 Na, K, Li Threshold Voltage
Shift
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Real MOS Capacitor
➢ Work Function Difference

Efm Ec
qΦs Ei
qVG
Ec Ef
qΦm
Ei Ev
Ef
metal Ev
Flat-Band
Equilibrium VG = VFB = Φms
VG = 0

✓ Real surfaces have workfunction differences

✓ The difference is always negative and is most
negative for heavily p-type Si.
➢ Charges in the Oxide and at Interface

For simplicity the various oxide and interface can be included as a positive
equivalent charge (Qoi) at the interface.

Q Qoi
V FB = − oi
C ox

In real MOS Cap.

Q oi
V FB =  ms −
C ox
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 Threshold Voltage
➢ Threshold voltage presents the minimum gate voltage required to achieve
the onset of strong inversion

VG → Vth ϕs → 2ϕF
Qs  Qd Qd = − 2  si q N A  S
Qd
V G = V FB + S −
QS V th = V FB + 2 F −
C ox C ox

The threshold voltage must be strong enough to achieve flatband, accommodate

the charge in the depletion region, and induce the inverted region.

Vth = VFB + 2 F +  2 F

2  si q N A
 =  Body effect cofficient
C ox
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 Sheet of
Polysilicon Gate Effect gate charge

Case 1 : Polysilicon is heavily doped

 1020 cm-3 (degenerate)

Fermi level of the gate electrode is

pegged at either one of the two band
edges.
Φms
Eg −
V FB =  ms =− F
2q qϕF
qΦms
QS
V G V FB  S
= + −
C ox

1 1 1
 +
C C ox C si

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 Case 2 : Polysilicon is NOT heavily
doped

➢ Thin space charge region is formed in

polysilicon (poly gate depletion effect)
➢ Additional capacitance in series with the
oxide capacitance
➢ Reduction in inversion layer charge density

V G = V FB +  S +  P + V ox
1 1 1 1
= + +
C CP C ox C si
qϕs
The effective gate voltage is VG
qϕp

V G _ eff = V G −  P

35
Low-frequency C- V curves of a polysilicon gate
MOS Capacitor

Effect of polysilicon
gate inversion
N+ polysilicon
gate on p-type Effect of polysilicon
MOS capacitor gate depletion

36
Backup

37
 Qs vs. ϕs
Accumulation ϕs < 0

Q s = Q acc  2  si N A KT exp( − q  S 2 KT )

Depletion 0 < ϕs < ϕF

Q s = Qd  − 2  si qN A  S

Weak inversion ϕF < ϕs < 2 ϕF

2  si N A
Qs  − KT exp( q(  S − 2 F ) KT ) |Qn | < |Qd |
2 q S

Strong inversion ϕs > 2 ϕF

Q s  − 2  si N A KT exp( q(  S − 2 F ) / 2 KT ) |Qn | > |Qd |

38
 Oxide Charges

1. Interface Trapped Charge

➢ Can be either positive or negative charge
➢ Due to
✓Structural Defects
✓Oxidation induced Defects
✓Metallic Impurities
✓Broken bonds
➢ Can be improved by a low temperature (~ 450 oC) anneal.

2. Fixed Oxide Charge

➢ Generally positive charge and is related to oxidation conditions

✓Increases with decreasing oxidation temperature
✓Can be reduced to a fixed( minimum value) by anneal in inert gases
✓Can be affected by rapid cooling.
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3. Oxide Trapped Charge

➢ Can be either positive or negative charge.

➢ Due to electrons or holes trapped in the oxide:
✓ Tunnel currents
✓ Breakdown

4. Mobile Charge
➢ Generally positive
➢ Due to contaminants (Na, K, Li) in the oxide:
✓ Gate voltage slowly drives the charge across the oxide changing the
threshold voltage and capacitance characteristics
✓ Can lead to hysteresis in the CV curve
✓ Can lead to time dependent threshold voltages

40