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Indian Institute of Space Science and Technology

Course : Micro/Nanofabrication Technologies

2nd Semester M-Tech in VLSI and Microsystems

Lecture :CMOS Device Fundamentals

Course Instructor
Seena.V.
E-mail : seena.v@iist.ac.in / seenapradeep@gmail.com
Office : R-107, Avionics Block
Ext: 579

VLSI/CMOS Device
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Twin-well CMOS

Figures from Semiconductor Physics and Devices by Donald A. Neamen 2/1/2023

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MOSFET: A field Effect Device

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1935 British patent, Oskar Heil

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MOSFETs
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MOSFETs
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VG > VT & VD < VG -VT

VG > VT & VD = VG -VT

VG > VT & VD >VG -VT

Figures from Semiconductor Physics and Devices by Donald A. Neamen 2/1/2023

MOS Capacitor
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Heart of MOSFET

Figures from Semiconductor Physics and Devices by Donald A. Neamen 2/1/2023

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MOS Capacitor
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Ideal MOS Capacitor

M Metal work function

qF
s Semiconductor work function
 Electron affinity

Figures from Semiconductor Physics and Devices by Donald A. Neamen 2/1/2023

MOS Capacitor
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qF

Figures from Semiconductor Physics and Devices by Donald A. Neamen 2/1/2023

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MOS Capacitor
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Figures from Semiconductor Physics and Devices by Donald A. Neamen 2/1/2023

MOS Capacitor
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Figures from Semiconductor Physics and Devices by Donald A. Neamen 2/1/2023

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MOS Capacitor
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q s

Figures from Semiconductor Physics and Devices by Donald A. Neamen 2/1/2023

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MOS Capacitor
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The surface potential: This is the total amount of

band bending at the surface of the q s
semiconductor measured with respect to the
bulk.

Condition for inversion is that the surface is as n-type as the bulk is p-type, that is , ns = po.

Figures from Semiconductor Physics and Devices by Donald A. Neamen 2/1/2023

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MOS Capacitor
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po is the equilibrium number of holes in the p-type semi. cond.

For a typical value of Na = 10E16 cm –3 ,and ni = 1.5 X 10E10 cm –3

the bulk potential = 0.34 V at room temperature.

A common definition of the onset of inversion is that the

surface is as n-type as the bulk is p-type, that is , ns = po.

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MOS Capacitor
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MOS Capacitor
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MOS Capacitor
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Threshold Voltage Determination : Depletion Approximation
Band ending, can be easily found by solving Poisson's equation in Region A
Assumptions:
• Reg A: No mobile carriers ➔ space charge density is
given by
• Reg B: No space charge
• There is a sharp transition between the two regions
at a point x = xd called the depletion width.

➔The band-bending in the semiconductor is parabolic.

(at x = 0)

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MOS Capacitor
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Threshold Voltage Determination : Depletion Approximation

In depletion, the total charge in the semiconductor QS is just the depletion charge QD

VG
The value of VG required to produce the
surface potential ? Vox

Using Gauss' law, the electric field emanating

from the gate into the oxide is
(The charge on the gate QG is equal to and opposite that of QD)

(oxide capacitance per unit area)

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MOS Capacitor
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Threshold Voltage Determination : Depletion Approximation

Onset of inversion

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MOS Capacitor
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Threshold Voltage Determination : Depletion Approximation

For VG > VT , charge in the inversion layer QI cannot be ignored

Beyond threshold , the inversion layer charge(QI) increases linearly with VG , and the
device behaves like a parallel plate capacitor of value Cox per unit area

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MOS Capacitor
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Capacitance-Voltage (CV) Plot of the Ideal MOS Capacitor
➢ It is a plot of small signal capacitance C as a function of the gate voltage VG.

➢ It is an important plot because it gives a great deal of information about the MOS
structure, and makes the MOS capacitor a useful diagnostic tool.

The small-signal capacitance for the MOS capacitor

➔semiconductor capacitance CS.

This is the differential change in the semiconductor
charge with respect to a change in the surfacepotential
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MOS Capacitor
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Capacitance-Voltage (CV) Plot of the Ideal MOS Capacitor

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MOS Capacitor
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Silicon Dioxide as Dielectric for MOS

➢ Forms an almost ideal interface with silicon

➔produce very few defects,

➢ It has a large bandgap (9.1eV)

➔Very few intrinsic carriers

➢ Large barriers for both electrons and holes

in silicon (as well as the gate)

➔the carriers can be effectively contained

in the silicon, and do not get injected
easily into the insulator.

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MOS Capacitor
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Work Function Difference
THE NON-IDEAL MOS CAPACITOR

p-Si

(a) Al
n Al-SiO2-Si MOS capacitor
Aluminum has

n Al-SiO2-Si MOS capacitor

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MOS Capacitor
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Work Function Difference
THE NON-IDEAL MOS CAPACITOR

In equilibrium, the semiconductor is in depletion (or

perhaps inversion depending on the oxide thickness) and
not at flat bands

To produce flat bands for the Al-gate MOS capacitor, we now need
to pull up the fermi level in the gate with respect to the silicon, by
applying a (negative) gate voltage.
Kirchhoff’s equation now is given by

The flat-band condition is produced when the gate voltage

The gate voltage required to produce flat bands is called the flat-band voltage VFB,
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MOS Capacitor
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Work Function Difference
THE NON-IDEAL MOS CAPACITOR

For Na = 1x 1016 cm-3 and tox = 25 nm, the

threshold voltage =0.15 V instead of 1.05 V for
the ideal MOS device.

Vth is too low, and therefore a threshold adjust

implant has to be done. This implant increases the
doping near the surface, which increases VT.

Band diagram under flat-bands of a MOS

capacitor with work function difference =-0.9 V
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MOS Capacitor
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Work Function Difference
THE NON-IDEAL MOS CAPACITOR

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MOS Capacitor
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Effect of Oxide Charge
THE NON-IDEAL MOS CAPACITOR

• When SiO2 is thermally grown on silicon by oxidation at high temperatures, there is

inevitably produced a positive charge close to the Si/SiO2 interface. This is called the
fixed oxide charge Qf.
• It is “fixed” in the sense that changing the voltage on the gate does not change the
amount of this charge.
• Its physical origin : Probably a trivalently bonded silicon which has lost its extra
electron, and thereby gained its positive charge.
• Location : It is probably located within 1-2 nm of the Si/SiO2 interface.
• Thermal oxidation of silicon under controlled conditions (which often includes a post-
oxidation inert anneal) reduces the value of Qf to less than 5 x 1010 charges/cm2
• The energy location in the SiO2 band gap of the defect producing Qf is probably high
above the silicon band edge➔ Qf will be permanently positively charged.

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MOS Capacitor
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Effect of Oxide Charge
THE NON-IDEAL MOS CAPACITOR
The characteristic of defects which contribute to the
oxide charge is that they cannot exchange charge
(undernormal operating conditions) with the silicon

Assume presence of positive sheet of charge Qox per

cm2 exactly at the Si/SiO2 interface

This positive charge will induce

negative in the semiconductor,
causing the it to go into depletion
or inversion, even at (VG = 0V).
We need to apply a negative
voltage to the gate in order to
neutralize the effect of +Qox ,
and produce flat bands

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Effect of Oxide Charge
THE NON-IDEAL MOS CAPACITOR

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MOS Capacitor
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Effect of Oxide Charge
THE NON-IDEAL MOS CAPACITOR

Case 2: The charge sheet Qox per cm2 is present not at the interface, but at x = x1 (i.e. at x1
from the Si/SiO2 interface),

➔As Qox goes further away from the interface, the value
VFB needed to counteract its effect reduces

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Effect of Oxide Charge
THE NON-IDEAL MOS CAPACITOR

Case 3: The charge sheet Qox per cm2 is present not at the interface, but at x = x1 (i.e. at x1
from the Si/SiO2 interface),

➔As Qox goes further away from the interface, the value
VFB needed to counteract its effect reduces

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MOS Capacitor
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Effect of Oxide Charge
THE NON-IDEAL MOS CAPACITOR

Case 3: Instead of a sheet of charge Qox , an arbitrarily distributed volume charge density
(per cm3 )

➔As Qox goes further away from the interface, the value
VFB needed to counteract its effect reduces

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Effect of Interface States
THE NON-IDEAL MOS CAPACITOR
• An ideal semiconductor abruptly terminated at a surface will have a large density
of localized energy states in the forbidden energy region.
• These can be attributed to dangling bonds
• Such a large density of states would make operation of a MOS device impossible.
Indeed, it was exactly the presence of these unwanted states which hindered the
development of working field-effect transistors in the early years
• The hypothesis of the “dangling bond” origin of interface states is also validated
by the variation of the number of the interface states with the crystal orientation of
the silicon surface.
• Nit is always larger (for identical processing conditions) for the <111> orientation
of Si compared to the <100> orientation, since the former has more bonds (per
cm2) at the surface

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MOS Capacitor
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Effect of Interface States THE NON-IDEAL MOS CAPACITOR
• The interface states, or interface traps, are spread throughout the forbidden energy
region between Ec and Ev of silicon.
• ➔ energy density of interface states, Dit, is the number of interface states per
energy interval per unit area.
• Unlike the fixed charge Qf and the oxide electron and hole traps, the interface
states can readily exchange charge with the semiconductor. As the MOS device
goes from accumulation to inversion, the
• interface states can be filled with holes or electrons. This produces a varying
charge at the interface.
• The charge status of the interface states depends on whether they are donor-like or
acceptor-like.
• Donor-like :Positively charged when empty of an electron and neutral when filled
• Acceptor-like:Neutral when empty of an electron
and negatively charged when filled with an electron

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Effect of Interface States
THE NON-IDEAL MOS CAPACITOR
(a) In accumulation

(c) In inversion

(b) At mid-gap

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MOS Capacitor
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Effect of Interface States
THE NON-IDEAL MOS CAPACITOR

Band diagram in silicon in the presence of Unioform Dit

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Effect of Interface States
THE NON-IDEAL MOS CAPACITOR

Interface-State Capacitance and Equivalent Circuit

• Since the interface states can get filled and unfilled as the gate voltage vary, they introduce
an interface trap capacitance Cit.
• In the presence of interface states, the gate charge QG is now balanced by the
semiconductor charge QS +interface charge Qit:

This shows that for any given change in , we need a larger dVG with interface states
present than without. This results in the stretchout.

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MOS Capacitor
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Effect of Interface States
THE NON-IDEAL MOS CAPACITOR

Interface-State Capacitance and Equivalent Circuit

We can find the quasistatic (or low-frequency) capacitance of the MOS capacitor including
interface states by evaluating C = (dQG/dVG)

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Effect of Interface States
THE NON-IDEAL MOS CAPACITOR

Interface-State Capacitance and Equivalent Circuit

The interface states do not get filled and emptied arbitrarily quickly. There is a time
constant associated with the capture/emission process.

➔How slowly or rapidly the interface states can respond.

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