ICC2：Design Planning（02）Shaping Placement

blog.csdn.net/m0_61544122/article/details/127664536

The content of this part is as follows:

1) Split Constraints: Split UPF and SDC.

2) Create Placement Abstracts: Create the abstract view* of the block.

3) - 4) Shaping Block and Voltage Areas+Analysis and Incremental Shaping: Adjust the
shape of the block and power domain.

5) Placement: Place macros和standard cells。

* abstract view can be understood as a summary view, retaining the std cell of the block
interface, including the first and last registers of in2reg and reg2out; retaining all hard
macros; saving time when doing top-level design.

1.Split Constraints
If this step is a bottom-up design, then split constraints can be performed after the
commit block. If it is a top-down design, this step needs to be performed after reading upf
and sdc .

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Split constraints are used to split the sdc constraints and upf of the top level and block
level when the partition block is used, and do not split any content related to physical
information. After splitting, you can get:

1) The timing constraints and upf of the block level can be used for the physical realization
of the block level.

2) top level timing constraints and upf, where the timing constraints only retain the
timing constraints of the top level part and the top-to-block interface, and upf only retains
the top level part.

1.1 Split Constraints Flow

The process of split constraints is as follows:

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1) read_verilog

Here, if the verilog netlist data information of the outline is used, it is not enough, and the
complete netlist needs to be used.

read_verilog -top top_cell_name "top_level.v block_level.v"

or

read_verilog_outline -top top_cell_name "top_level.v block_level.v"

commit_block

expand_outline

2) Load & Commit UPF

To read upf, use the load_upf command. If there is upf in the block level, it can also be
read in through load_upf -scope.

load_upf top_level.upf

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load_upf incremental.upf (as a supplement)

load_upf -scope block_cell_name block_level.upf

... ...

commit_upf

3）Timing Setup & SDC Import

The MCMM environment needs to be set before split_constraints, namely create_mode,

create_corner, create_scenario, set_parasitic_parameters, set_voltage, set_temperature,
set_process, set_scenario_status & read_sdc

Among them, set_voltage should define all the supply_nets in UPF (if VDD and
block/VDD are connected together, then only one definition is enough), after setting up
the MCMM environment, you can use report_pvt to report which supply nets do not
define voltage .

4）Split the UPF and SDC

Split constraints need to specify the corresponding block inst name, use the command
set_budget_options.

set_budget_options -reset

set_budget_options –add_blocks "inst_A inst_B1 inst_B2 inst_C"

split_constraints

It should be noted that if you want to keep the constraints inside a block, you can use the
following command:

split_constraints -hier_abstract_subblocks block_name

or

split_constraints -design_subblocks module_name

5）split_constraints Output

The default output folder name of split constraints is ./split, and the directory structure is
as follows:

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Split constraints will generate all modes and corners by default. Specify corner or mode to
add -corner or -mode when split_constraints.

Example mapfile:

BLENDER SDC BLENDER/top.tcl

BLENDER CLKNET BLENDER/clocknets.tcl

BLENDER UPF BLENDER/top.upf

PCI_TOP SDC PCI_TOP/top.tcl

PCI_TOP CLKNET PCI_TOP/clocknets.tcl

PCI_TOP UPF PCI_TOP/top.upf

Example clocknets.tcl:

set_attribute -quiet [get_net {net_pclk}] -name net_type -value clock

set_attribute -quiet [get_net {I_ORCA_TOP/pclk}] -name net_type -value clock

set_attribute -quiet [get_net {I_ORCA_TOP/I_CLKGEN/pclk_in}] -name net_type -

value clock

set_attribute -quiet [get_net {net_sys_2x_clk}] -name net_type -value clock

This file is used to identify clock nets because there is no timing information in the
place_pins stage. place_pins needs to distinguish between clock and signal nets, because
by default, the feedthrough of clock nets is disabled.

6）UPF&Split Constraints

All UPF commands can be split by split constraints, including:

Domains

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Supply sets & associations

Supply_nets

Strategies (levelshifter, switch, isolation) Power States and Power State Tables

Enable line / control signal stitching (connect_logic_net) etc…

An example of SDC split constraints is as follows:

Example 1

Example 2

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2.Create Placement Abstract
The abstract view can be understood as a summary view, retaining the std cell of the block
interface, including the first and last registers of in2reg and reg2out; retaining all hard
macros; saving time when doing top-level design.

2.1 Design vs.Abstract View

create_abstract will retain the design view of top level and intermediate level by default,
and only create abstract view for leaf level.

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The intermediate level connects the upper and lower level blocks. The abstract view will
have more logic than the abstract view generated by the general leaf level block, but it is
better to keep the design view.

To make the intermediate level (intermediate level) also apply abstract view you can use
the command:

set_app_options -name abstract.allow_all_level_abstract -value true

2.2 Ready the Design for Shaping

In the previous split constraints, it is not enough to split the constraints and use the
outline design of UPF, so expand_outline needs to be executed before split constraints.
Although the outline design can be used in the create_abstract step, it is recommended to
use the complete netlist.

# expand outline

open_lib top_lib

open_block top.outline

expand_outline

set_constraint_mapping_file ./split/mapfile

create_abstract –placement -all_blocks

2.3 Abstract View Handing

1) After the abstract view of the block is created, the corresponding design is the locked
attribute, that is, the read-only mode.

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2) When the design is opened, the modification of its abstract view will be merged into the
design view.

3) If you have modified the design view, you need to create abstract again.

3.Shape Block and Voltage Area

This step needs to create a voltage area, and adjust the shape of the voltage area and block
and place them in a suitable position.

3.1 Pre Shaping Block

1) check_design, you need to check the block utilization, core area and block boundary
before shape block. Use the command:

check_design -check dp_pre_block_shaping

2) set_ignored_layer, this step needs to set the winding resources. Use the command:

set_ignored_layer -min_routing_layer M2

set_ignored_layer _max_routing_layer M8

report_ignored_layer

3) set_shape_options, set channel size (between blocks, block and top level macro, block
and core boundary), set voltage area guard band, and set whether to put top level cells
together. Use the command:

set_shaping_options  \

     -min_channel_size 10 \ #default 0

     -guard_band_size 6 \   #default 0

     -keep_top_level_together true #default true

Here, if you don't like the voltage area automatically created by shape_blocks, the user
can also create the voltage area before the shape block.

create_voltage_area -power_domains PD_xx -is_fixed -region {... ...} -guard_band ...

3.2 Configuring Shaping

The hard and soft constraints of block and voltage area can be written into the config file,
using the command, "shape_block -constraint_file <filename> ", the example is as
follows:

Example 1. global & block constraints

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Utilization, shape constraints.

Example 2. channels

block and block, block and core boundary.

3.3 PG Strategy
Set the pg mesh scheme for the block.

set_pg_strategy mesh -core -pattern  {{name: my_pattern} {nets: VDD VSS}} 

shape_blocks  -pg_strategy mesh

compile_pg -strategies mesh

-core, the solution is applied to the entire core area, and -block can also be used. After
compile_pg, the pg mesh is routed on the entire core area or on the block, and the tool
will avoid the boundary of the block.

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3.4 keepout margin for blocks

Setting keepout margin for block is the same as setting method for inst.

create_keepout_margin -outer {... ...}

3.5 MIB Placement Considerations

In the floorplan stage of the chip level, the movement and flipping of MIB (multiple
instances) blocks can only be along the X-axis or Y-axis (keep the routing direction
consistent and reduce congestion), so the direction of the block is only R0, MX, R180 and
MY.

To allow the MIB place to move to a different location or change direction in the future,
you need to ensure that the following settings are consistent:

1) site array (avoid power rail short)

2) power grid

3) route track (for signal pin)

If the block moves or changes direction and cannot keep the above settings consistent,
then the site and power grid will fail when push down. As shown below.

Therefore, adjusting the MIB block requires the following two steps:

1) create a block grid

    Creating a block grid can be based on site row or pg grid.

2) Specify the block grid and snap point for the block

     Use the snap point to snap the block to the block grid. The snap point must be on the
block grid, and the default is the lower left corner of the block.

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The snap point defaults to the lower left corner of the block (0, 0). To change the snap
point, use set_block_grid_references -design block_name -grid grid_name -snap_point
"x y"

4.Analysis and Incremental Shaping

4.1 Path Analyzer Flylines

View->Flylines->Path Analyzer Flylines

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Through From/To, you can see the connection relationship related to the block.

4.2 Timing Ruler

The timing ruler does not display the length, but displays the delay value. The user can
customize the layer, buffer type, NDR, etc., and the user controls the distance from point
to point, and the tool will display the delay.

4.3 Incremental Shaping

If the first shape block is not satisfied, you can choose incremental shaping

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shape_blocks -incremental congestion_driven/target_utilization_driven

target_utilization_driven shapes the block according to the utilization rate of each block
target, while congestion driven needs to place standard cell and global route first and then
shape the block to improve channel congestion.

set_shaping_options -utilization_slack  0.1 -add_channel_blockages

none/partial/soft/hard

Give the target utilization of the block a certain margin, so that the shape block of incr will
not overlap.

4.4 Push Down Site Array

After the shape block, you need to push down the top routing track to each block.

4.5 Block Origin

Set the origin position of the block. By default, the lower left corner is set to the origin (0,
0). If the right or upper side of the block is changed when the block is resized, the origin
does not change. If the left or lower side is changed, the origin of the block changes. If you

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want to reset the origin, you can use move_block_origin.

Examples are as follows:

Original block on the left:

icc2_shell> set origin [get_attribute [get_blocks -hier -filter name==$block]

boundary_bounding_box.ll]

0.0000 0.0000

After sizing (on the right):

icc2_shell> set origin [get_attribute [get_blocks -hier -filter name==$block]

boundary_bounding_box.ll]

-23.1950 -37.3770

To move the origin:

move_block_origin -to $origin [get_blocks -hier -filter name==$block]

5.Placement

5.1 Pre Macro Placement Check

check_design -check dp_pre_macro_placement 

Check whether the block shape has overlap, check whether the block or voltage area
exceeds the parent block boundary, check placement constraints, and check the utilization
of block/voltage area/bound.

5.2 Pin Constraints Aware Placement

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Load pin constraints before place, you can specify which side the pin is placed on, offset,
level, etc.

set_block_pin_constraints -allow_feedthrough true -allowed_layers {MX ... ...}

5.3 Keepout Margin

The hard macro needs to set the keepout margin before the place, which is usually set
with the create_keepout_margin command, and the tool also supports the command to
automatically set the keepout margin according to the pin count.

plan.place.default_keepout true(default)

plan.macro.min_macro_keepout 0.5um; # here you need to set the length unit

5.4 Macro Constraints

If the macro does not define the available direction, or the user needs to define it
specially, you can do the following settings:

set_macro_constraints -allow_orientations {R0 ... ...} {hard_macro_list}

Similarly, the user can also set the

approximate position of the macro, and
the tool place hard macro will place the
hard macro around the left side of the
setting.

set_macro_constraints -
preferred_location  {x y} {hard macro list}

Preferred Macro Location Control

5.6 Macro Only Placement

create placement supports only macro cell placement.

set_app_options -name plan.macro.macro_place_only -value true

create_placement -floorplan

Macro Only Placement

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5.7 Automatic Placement Blockage

By default, the create placement tool will generate blockage in the channel, and users can
also execute the command to add blockage separately.

derive_placement_blockages:

Automatic Placement Blockage

5.8 Analyzing Congestion

Analyzing Global Routing Congestion

It is best to analyze congestion based on global route.

route_global -floorplan true -congestion_map_only true -virtual_flat

top_and_interface_routing_only/all_routing 

1) Analyze channel congestion

Need to create channel congestion map first

create_channel_congestion_map -channel_width_threshold 20

2) Analyze global route congestion

Just wire the top and block interface.

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route_global -floorplan true -congestion_map_only true -virtual_flat
top_and_interface_routing_only

5.9 Create Bound to Constraint Macro Placement

The user can set the bound constraint placement, so that the specified cell list should be
placed together as much as possible.

create_bound -name GB {macro list}

You can add an option -effort low/high to control the tightness

5.10 Placement

Put the standard cell and non-fixed hard macro place on it.

create_placement -floorplan

1) incremental placement

After analyzing congestion, if you need to do incremental placement, you can use:

create_placement -floorplan -incremental -congestion

Among them, there are three modes of congestion driven placement, one is to reduce only
macro-related congestion, the other is to only reduce standard cell-related, and the last is
a combination of both.

set_app_options -name plan.place.congestion_driven_mode -value macro/std_cell/both

Corresponding to congestion driven is timing driven

set_app_options -name plan.place.timing_driven_mode -value macro

create_placement -floorplan -timing_driven

2) top level only placement

By default, create placement places the entire chip. If you want to target the top level, you
can use the following command:

set_editability -from_level 1 -value false

create_placement  

5.11 Analyzing and Assessing Results

Use report_placement to analyze the placement results, and errors can be opened using
the error browsr of the GUI interface.

Report Placement

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