3/1/22, 2:37 PM LEF, DEF & LIB – signoffsemiconductors

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LEF, DEF & LIB Hom

November 2, 2017
By signoff-scribe

LEF, DEF & LIB

 

Author: Ashish Kumar Sharma, Physical Design Engineer, Signoff Semiconductors

Library Exchange Format (LEF)

The LEF file is the abstract view of cells. It only gives the idea about PR boundary, pin position and metal layer information of
information about the cell, DEF (Design Exchange Format) file is required. In this 3 sections are defined, i.e. technology, site
part layers, design rules, via definitions and metal capacitance are defined. In the site, site extension is defined and in the ma
cell description, dimension, layout of pins and blockages and capacitance are defined.

For every technology the layer and the via statements are different. So for the layer and via, the type of the layer (layer m
slice or overlap), width/pitch and spacing, direction, resistance, capacitance, and antenna factor are defined.

Unit Definition

UNITS

DATABASE MICRONS 1000 ;

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END UNITS

Values defined in file will be multiplied

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Manufacturing grid

MANUFACTURING GRID 0.1 ;

This is defined for the geometry alignment, once it is specified, then the cells are placed in location which is aligned to the m

Implant Layer definition

This syntax defines the Implant layer in the design. For each layer, name, space and width are defined. Space and width are
legal cell placement.

Masterslice or Overlap Layer definition

LAYER layerName

TYPE{MASTERSLICE| OVERLAP} ;

This defines the masterslice (non routing) or overlap layers in the design. Master slice layers are basically polysilicon la
MACROS are present on Polysilicon these layers are used.

VIA

for signal routers the VIA statement defines via’s. By default via is using three layers

1. cut layers.
2. Routing
3. Masterslice.

The routing and the master slice layers touch the cut layers.

Via Rule Generator

In order to generate the via arrays, via rule generator defines the formulas.VIARULE GENERATE statement can be used to def
is explicitly not defined in VIARULE statement.
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Same-Net Spacing

This rule determines the minimum

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SITE

Site specifies the region of the block like PAD and CORE, under this syntax, symmetry is also defined w.r.t. X, Y or R90 (Rotate by

Macro (Attributes of Macros are defined)

This syntax defines the detail about Macros like name, PAD detail, class size, location of endcap cells (like topright, bottom
obstruction detail.

Macro Pin Statement

Defines the pins for the Macros. For each macro, Pin statements are required (all I/O pins, VDD , VSS).

Following list of pins are required

Power and ground pins

Input and Output Pins, inout and netlist pins.
Must Join pins

MustJoin pin

This specifies the name of the pins to be connected together.

Macro Obstruction statement

The OBS defines the group of obstruction on macros, normally this blocks the routing but in case of obstruction on pin it allow

DEF (Design Exchange Format)

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The DEF file basically contains the placement information of macros , standard cells, I/O pins and other physical entities.
place and route tool and takes the physical design data from place and route tool in form of DEF. The logical design
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connectivity, grouping information, and physical constraints and the physical design data contains routing geometry dat
orientation. DEF is used as an input for various stages.Floorplan DEF is given at the import design stage to provide informatio
ports and block shape, SCANDEF is given at the import design stage for scan chain reordering which contains the connectiv
and it is also an input of scan tracing stage, DEF generated by PnR is used in Star RC extraction.

In detail it contains:

Die Area
Tracks
Components (macros)
I/O Pins
Nets
Blockages
Halo
Scan Chain
Vias
Slots
Fills
Region
Row
Metal layers

Liberty Timing File (LIB)

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.lib is basically a timing model contains cell delays, transition, setup and hold time requirements. CCS and NLDM technique
files. In CCS (composite current source) current source is used for driver modeling, CCS has 20 variables to account input
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where as, NLDM uses the voltage source for driver modeling and it has only 2 variables which are not sufficient for mode
circuit. So CCS is more accurate than NLDM. Because of the difference in number of variables used in both the models, size o
than the NLDM file. Also the run time for CCS is more when compared to NLDM.

The design needs to be tested for certain PVT (process voltage and temperature) corners. But for every PVT corner, the timi
Hence there is a .lib file for every PVT corner.

In .lib file following unit attributes are present

Time unit
Voltage unit
Current unit
Leakage power unit
Capacitive load unit
Slew rate : Lower and upper limit values are defined in terms of percentage for both rise and fall time
Input threshold at rise and fall time
Output threshold for rise and fall time

Look Up table templates are defined for different parameters like delay, hold, passive energy, recovery, removal, setup, with d

For each cell (AND, NAND, Or etc..) following attributes are defined:

Area of cell
Leakage power
Capacitance
Rise and fall capacitance
Properties such as capacitance, direction of the pin etc. for each pin (input and output) will be defined. Further different v
matrix form, as shown in the below example.

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fall_transition(delay_template_5x5) {

index_1 (“0.015, 0.04, 0.08, 0.2, 0.4”);

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index_2 (“0.06, 0.18, 0.42, 0.6, 1.2”);

values ( \

“0.0606, 0.0624, 0.0744, 0.0768, 0.09”, \

“0.1146, 0.1152, 0.1164, 0.1212, 0.1314”, \

“0.201, 0.2004, 0.2052, 0.2058, 0.2148”, \

“0.48, 0.4806, 0.4812, 0.4824, 0.4866”, \

“0.9504, 0.9504, 0.9504, 0.951, 0.9534”);

Output fall transition is characterized based on output capacitance and input transition. Index_1 represents output
represents input transition . In the above example, 5 values are specified in each indexes, if a given value is not there in th
transition by intrapolation or extrapolation. If the value is in between the given values of an index we go for intrapolation or e

Like “fall transition” other parameter also calculated which are as follows:

Rise transition
Internal Power
Fall power
Rise power
Cell fall
Cell rise

Below an another example of D flip flop characterization table is given, which shows the hold falling, and setup falling is als
above attributes. Index_1 is corresponds to related pin transition and index_2 corresponds to constrained pin transition.

timing_type : hold_falling;

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rise_constraint(hold_template_3x5) {

index_1 (“0.06, 0.3, 0.6”); Home Services  Solutions  Domains  Insights  Careers  Company 

index_2 (“0.06, 0.18, 0.42, 0.6, 1.2”);

values ( \

“-0.09375, -0.0875, -0.075, -0.1125, -0.175”, \

“-0.2, -0.19375, -0.18125, -0.21875, -0.1875”, \

“-0.16875, -0.25625, -0.24375, -0.28125, -0.25”);

timing_type : setup_falling;

rise_constraint(setup_template_3x5) {

index_1 (“0.06, 0.3, 0.6”);

index_2 (“0.06, 0.18, 0.42, 0.6, 1.2”);

values ( \

“0.28125, 0.275, 0.2625, 0.3, 0.3625”, \

“0.29375, 0.2875, 0.36875, 0.3125, 0.375”, \

“0.35625, 0.35, 0.3375, 0.375, 0.4375”);

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