Digital VLSI Design
Lecture 1: Introduction
Semester B, 2022
Lecturer: Zvika Webb
21 Feb 2022
Lecture Outline
• Motivation
• Course Logistics
• Building a Chip
• Design Automation
• Chip Design Flow
2
Motivation
1992 – The Intel 486DX2
1.2M Transistors
1964 – The Integrated Circuit
1971 – The Intel 4004 2006 – Itanium 2 “Montecito”
2,300 Transistors 1.7B Transistors
3
Introduced May 2016
Motivation Technology 14nm FinFET
Memory 320KB L1-I$
Core i7-6950X Extreme Edition (Broadwell-E) 320KB L1-D$
2.56MB L2$
25MB L3$
Cores 10
Threads 20
Frequency 3.0-3.5 GHz
Die Size 246 mm2
#Transistors 3.2 B
http://en.wikichip.org/wiki/intel/core_i7ee/i7-6950x 4
5
Motivation
• Houston, we have a problem…
10,000 100,000
1,000 10,000
Logic transistors per chip
(K) Trans./Staff-Mo.
100 1000
Productivity
Gap
(in millions)
10 100
1
IC capacity 10
0.1 1
0.01 productivity 0.1
0.001 0.01
“Moore’s Law of Engineers” 6
Motivation
• How on earth do we design such a thing???
7
History and Evolution of the IC Industry (1)
Clock frequency doubles every 2 years
Clock frequency (MHz)
1010
109
108
107
1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 year
History and Evolution of the IC Industry (2)
Capacity of memories increase about three times every year
Number of bits per chip
1012
8Tbits
1011
4Tbits
1010
4Gbits
109 1Gbits
256Mbits
108
64Mbits
107
16Mbits
106 4Mbits
105 1Mbits
256Kbits
104
64Kbits
103
102 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 year
History and Evolution of the IC Industry (3)
Die size grows by 14% every year
Die size (mm)
1000
220 mm2
100
10
1
1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 year
History and Evolution of the IC Industry (4)
Powers increase about ten times every 3 years
Power (Watts)
1000
100
10
1
1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 year
History and Evolution of the IC Industry (5)
Power densities increase twice every year
Power Density (W/cm2)
1000
100
10
1
1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 year
History and Evolution of the IC Industry (6)
The minimum length of gate is divided by two every 5.4 years
Gate length (nm)
101
100
5 nm
10-1
1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 year
Cost of Transistor
The cost of transistors reduce twice every 1.5 years
cost: ¢-per-transistor
1
0.1
0.01
0.001
0.00001 ¢
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012 2015 2020 Year
History and Evolution of the IC Industry (7)
Semiconductor Industry Association (SIA) Roadmap
Date 1999 2005 2010 2018 2022
Technology (nm) 180 65 28 5 1
Minimum mask count 24 25 27 30 50
Wafer diameter (mm) 200 400 400 450 500
Memory samples (bits) 1G 8G 32G 10T 100T
Transistors/cm2 6.2M 180M 330M 1.5G 20 G
Maximum number of metal layers 6-7 9 9 12 25
Clock frequency (MHz) 1250 3200 5200 20000 35000
IC sizes (mm2 ) 400 596 699 750 1200
Power supply (V) 1.5-1.6 0.8-1.2 1.2-1 0.37-0.42 0.28-0.33
Maximum power (W) 90 150 171 183 1200
Number of pins 700 1957 2734 3350 4200
The Solution:
Design Design Design
Abstraction Automation Re-use (IP)
16
Where does this course fit in? Digital
Introduction Electronic
• In this course, we will learn how to design to Computers Circuits
a chip. and Logic
Design
• You have already learned: Linear
• Build a general purpose micro-processor. Designing with Circuits
Verilog HDL
• How to design a digital gate, analog circuit,
and custom-designed component.
• How to fabricate a chip. Integrated
Microelectronic
Processes
Circuits and
VLSI
• Now, we will learn how to fit all of these
on a chip
…and make sure it
DIGITAL VLSI
works!
DESIGN
17
1 2 3 4 5
Motivation Course Building a Design Chip Design
Logistics Chip Automation Flow
Course Logistics
18
Course Info
• Course number: 0512-4707, Semester B, 2021-22
• Hebrew name: VLSI תכנון מתקדם של מעגלי
• More appropriate name: Digital VLSI Design
• 4 Credits (3 hrs. Lecture + 1 hr. Discussion/Exercise)
• Lectures: Monday 16:00-19:00 – Class Naftali 001
• Lecture will start at 16:10, and will include two breaks
• Zoom meeting for all the semester:
• Meeting ID: 842 3373 3381 Passcode: 632425
• Recitations/Exercise:
• Thursday 15:00-16:00 – Class Kitot Handasa 102
• Thursday 16:00-17:00 – Class Kitot Handasa 102
• You are expected to come to the exercise, after being present in the lecture.
• Presentations and Discussion Handouts will be available before the lecture.
19
Course Administration
• Lecturer:
• Mr. Zvi Webb– but call me Zvika.
• Office Hours:
• Kitot, 2nd Floor, Office 220
• Tuesday 10:00-12:00 – by appointment!
• Contact: webb@tauex.tau.ac.il
• Teaching Assistant:
• Elad Simanian
• Meeting can be done after the Recitation: 17:00 18:00
• Contact: elad
• USE THE FORUM!!!
• Google and Synopsys Support are your best friends!
If you have not yet opened a Synopsys Support account, now is the time!
20
Homework/Projects
• Homework:
• Almost every week, you will receive a homework assignment.
• Deadline for homework is (usually) 1 week from publication.
• Homework is done individually!
• Helping each other is encouraged.
• Grading may be according to the order of submission!
• Submission using git + Moodle(Thank me later!)
21
Grading
• Homework: 20%
• Not equally divided!
• Final Exam: 40%
• Project: 40%
22
Ethics
• Doing your own work
• Please don’t do this course if you don’t
actually want to learn.
• And… we have a ZERO TOLERANCE policy.
• The importance of a grade
• I know that you think you deserved that extra point…
• But… what is the goal of your studies?
• Basic respect
• We are very nice and informal.
• But… remember who you are addressing in an email or any other
means.
• And finally, don’t shoot yourselves (or others) in the foot
• You can find last year’s tests on the student Drive.
• … Now, we will have to write brand new questions.
23
Syllabus Important Dates:
• Lecture 1: Introduction 20/02/2022 – תחילת סמסטר
• Lecture 2: Verilog 10/06/2022 – סוף סמסטר
03/07/2022 – מבחן מועד א
• Lecture 3: Logic Synthesis 14/08/2022 – מבחן מועד ב
• Lecture 4: Static Timing Analysis
• Lecture 5: Moving to the Physical Domain
• Lecture 6: Placement
• Lecture 7: Clock Tree Synthesis
• Lecture 8: Routing
• Lecture 9: I/O and Packaging
• Lecture 10: Design for Test
• Lecture 11: Signoff and tapeout
• Lecture 12: IP’s and other
24
Syllabus
תאריך
תרגול נושא הרצאה
24.02.22 21.02.22מבוא – VLSIהיסטוריה ,שוק ,יישומים ,כלי ,EDAומילון מונחים
03.02.22 – Verilog 03.03.22ורילוג מושגי יסוד,תכנון היררכי ,סימולציה ובדיקות.
10.03.22 - Synthesis 07.03.22סינתזה לוגית,מבנה סיפריות לוגיות ופיזיות
פורים - Synthesis 14.03.22סינתזה לוגית ,מסלול עבודה ,מגבלות הגעה ליעד
24.03.22 – STA 21.03.22ניתוח תיזמון סטטי.אילוצי תכנון ,ביצוע ריצה וקריאת דוחות.
31.03.22 – Floorplanning 28.03.22תכנון מיקום ראשוני של רכיב .רב מתחים ותכנון הספק.
07.04.22 – Placement 04.04.22כיצד כלי ה CADממקמים את התאים ,דרישות.
11.04.22 יום השלמה לימי ה'
28.04.22 - CLOCKS 25.04.22הפצת שעונים ברכיב.שיטות ודרישות
עצמאות -Routing 02.05.22חיווט ,אלגוריתמי חיווט,חיות בפועל וחיווט מיוחד.
12.05.22 – Low Power 09.05.22דרישות מתכנון עבור צמצום ההספק .מספר מתחים וניתוק הספקה.
19.05.22 -Design for Test 16.05.22כיצד מוסיפים לרכיב לוגיקה עבור בדיקות ,דרישות וכלים.
26.05.22 -Chip Sign-off 23.05.22כיצד מסיימים תכנון )מילוי מתכות וכו'( ומכינים רכיב לייצור
יום הסטודנט -IP’s 30.05.22הטמעה של פונקציות מוכנות לתכנון VLSI
09.06.22 06.06.22חזרה למבחן 25
References
• Way too many to state all, and hopefully many are cited
on the slides themselves, but here are a few:
• Rob Rutenbar – “From Logic to Layout” (available on Coursera)
• Nir Sever – Low Power Design (BGU)
• Roy Shor – ( תכן לוגיBGU)
• IDESA Digital Design Course
• Rabaey “Digital Integrated Circuits” 2nd Edition
• Weste, Harris “CMOS VLSI Design”
• Google (oh, thank you Google!)
• Cadence Support (support.cadence.com)
• Synopsys SolveNet (solvenet.synopsys.com)
• And many, many more…
26
1 2 3 4 5
Motivation Course Building a Design Chip Design
Logistics Chip Automation Flow
Building a Chip
27
General Design Approach
• How do engineers build a bridge?
• Divide and conquer !!!!
• Partition design problem into many sub-problems, Partition
which are manageable
• Define mathematical model for sub-problem Model/Solution
and find an algorithmic solution
• Beware of model limitations and check them !!!!!!!
• Implement algorithm in individual design tools, Tools/Interfaces
define and implement general interfaces between
the tools
Verify/Validate
• Implement checking tools for boundary conditions
• Concatenate design tools to general design flows
which can be managed Develop Flow
• See what doesn’t work and start over. 28
Basic Design Abstraction Another view:
Application
System Level
Algorithm
Register Transfer Level Programming Language
Gate Level OS / Virtual Machine
Instruction Set Architecture
Transistor Level
Microarchitecture
Layout Level
Register-Transfer Level
Mask Level
Circuits
Devices
Physics
29
System Level Abstraction System Level
Register Transfer Level
• Abstract algorithmic description of high-level
behavior Gate Level
• e.g., C-Programming language
Port* compute_optimal_route_for_packet Transistor Level
(Packet_t *packet, Channel_t *channel)
{
static Queue_t *packet_queue; Layout Level
packet_queue = add_packet(packet_queue, packet);
...
}
Mask Level
• Abstract because it does not contain any
implementation details for timing or data
• Efficient to get a compact execution model
as a first design draft
• Difficult to maintain throughout project
because no link to implementation
30
Register-Transfer Level (RTL) System Level
Register Transfer Level
• Cycle accurate model “close” to the
hardware implementation Gate Level
• bit-vector data types and operations as
abstraction from bit-level implementation Transistor Level
• sequential constructs module mark1;
reg [31:0] m[0:8192];
(e.g., if-then-else, reg [12:0] pc; Layout Level
while loops) to support reg [31:0] acc;
reg[15:0] ir;
modeling of complex Mask Level
control flow always
begin
ir = m[pc];
if(ir[15:13] == 3b’000)
pc = m[ir[12:0]];
else if (ir[15:13] == 3’b010)
acc = -m[ir[12:0]];
...
end
endmodule
31
Gate Level Abstraction (GTL) System Level
Register Transfer Level
• Model on finite-state machine level
• Models function in Boolean logic using Gate Level
registers and gates
• Various delay models for gates and wires Transistor Level
Layout Level
3ns 4ns
Mask Level
5ns
32
Transistor to Mask Level System Level
Register Transfer Level
• As we’ve seen in previous courses:
• Transistor Level: Gate Level
• Use compact models to enable
accurate circuit simulation. Transistor Level
• Layout Level:
• Draw polygons to implement the Layout Level
devices and interconnect.
• Mask Level:
Mask Level
• Create actual
photo-masks for
performing
lithography during
fabrication process.
Images courtesy of wikipedia 33
1 2 4 5
3
Motivation Course Design Chip Design
Building a Chip
Logistics Automation Flow
Design Automation
34
The (really) Olden Days
• Early chips were prepared entirely by hand:
Schematic of Intel 4004 (1971)
Mainframe CAD System (1967)
http://www.computerhistory.org/revolution/digital-logic 35
The (really) Olden Days
• Early chips were prepared entirely by hand:
Hand drawn gate layout (Fairchild)
Rubylith Operators (1970) The original Tape-Out?
http://www.computerhistory.org/revolution/digital-logic
8088A Mask Transparent Overlays (1976) 36
Design Automation Today
Design: Simulation: Validation:
• High-Level Synthesis • Transistor Simulation • ATPG
• Logic Synthesis • Logic Simulation • BIST
• Schematic Capture • Hardware Emulation
• Layout • Technology CAD
• PCB Design • Field Solvers
Analysis and Verification: Mask Preparation:
• Functional Verification • Optical Proximity Correction (OPC)
• Clock Domain Crossing • Resolution Enhancement Techniques
• Formal Verification • Mask Generation
• Equivalence Checking
• Static Timing Analysis
• Physical Verification 37
EDA in this Course
• RTL
• Verilog
• Synthesis
• Design Compiler (Fusion Compiler)
• Place and Route
• P&R- IC Compiler II (Fusion Compiler)
• Static Timing Analysis – Prime Time
• Power Estimation – Prime Power
• Parasitic Extraction – StarRC
• Logic Simulation
• VCS
38
Other EDA
• RTL
• Verilog
• Synthesis
• Cadence Genus
• Place and Route
• Cadence Innovus
• Static Timing Analysis – Tempus
• Power Estimation – Voltus
• Parasitic Extraction – QRC
• Clock Tree Synthesis - CCOpt
• Logic Simulation
• Cadence Incisive (irun)
Source: IEEE Electronics 360 39
1 2 3 4 5
Motivation Course Building a Design Chip Design
Logistics Chip Automation Flow
Chip Design Flow
40
How a chip is built Definition and Planning
• Definition and Planning Design and Verification
• Design and Verification (Frontend)
• Logic Synthesis (Frontend and Backend) Logic Synthesis
• Physical Design (Backend)
Physical Design
• Signoff and Tapeout
• Silicon Validation Signoff and Tapeout
• Don’t forget package & board design, Silicon Validation
software design, test plan, etc., etc., etc.
41
Definition and Planning
Definition & Planning Design and Verification
• Marketing Requirements Document (MRD) Logic Synthesis
• Chip Architecture
Physical Design
• Define bus structures, connectivity
• Partition Functionality Signoff and Tapeout
• High-Level System Model (Bandwidths, Power, Freq.)
• System partitioning (HW vs SW, #Cores, Memories…) Silicon Validation
• Design Documents
• Floorplan/Board Requirements
• Process and fab
• Project kick-off – transfer to implementation
42
Definition and Planning
Design and Verification Design and Verification
• RTL (Register Transfer Level) Design Logic Synthesis
• Integration/Development of IPs
Physical Design
• RTL Lint/Synthesability checks
• Formal Verification Signoff and Tapeout
• Functional verification all the IPs: Silicon Validation
• Unit level
• Sub-system level
• Chip (SOC) level
43
Design and Verification - IP Integration
Definition and Planning
Design and Verification
• Hard IP
Logic Synthesis
• IP provided as pre-existing layouts with: Physical Design
• Timing models Signoff and Tapeout
• Layout abstracts Silicon Validation
• Behavioral models (Verilog/VHDL)
• Sometimes with Spice models, full-layouts
• This is the standard delivery format for custom digital blocks
• RAMs, ROMs, PLLs, Processors
• Soft IP
• RTL Code
• Can be encrypted
• Instantiated just like any other RTL block
• Sometimes with behavioral models
44
Design and Verification - Prototyping
Definition and Planning
Design and Verification
• Different levels of verification:
Logic Synthesis
• Specification driven testing Physical Design
• Bug driven testing Signoff and Tapeout
• Coverage driven testing Source: mouser.com
Silicon Validation
• Regression
• FPGA Prototyping:
• Synthesize to FPGA
• Speeds up testing
where possible.
• Hardware Emulation:
• Big servers that can
emulate the entire
design.
45
Definition and Planning
Logic Synthesis Design and Verification
• Inputs: • Synthesis Logic Synthesis
• Technology library • Converting RTL code into a generic logic
file netlist Physical Design
• RTL files • Mapping
• Constraint files (SDC) • Mapping generic netlist into standard cells Signoff and Tapeout
• DFT definitions from the core library
• Output: • Optimization Silicon Validation
• To meet Timing / Area / Power constraints
• Gate-level netlist
module DFF(Clk, D, Q);
D Q • Post Synthesis checks
input Clk;
input D;
• Gate-level simulation
output Q; • Formal verification (Logic Equivalence)
always @(posedge Clk) • Static Timing Analysis (STA)
Q <= D; Clk • Power/Area estimation
endmodule
46
Definition and Planning
Physical Design (Backend) Design and Verification
• Floorplan Logic Synthesis
• I/O Ring
Physical Design
• Power Plan
• Placement Signoff and Tapeout
• Clock Tree Silicon Validation
Synthesis
• Route
• DRC, LVS,
Antennas, EM
• LEC, Post-layout
47
Physical Design – Backend Flow
Definition and Planning
Design and Verification
• Physical Implementation Inputs
Logic Synthesis
Physical Design
Front-End Vendors Foundry Signoff and Tapeout
Spec Standard Cells Device Models
Silicon Validation
Architecture Memory Compiler Techfile
RTL I/Os Design Rules
Verification Hard IPs
Physical Design
(Backend)
48
Physical Design – Backend Flow Definition and Planning
Design and Verification
RTL
Synthesizer
Logic Synthesis
Gate Level
SDC Physical Design
Standard Cells and ATPG GTL with Scan Signoff and Tapeout
Macros Silicon Validation
Scan Chains Placer Placed Design
Floorplan CTS
Design with
Clock Tree
Power Grid,
Special Routing
Router Routed Design
Clock Definitions
Extraction, STA, DRC,
LVS, Density, Antennas, GDSII
Caps, Power/EM 49
Signoff and Tapeout
Definition and Planning
• Parasitic Extraction
Design and Verification
• STA with SI
• DRC/LVS/ERC/DFM Logic Synthesis
• Post-layout Gate-level Simulation Physical Design
• Power Analysis
Signoff and Tapeout
• DFT
• Logic Equivalence Silicon Validation
50
Glossary
• Just to cover most of the terminology of today’s lesson:
• RTL • Hard IP
• GTL • Soft IP
• CAD • FPGA
• EDA • Emulation Special Thanks to:
Prof Adi Teman
• DFT (ATPG, • Lint For the knowledge and materials
Scan, BIST) • Formal Verification required for preparing this lecture.
• OPC • STA
• Frontend • SDC
• Backend • SI
• Verification • DRC, LVS, EM
• Signoff • GDSII
• Tapeout • PPA
51
Glossary
• Just to cover most of the terminology of today’s lesson:
• RTL - Register Transfer Language
• GTL - Gate Level Language
• CAD - Computer-aided design
• EDA - Electronic design automation
• DFT (ATPG, Scan, BIST ) - Design for Test
• OPC - Optical Precision Components
• Frontend – RTL design up to Synthesis
• Backend – Place & Route
• Verification - Simulation,
• Signoff – Final chip verification (Timing and Physical)
• Tapeout – Final Design data for Fabrication
52
Glossary
• Just to cover most of the terminology of today’s lesson:
• Hard IP - IP after Layout
• Soft IP – IP in RTL level
• FPGA - Field-programmable gate array
• Emulation – Fast Simulation using Hard work
• Lint - Static code analysis tool
• Formal Verification
• STA – Static timing analysis
• SDC - Synopsys Design Constraints
• SI – Signal Integrity
• DRC, LVS, EM
• GDSII - Stream format (Graphic Design System)
• PPA – Power, Performance, Area
53
