Introduction to Digital VLSI

Design
‫ ספרתי‬VLSI ‫מבוא לתכנון‬

Introduction

Lecturer: Gil Rahav

Semester B’, EE Dept. BGU.
Freescale Semiconductors Israel

1
 IC Products

Processors
 CPU, DSP, Controllers

Memory chips
 RAM, ROM, EEPROM

Analog
 Mobile communication,
audio/video processing

Programmable
 PLA, FPGA

Embedded systems
 Used in cars, factories
 Network cards

System-on-chip (SoC)

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 Why VLSI?

Integration improves the design:

 lower parasitics = higher speed;
 lower power;
 physically smaller.

Integration reduces manufacturing cost-(almost) no manual
assembly.

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 Why build integrated Circuit?

IC Technology drives the whole innovative devices and systems which

effects the way we live.
 ICs are much smaller.
 Consume less power than discrete component.
 Easier to design and manufacture.
 More reliable than discrete system.
 Can design more complex system.

The growth of electronic industry.

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 Example of VLSI application

Electronic system in cars.

Digital electronics control VCRs

Transaction processing system, ATM

Personal computers and Workstations

Medical electronic systems.

etc….

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 The advantageous of digital ICs over the
discrete components (1/2)

Size
 much smaller both transistor and wires.
 leads to smaller parasitic resistances, capacitances and inductances

Speed
 communication within the chips are much faster than between a chips
on PCB (Printed Circuit Board).
 High speed of circuits on-chip due to smaller size.

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 The advantageous of digital ICs over the
discrete components (2/2)

Power Consumption
 Logic operation within the chip consumes
much less power.
 smaller size -> smaller parasitic
capacitances and resistance -> require less
power to drive the circuit.

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 Advantages of IC at System Level(1/2)

Smaller Physical Size

 can make a small electronic appliances. ie. portableTV, handheld
cellular telephone…

Lower Power Consumption
 reduce total power consumption on a whole electronic circuit.
 Cheaper power supply which leads to a simpler cabinet for power
supply. Less heat, Fan may no longer be necessary.

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 Advantages of IC at System Level(2/2)
Level(2/2)

Reduce Cost
 Reducing in number of components.
 Power Supply requirement.
 Cabinets
 The cost of building a whole system is reduce eventhough Ics cost
more.

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 Cost factors in ICs

For large-volume ICs:

 packaging is largest cost;
 testing is second-largest cost.

For low-volume ICs, design costs may swamp all manufacturing
costs.

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 Integrated Circuit Manufacturing

Technology
 Let us build a system faster, and more complex system
Economics
 In 1960s,Gordon Moore said that the number of transistor would grow
exponentially. The number of transistors per chip has doubled about once a
year.
 IC plant is very expensive. $2-3billion or more.
 Is it worth to invest in IC business?

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 Moore’s Law
• In 1965, Gordon Moore predicted that the number of transistors that can be
integrated on a die would double every 18 to 14 months (i.e., grow exponentially
with time).
• Amazing visionary – million transistor/chip barrier was crossed in the 1980’s.
– 2300 transistors, 1 MHz clock (Intel 4004) - 1971
– 42 Million, 2 GHz clock (Intel P4) - 2001
– 140 Million transistor (HP PA-8500)

Source: Intel web page (www.intel.com)

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 Die Size Growth

Die
Die size
size grows
grows by
by 14%
14% to
to satisfy
satisfy Moore’s
Moore’s Law
Law
100
Die size (mm)

P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years

1
1970 1980 1990 2000 2010
Year
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 Clock Frequency

Lead
Lead microprocessors
microprocessors frequency
frequency doubles
doubles every
every 22 years
years
10000

1000 2X every 2 years

Frequency (Mhz)

P6
100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
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 Challenges in VLSI design

Multiple levels of abstraction: transistors to CPUs.

Multiple and conflicting constraints: low cost and high
performance are often at odds.

Short design time: Late products are often irrelevant.

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 Jobs in VLSI

Layout designers

Circuit designers

Architects

Test engineers

Fabrication engineers

System designers

CAD tool programmers

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 The VLSI design process

May be part of larger product design.

Major levels of abstraction:
 specification;
 architecture;
 logic design;
 circuit design;
 layout.

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 Design Abstraction Levels

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 VLSI Levels of Abstraction
Specification
(what the chip does, inputs/outputs)

Architecture
major resources, connections

Register-Transfer
logic blocks, FSMs, connections

Logic
gates, flip-flops, latches, connections

Circuit
transistors, parasitics, connections

Layout
mask layers, polygons
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 Dealing with complexity

Divide-and-conquer: limit the number of components you

deal with at any one time.

Group several components into larger components:
 transistors form gates;
 gates form functional units;
 functional units form processing elements;
 etc.

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 Hierarchical name

Interior view of a component:

 components and wires that make it up.

Exterior view of a component = type:
 body;
 pins.
cout

sum
a Full
adder
b
cin

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 Instantiating component types

Each instance has its own name:
 add1 (type full adder)
 add2 (type full adder).

Each instance is a separate copy of the type:

Add2.a
Add1.a cout

sum sum
a Add1(Full a Add2(Full
adder) adder)

b b
cin cin

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 A hierarchical logic design

box1 box2 x

z
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 Net lists and component lists

Net list:
Component list:

net1: top.in1 in1.in top: in1=net1 n1=topin1 n2=topin2
net2: i1.out xxx.B n3=botin1 out=outnet
topin1: top.n1 xxx.xin1 i1: in=net1 out=net2
topin2: top.n2 xxx.xin2 xxx: xin1=topin1 xin2=topin2
botin1: top.n3 xxx.xin3 xin3=botin1 B=net2 out=net3
net3: xxx.out i2.in i2: in=net3 out=outnet
outnet: i2.out top.out

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 Component hierarchy

top

i1 xxx i2

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 Hierarchical names

Typical hierarchical name:

 top/i1.foo

component pin

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 Transistor schematic

+
φ'

D Q'

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 Mixed schematic

φ'

D Q'

inverter

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 Levels of abstraction

Specification: function, cost, etc.

Architecture: large blocks.

Logic: gates + registers.

Circuits: transistor sizes for speed, power.

Layout: determines parasitics.

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 Circuit abstraction

Continuous voltages and time:

v v

t t

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 Digital abstraction

Discrete levels, discrete time:

a
cout
a
sum
t full sum
b adder
b
t
cin
t
a
cout
a
sum
t
b full sum
adder
b t
cin
t

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 Register-transfer abstraction

Abstract components, abstract data types:

0010
+
0001
+ 0011

0100

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 Register-transfer abstraction

Abstract components, abstract data types:

0010
+
0001
+ 0111

0100

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 Top-down vs. bottom-up design

Top-down design adds functional detail.

 Create lower levels of abstraction from upper levels.

Bottom-up design creates abstractions from low-level
behavior.

Good design needs both top-down and bottom-up efforts.

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 Design abstractions

English specification
Executable Throughput,
program behavior design time

register- Function units,

Sequential clock cycles
transfer
machines
Literals,
Logic gates logic logic depth

transistors circuit nanoseconds

rectangles layout microns

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 Design validation

Must check at every step that errors haven’t been introduced-
the longer an error remains, the more expensive it becomes
to remove it.

Forward checking: compare results of less- and more-
abstract stages.

Back annotation: copy performance numbers to earlier
stages.

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 Manufacturing test

Not the same as design validation: just because the design is
right doesn’t mean that every chip coming off the line will be
right.

Must quickly check whether manufacturing defects destroy
function of chip.

Must also speed-grade.

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 VLSI Design Cycle

38
 IC Design Steps
High-level
High-level Functional
Functional
Specifications
Specifications Description
Description Description
Description

Behavioral Structural
HDL, C HDL

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 IC Design Steps (cont.)
High-level
High-level Functional
Functional
Specifications
Specifications Description
Description Description
Description

Synthesis
Physical Technology
Design Mapping
Placed
Placed Logic
&& Routed Gate-level
Gate-level Logic
Routed Design Description
Description
Design
Design Design

Packaging Fabri-
Fabri- X=(AB*CD)+
cation (A+D)+(A(B+C))
Y = (A(B+C)+AC+
D+A(BC+D))
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Figs. [©Sherwani]
 VLSI Design Cycle (2/9)

System Specification – Specification of the size, speed,

power and functionality of the VLSI system.
Architectural Design – Decisions on the architecture, e.g.,
RISC/CISC, # of ALU’s, pipeline structure, cache size, etc.
Such decisions can provide an accurate estimation of the
system performance, die size, power consumption, etc.

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 VLSI Design Cycle (3/9)
Functional Design – Identify main functional units and their
interconnections. No details of implementation.

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 VLSI Design Cycle (4/9)
Logic Design – Design the logic, e.g., boolean
expressions, control flow, word width, register allocation,
etc. The outcome is called an RTL (Register Transfer
Level) description. RTL is expressed in a HDL (Hardware
Description Language), e.g., VHDL and Verilog.

X = (AB+CD)(E+F)
Y= (A(B+C) + Z + D)

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 VLSI Design Cycle (5/9)
Circuit Design – Design the circuit including gates,
transistors, interconnections, etc. The outcome is called a
netlist.

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 VLSI Design Cycle (6/9)

Component list:

Net list: top: in1=net1 n1=topin1 n2=topin2
net1: top.in1 in1.in n3=botin1 out=outnet
net2: i1.out xxx.B i1: in=net1 out=net2
topin1: top.n1 xxx.xin1 xxx: xin1=topin1 xin2=topin2 xin3=botin1
topin2: top.n2 xxx.xin2 B=net2 out=net3
botin1: top.n3 xxx.xin3 i2: in=net3 out=outnet
net3: xxx.out i2.in
outnet: i2.out top.out

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 VLSI Design Cycle (7/9)

Component hierarchy

top

i1 xxx i2

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 VLSI Design Cycle (8/9)
Physical Design – Convert the netlist into a geometric
representation. The outcome is called a layout.

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 VLSI Design Cycle (9/9)

Fabrication – Process includes lithography, polishing,

deposition, diffusion, etc., to produce a chip.
Packaging – Put together the chips on a PCB (Printed
Circuit Board) or an MCM (Multi-Chip Module)

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 VLSI Design Cycle

System Specification Netlist

Architectural Physical
Design Design

Architectural Layout
Specification Circuit Design
or Fabrication
Functional
Logic Synthesis
Design
Chips
Timing & relationship
Packaging
between functional units
Logic Packaged and
Design
tested chips
RTL in HDL
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 Physical Design Cycle (1/6)
Circuit Partitioning

Floorplanning & Placement

Clock Tree

Routing

Layout Compaction

Extraction and Verification

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 Physical Design Cycle (2/6)
Circuit Partitioning – Partition a large circuit into sub-circuits
(called blocks). Factors like #blocks, block sizes,
interconnection between blocks, etc., are considered.





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 Physical Design Cycle (3/6)
Floorplanning – Set up a plan for a good layout. Place the
modules (modules can be blocks, functional units, etc.) at an
early stage when details like shape, area, I/O pin positions of
the modules, …, are not yet fixed.

Deadspace

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 Physical Design Cycle (4/6)
Placement – Exact placement of the modules (modules can be
gates, standard cells, etc.) when details of the module design
are known. The goal is to minimize the delay, total area and
interconnect cost.

Feedthrough
Standard cell type 1
Standard cell type 2
v

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 Physical Design Cycle (5/6)
Routing – Complete the interconnections between
modules. Factors like critical path, clock skew, wire
spacing, etc., are considered. Include global routing and
detailed routing.

Feedthrough
Type 1 standard cel1
v
Type 2 standard cell

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 Physical Design Cycle (6/6)

Compaction – Compress the layout from all directions to

minimize the total chip area.
Verification – Check the correctness of the layout. Include DRC
(Design Rule Checking), circuit extraction (generate a circuit
from the layout to compare with the original netlist),
performance verification (extract geometric information to
compute resistance, capacitance, delay, etc.)

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 Design Styles

Full-Custom ASICs
 Some (possibly all) logic cells are customized and
all mask layers are customized

Semicustom ASICs
 All logic cells are predesigned (defined in cell library) and some
(possibly all) of the mask layers are customized
 Types:
Standard-cell based and Gate-array-based ASICs

Programmable ASICs
 All logic cells are predesigned and
none of the mask layers are customized
 Types: PLD (Programmable Logic Device) and
FPGA (Field Programmable Gate Array)

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 Full-custom ASICs (1/3)

Engineers design some or all of the logic cells, circuits, or

layout specifically for one ASIC
 Full-custom ICs are the most expensive
to manufacture and to design
 Manufacturing lead time (the time it takes just to make an IC – not
including design time) is typically 8 weeks

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 Full-custom ASICs (2/3)

When does it make sense?
 there are no suitable existing cell libraries available
 existing logic cells are not fast enough
 logic cells are not small enough
 logic cells consume too much power
 ASIC is so specialized that
some circuits must be custom designed

Trends: fewer and fewer full-custom ICs are being designed
(excluding mixed analog/digital ASICs)

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 Full Custom Design (3/3)

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 Standard-Cell-Based ASICs (1/5)

Cell-Based ASIC (CBIC) uses pre-designed cells
(AND, OR gates, multiplexers, flip-flops, ...)

Standard-cell areas are built of rows of standard cells

Standard-cell areas can be used in combination with larger pre-
designed cells (microcontrollers, or even microprocessors), known as
megacells

A cell-based
ASIC (CBIC) die
with a single
standard-cell
area combined
with 4 fixed
blocks

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 Standard-Cell-Based ASICs(2/5)

Characteristics
 custom blocks can be embedded;
ASIC designer defines only the placement of the standard cells and
the interconnect in a CBIC
 standard cells can be placed anywhere on a silicon =>
all mask layers of a CBIC are customized
 manufacturing lead time is 8 weeks

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 Standard-Cell-Based ASICs (3/5)

Advantages
 designers save time, money, and reduce risks using a predesigned,
pretested, and precharacterized standard-cell library
 standard cells in the library are constructed using full-custom;
each standard cell can be optimized individually
(for example, to maximize speed, minimize area, etc);

Disadvantages
 time or expense of designing or buying the standard-cell library
 time needed to fabricate all layers of the ASIC for each new design

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 Standard-Cell-Based ASICs(4/5)

Standard-cells are designed

to fit horizontally together to form rows

Internal construction of a cell

- 25 microns wide (lambda is 0.25)

- AB: abutment box
- BB: bounding box
- Power supplies: VDD, GND
- Each different shaded and
labeled pattern represents a
different layer
- Connections: A1, B1, Z

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 Standard-Cell-Based ASICs (5/5)
- Interconnections
between cells use

Routing the CBIC spaces (called
channels) between
rows
- 2 separate layers of
metal interconnect
(metal1 and metal2)
running at right angles
to each other
- Feedthrough: refers
either to the piece of
metal that is used to
pass a signal through a
cell or to a space in a
cell waiting to be used
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 Programmable Logic Devices(1/2)

PLDs
 standard ICs, available in standard configurations
 sold in high volume to many different customers
 PLDs may be configured or programmed to create
a part customized to specific application

Characteristics
 no customized mask layers or logic cells
 fast design turnaround
 a single large block of programmable interconnect
 a matrix of logic macrocells that usually consists of programmable array
logic followed by a flip-flop or latch

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 Programmable Logic Devices(2/2)

Types of PLDs
 PROM: uses metal fuse that can be blown permanently)
 EPROM: used programmable MOS transistors whose characteristics are altering by
applying a high voltage
 PAL – Programmable Array Logic
• programmable AND logic array or AND plane,
and fixed OR plane
 PLA – Programmable Logic Array
• programmable AND plane
followed by programmable OR plane

Depending on how
the PLD is programmed
 erasable PLD (EPLD)
 mask-programmed PLD

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 Field-Programmable Gate Arrays (FPGA)

FPGA
 a step above the PLD in complexity;
it is usually larger and more complex than a PLD
 rapidly growing in importance

Characteristics
 none of mask layers are customized
 a method for programming basic cells
and the interconnect
 the core is regular array
of programmable basic logic cells
(combinational + sequential)
 a matrix of programmable interconnect
that surrounds the basic cells
 programmable I/O cells around the core
 design turnaround is a few hours

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 Digital Logic Circuit Definitions
PLD
Programmable Logic Devices

SPLD HCPLD
Simple PLD High Capacity PLD

PLA PAL
Programmable Logic Array Programmable Array Logic

CPLD FPGA
Complex PLD Field Programmable Gate Array

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 Cell development (Analog/digital)

Schematic entry (transistor symbols)

Analog simulation (SPICE models)

Layout (layer definitions)

Design Rule Checking, DRC ( design rules)

Extraction (extraction rules and parameters)

Electrical Rule Checking, ERC (ERC rules)

Layout Versus Schematic, LVS ( LVS rules)

Analog simulation.

Characterization: delay, setup, hold, loading sensitivity,etc.

Generation of digital simulation model with back annotation.

Generation of synthesis model

Generation of “black-box” for place & route
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 Digital design

Behavioral simulation

Synthesis (synthesis models)

Gate level simulation (gate models)

Floor planning

Loading estimation (loading estimation model)

Simulation/timing verification with estimated back-annotation

Place and route (place and route rules)

Design Rule Check, DRC (DRC rules)

Loading extraction (rules and parameters)

Simulation/timing verification with real back-annotation

Design export

Testing: Test generation, Fault simulation, Vector translation
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 Design entry

Layout
 Drawing geometrical shapes: Defines layout hierarchy
Defines layer masks
Requires detailed knowledge about CMOS technology
Requires detailed knowledge about design rules (hundreds of rules)
Requires detailed knowledge about circuit design
Slow and tedious
Optimum performance can be obtained

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Schematic
 Drawing electrical circuit: Defines electrical hierarchy
Defines electrical connections
Defines circuit: transistors, resistors,,,
Requires good circuit design knowledge for analog design
Requires good logic design knowledge for digital design (boolean logic, state machines)
Gives good overview of design hierarchy
Significant amount of time used for manual optimization

Transistor level Gate level Module level

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Behavioral + Synthesis
 Writing behavior (text): Defines behavioral hierarchy
Defines algorithm
Defines architecture
 Synthesis tool required to map into gates
 Often integrated with graphical block diagram tool.
module add_and_mult( a,b,c, out)
input[31:0] a,b,c;
output[31:0] out;
wire[31:0] internal_add; assign #(test.logic_delay)
bsr_clk = ~(m_extest | m_sample | m_intest) | clk_dr,
adder32 add1(a,b, internal_add); bsr_shift = (m_extest | m_sample | m_intest) & shift_dr,;
multiplier32 mult1( internal_add, c, out);
endmodule
always @(posedge clk)
begin
if (set) coarse <= #(test.ff_delay) offset;
else if (coarse == count_roll_over)
coarse <= #(test.ff_delay) 0;
else coarse <= #(test.ff_delay) coarse + 1;
end
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 Verification

Design Rule Check (DRC):

Checks geometrical shapes: width, length, spacing, overlap, etc.

Electrical rule check (ERC):
Checks electrical circuit: unconnected inputs
shorted outputs
correct power and ground connection
a

b
?

Extraction: Vdd
Extracts electrical circuit: transistors, connections, capacitance,
resistance
IN Out

Layout versus schematic (LVS):
Gnd
Compares electrical circuits: transistors: parallel or serial
(schematic and extracted layout)

10 10 10 10 10 10 40

EXT LVS

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 Simulation

Simulates behavior of designed circuit

 Input: Models (transistor, gates, macro)
Textual netlist (schematic, extracted layout, behavioral)
User defined stimulus
 Output: Circuit response (waveforms, patterns), Warnings

Transistor level simulation using analog simulator (SPICE)
 Time domain
 Frequency domain
 Noise

Gate level simulation using digital simulator
 Logic functionality
 Timing: Operating frequency, delay, setup & hold violations
Timing calculator needed to calculate delays from extracted Normally same
parameters simulator

Behavioral simulation
 System and IC definition ( algorithm, architecture )
 Partitioning
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 Complexity estimation Gil Rahav
 Gate level models

Border between transistor domain (analog)
and digital domain

Digital gate level models introduced to speed
up digital simulation.

Gate level model contains:
 Logic behavior
 Delays depending on: operating conditions, process, loading,
signal slew rates
 Setup and hold timing violation checks

Gate level model parameters extracted from
transistor level simulations and
characterization of real gates.

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 Place and Route

Generates final chip from gate level netlist

 Goals: Minimum chip size
Maximum chip speed.

Placement:
 Placing all gates to minimize distance between connected gates
• Floor planning tool using design hierarchy
• Specialized algorithms ( min cut, simulated annealing, etc.)
• Timing driven Simulated annealing
• Manual intervention High temperature:
move gates randomly
 Very compute intensive
Hierarchy based floor planning Min cut
Low temperature:
Move gates locally
Keep cutting design
into equal sized pieces

For each cut:

Move gates around
until minimum connection
across cut
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Routing:
 Channel based: Routing only in channels between gates
(few metal layers: 2)
 Channel less: Routing over gates
(many metal layers: 3 - 6)
 Often split in two steps:
• Global route: Find a coarse route depending on local routing
density
• Detailed route: Generate routing layout
Channel based Channel less

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Performance of sub-micron CMOS IC’s are to a large extent
determined by place & route.
 Loading delays bigger than intrinsic gate delays
 Wire R-C delays becomes important in sub-micron
 Clock distribution over complete chip gets critical at operating
frequencies above 100Mhz.
Delay Number of wires

200ps Wire load delay

Local connections
100ps

50ps
Global connections
Gate delay
25ps

Technology
1.0u 0.5u 0.25u 0.1u Wire length

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 Design tool framework

Design tools from one vendor normally integrated into a

framework which enables tools to exchange data.
 Common data base
 Automatic translation from one type to another
 (Allows third part tools to be integrated into framework)

Few standards to allow transport of designs between tools
from different vendors.
 VHDL and Verilog behavioral models and netlists
 EDIF netlist, SPICE netlist for analog simulation
 GDSII layout
 Standard Delay Format (SDF) for gate delays.
 Small vendors must be compatible with large vendors.
Transporting designs between tools from
different vendors may cause problems
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 Hardware describing languages
(HDL)

Describe behavior not implementation

Make model independent of technology

Model complete systems

Specification of sub-module functions

Speed up simulation of large systems

Standardized text format

CAE tool independent

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VHDL
 Very High speed integrated circuit Description Language
 Initiated by American department of defense as a specification
language.
 Standardized by IEEE

Verilog
 First real commercial HDL language from gateway automation (now
Cadence)
 Default standard among chip designers for many years
 Until a few years ago, proprietary language of Cadence.
 Now also a IEEE standard because of severe competition from
VHDL. Result: multiple vendors

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Compiled/Interpreted
 Compiled:
• Description compiled into C and then into binary or
directly into binary
• Fast execution
• Slow compilation
 Interpreted:
• Description interpreted at run time
• Slow execution
• Fast “compilation”
• Many interactive features
 VHDL normally compiled
 Verilog exists in both interpreted and compiled versions

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 HDL design entry

Text:
 Tool independent
 Good for describing algorithms
 Bad for getting an overview of a large design

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Add-on tools
 Block diagrams to get overview of hierarchy
 Graphical description of final state machines (FSM)
• Generates synthesizable HDL code
 Flowcharts
 Language sensitive editors
 Waveform display tools
From Visual HDL, Summit design

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 Synthesis and Technology
dependence
Algorithm For i = 0 ; i = 15
sum = sum + data[I]
0% technology dependent
i
Data[0] Data[0] Data[15]
Architecture
10% technology dependent Data[15]

Sum
Sum
Behavioral synthesis
Clear
address MEM
Register level
Clock
20% technology dependent Clear
sum

Logic synthesis

Gate level
100% technology dependent

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 Logic synthesis

HDL compilation (from VHDL or Verilog)

 Registers: Where storage is required
 Logic: Boolean equations, if-then-else, case, etc.

Logic optimization
 Logic minimization (similar to Karnaugh maps)
 Finds logic sharing between equations
 Maps into gates available in given technology
 Uses local optimization rules
6 basic CMOS gates
3 logic gates

3 basic CMOS gates

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Timing optimization
 Estimate loading of wires
 Defined timing constraints (clock frequency, delay, etc.)
 Perform transformations until all constraints fulfilled
Arriving late
Arriving late

Complex
logic
0 0
Complex
logic 1
Arriving late
Complex
logic Arriving late
1

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 Synthesis goals

Combined timing - size optimization

 Smallest circuit complying to all timing constraints
Size

Design space

Delay
Requirements

 Best solution found as a combination of special optimization

algorithms and evaluation of many alternative solutions
(Similar to simulated annealing)

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Problems in synthesis
 Dealing with “single late signal”
 Mapping into complex library elements
(special directives required)
 Regular data path structures:
• Adders: ripple carry, carry look ahead, carry select,etc.
• Multipliers, etc.
Use special guidance to select special adders, multipliers, etc..
Performance of sub-micron technologies are dominated by wiring delays
(wire capacitance + R-C delays)

Synthesis in many cases does a better job than a manually
optimized logic design.
(in much shorter time)

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 Timing estimation in synthesis

Wire loading
Timing optimization is based on a wire loading model.
Loading of gate = input capacitance of following gates + wire capacitance
Gate loading known by synthesizer
Wire loading must be estimated
R-C delay calculation very complicated
Delay Relative number
Average Average
200ps Wire load delay

100ps

50ps
Gate delay Large chip
25ps Small chip

Technology
1.0u 0.5u 0.25u 0.1u Wire capacitance

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Estimate wire capacitance from number of gates connected
to wire.
Wire capacitance

Large chip

Small chip

Number of gates per wire

Advantage: Simple model

Disadvantage: Bad estimate of long wires
(which limits circuit performance)

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Estimate using floor plan

Inside local region: Region 1

Estimate as function of number
of gates and size of region
Region 3
Between regions:
Use estimate of physical distance
between routing regions. Region 2

Advantage: Realistic estimate

Disadvantage: Synthesizer most work with complete design

In sub-micro CMOS technologies Synthesis and Place & Route

must work hand in hand

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 Trends in synthesis

Integration of synthesis and P&R

Synthesizable standard modules (Processor, PCI
interface, Digital filters, etc.)

Automatic insertion of scan path for production
testing.

Synthesis for low power

Synthesis of self-timed circuits (asynchronous)

Behavioral synthesis

Formal verification

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 Technology Trends

Processor
 Logic capacity increases ~ 30% per year
 Clock frequency increases ~ 20% per year
 Cost per function decreases ~20% per year

Memory
 DRAM capacity: increases ~ 60% per year
(4x every 3 years)
 Speed: increases ~ 10% per year
 Cost per bit: decreases ~25% per year

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 These trends have brought many
changes and new challenges to circuit
design.

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 Complicated Design

Too many transistors and no way to handle them manually.

Solutions:
 CAD
 Hierarchical design
 Design re-use

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 Power and Noise

Huge power consumption and heat dissipation becomes a

problem

Noise and cross talk.

Solutions:
 Better physical design

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 Interconnect Area

Too many interconnects

Solutions:
 More interconnect layers (made possible by Chemical-
Mechanical Polishing)
 CAD tools for 3-D routing

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 Interconnect Delay

Interconnect delay becomes a dominating factor in circuit

performance

Solutions:
 Use copper wire
 Interconnect optimization in physical design, e.g., wire sizing,
buffer insertion, buffer sizing.

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 The Process of Design
Design

Implementation

Debug
Design
Initial concept: what is the function performed by the object?
Constraints: How fast? How much area? How much cost?
Refine abstract functional blocks into more concrete realizations
Implementation
Assemble primitives into more complex building blocks
Composition via wiring
Choose among alternatives to improve the design
Debug
Faulty systems: design flaws, composition flaws, component flaws
Design to make debugging easier
Hypothesis formation and troubleshooting skills

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